Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x160 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
SYNFP Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFMUD : offsetFromMaster Value Update Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The offsetFromMaster value has not been updated.
#1 : 1
The offsetFromMaster value has been updated.
End of enumeration elements list.
INTCHG : Receive logMessageInterval Value Change Detection Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No change in the received logMessageInterval value.
#1 : 1
A change in the received logMessageInterval value.
End of enumeration elements list.
MPDUD : meanPathDelay Value Update Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The meanPathDelay value has not been updated.
#1 : 1
The meanPathDelay value has been updated.
End of enumeration elements list.
DRPTO : Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
A Delay_Resp/Pdelay_Resp timeout has not occurred.
#1 : 1
A Delay_Resp/Pdelay_Resp timeout has occurred.
End of enumeration elements list.
INTDEV : Receive logMessageInterval Value Out-of-Range Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
The received logMessageInterval value is within the range.
#1 : 1
The received logMessageInterval value is out of the range.
End of enumeration elements list.
DRQOVR : Delay_Req Reception FIFO Overflow Detection Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The received Delay_Req has not caused the reception FIFO to overflow.
#1 : 1
The received Delay_Req has caused the reception FIFO to overflow.
End of enumeration elements list.
RECLP : Loop Reception Detection Flag
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
A received message has not returned through a loop.
#1 : 1
A received message has returned through a loop.
End of enumeration elements list.
INFABT : Control Information Abnormality Detection Flag
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No abnormality in control information
#1 : 1
Abnormality in control information
End of enumeration elements list.
RESDN : Response Stop Completion Detection Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stopping responses has not been completed.
#1 : 1
Stopping responses has been completed.
End of enumeration elements list.
GENDN : Generation Stop Completion Detection Flag
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stopping generation has not been completed.
#1 : 1
Stopping generation has been completed.
End of enumeration elements list.
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRU : These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
SYNFP MAC Address Registers
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYMACRU : These bits hold the setting for the higher-order 24 bits of the local MAC address.
bits : 0 - 22 (23 bit)
access : read-write
PTP-primary Message Destination MAC Address Setting Registers
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPMACRU : These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-primary messages.
bits : 0 - 22 (23 bit)
access : read-write
PTP-primary Message Destination MAC Address Setting Registers
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPMACRL : These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-primary messages.
bits : 0 - 22 (23 bit)
access : read-write
PTP-pdelay Message MAC Address Setting Registers
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACRU : These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-pdelay messages.
bits : 0 - 22 (23 bit)
access : read-write
PTP-pdelay Message MAC Address Setting Registers
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACRL : These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-pdelay messages.
bits : 0 - 22 (23 bit)
access : read-write
PTP Message EtherType Setting Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : PTP Message EtherType Value SettingThese bits hold the setting for the EtherType field value for frames in the Ethernet II format.
bits : 0 - 14 (15 bit)
access : read-write
PTP-primary Message Destination IP Address Setting Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPIPR : These bits hold the setting for the destination IP address for PTPprimary messages.
bits : 0 - 30 (31 bit)
access : read-write
PTP-pdelay Message Destination IP Address Setting Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIPR : These bits hold the setting for the destination IP address for PTPpdelay messages.
bits : 0 - 30 (31 bit)
access : read-write
PTP Event Message TOS Setting Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVTO : PTP Event Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP event messages.
bits : 0 - 6 (7 bit)
access : read-write
PTP general Message TOS Setting Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GETO : PTP general Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP general messages.
bits : 0 - 6 (7 bit)
access : read-write
PTP-primary Message TTL Setting Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTL : PTP-primary Message TTL Field Value SettingThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-primary messages.
bits : 0 - 6 (7 bit)
access : read-write
PTP-pdelay Message TTL Setting Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDTL : PTP-pdelay Message TTL Field ValueThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-pdelay messages.
bits : 0 - 6 (7 bit)
access : read-write
PTP Event Message UDP Destination Port Number Setting Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVUPT : PTP Event Message Destination Port Number SettingThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP event messages.
bits : 0 - 14 (15 bit)
access : read-write
PTP general Message UDP Destination Port Number Setting Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEUPT : PTP general Message Destination Port NumberThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP general messages.
bits : 0 - 14 (15 bit)
access : read-write
SYNFP MAC Address Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYMACRL : These bits hold the setting for the lower-order 24 bits of the local MAC address.
bits : 0 - 22 (23 bit)
access : read-write
Frame Reception Filter Setting Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Receive MAC Address SelectNOTE: The setting of these bits is only effective when EXTPRM=0, ENB=1and RPT=1.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Only receive multicast frames matching the MAC address setting in FMAC0R(U/L).
#1 : 1
Only receive multicast frames matching the MAC address setting in FMAC1R(U/L).
End of enumeration elements list.
PRT : Frame Reception EnableNOTE: The setting of these bits is only effective when EXTPRM=0 and ENB=1.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not receive multicast frames.
#1 : 1
See SEL bit.
End of enumeration elements list.
ENB : Reception Filter EnableNOTE: The setting of these bits is only effective when EXTPRM=0.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Filtering is disabled (all multicast frames are received).
#1 : 1
See PRT and SEL bit.
End of enumeration elements list.
EXTPRM : Extended Promiscuous ModeSetting
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation (unicast frames addressed to the EPTPC are received, filtering of PTP frames is applied, multicast filtering is applied, and all broadcast frames are received).
#1 : 1
Extended promiscuous mode (all frames are received)
End of enumeration elements list.
SYNFP LLC-CTL Value Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTL : LLC-CTL FieldThese bits specify the value used for the control field in the LLC sublayer when generating IEEE802.3 frames.
bits : 0 - 6 (7 bit)
access : read-write
SYNFP Local IP Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYIPADDRR : These bits hold the setting for the local IP address.
bits : 0 - 30 (31 bit)
access : read-write
Asymmetric Delay Setting Registers
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DASYMRU : These bits hold the setting for the higher-order 16 bits of the asymmetric delay value.
bits : 0 - 14 (15 bit)
access : read-write
Asymmetric Delay Setting Registers
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DASYMRL : These bits hold the setting for the lower-order 32 bits of the asymmetric delay value.
bits : 0 - 30 (31 bit)
access : read-write
Timestamp Latency Setting Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EGP : Input Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the input ports.
bits : 0 - 14 (15 bit)
access : read-write
INGP : Output Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the output ports.
bits : 16 - 30 (15 bit)
access : read-write
SYNFP Operation Setting Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCYC : PTP Message Transmission Interval SettingThese bits are used to set the time from the completion of one transmission to the start of the next in cycles of the transmission clock. A value n in these bits means that a transmission interval of n cycles will be secured.No interval is secured if the setting is 00h.We recommend the setting 28h (40 cycles).
bits : 0 - 6 (7 bit)
access : read-write
SBDIS : Sync Message Transmission Bandwidth Securing Disable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Securing of the bandwidth for the transmission of SYNC messages is enabled (transfer by the EDMAC is given lower priority).
#1 : 1
Securing of the bandwidth for the transmission of SYNC messages is disabled (transfer by the EDMAC is given higher priority).
End of enumeration elements list.
FILDIS : Receive Message domainNumber Filter Disable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Filtering conditions for the reception of PTP messages include comparison with the domainNumber field.
#1 : 1
Filtering conditions for the reception of PTP messages do not include comparison with the domainNumber field.
End of enumeration elements list.
TCMOD : TC Mode Setting
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
E2E TC
#1 : 1
P2P TC
End of enumeration elements list.
SYNFP Frame Format Setting Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORM0 : Ethernet/UDP Encapsulation
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP directly over Ethernet
#1 : 1
PTP over UDP/IPv4
End of enumeration elements list.
FORM1 : Ethernet Frame Format Setting
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Set this bit to 0 (Ethernet II frame format).
#1 : 1
Setting prohibited
End of enumeration elements list.
Response Message Reception Timeout Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTOUTR : Response Message Reception Timeout Time SettingA response message not being received within n x 1024 (ns), where n is the setting, is judged to represent a timeout.
bits : 0 - 30 (31 bit)
access : read-write
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRU : These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRL : These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
SYNFP Status Notification Permission Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFMUD : SYSR.OFMUD Status Notification Permission
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.OFMUD.
#1 : 1
Permits notification of the state of SYSR.OFMUD.
End of enumeration elements list.
INTCHG : SYSR.INTCHG Status Notification Permission
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.INTCHG.
#1 : 1
Permits notification of the state of SYSR.INTCHG.
End of enumeration elements list.
MPDUD : SYSR.MPDUD Status Notification Permission
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.MPDUD.
#1 : 1
Permits notification of the state of SYSR.MPDUD.
End of enumeration elements list.
DRPTO : SYSR.DRPTO Status Notification Permission
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.DRPTO.
#1 : 1
Permits notification of the state of SYSR.DRPTO.
End of enumeration elements list.
INTDEV : SYSR.INTDEV Status Notification Permission
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.INTDEV.
#1 : 1
Permits notification of the state of SYSR.INTDEV.
End of enumeration elements list.
DRQOVR : SYSR.DRQOVR Status Notification Permission
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.DRQOVR.
#1 : 1
Permits notification of the state of SYSR.DRQOVR.
End of enumeration elements list.
RECLP : SYSR.RECLP Status Notification Permission
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.RECLP.
#1 : 1
Permits notification of the state of SYSR.RECLP.
End of enumeration elements list.
INFABT : SYSR.INFABT Status Notification Permission
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.INFABT.
#1 : 1
Permits notification of the state of SYSR.INFABT.
End of enumeration elements list.
RESDN : SYSR.RESDN Status Notification Permission
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.RESDN.
#1 : 1
Permits notification of the state of SYSR.RESDN.
End of enumeration elements list.
GENDN : SYSR.GENDN Status Notification Permission
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of SYSR.GENDN.
#1 : 1
Permits notification of the state of SYSR.GENDN.
End of enumeration elements list.
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRL : These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
SYNFP Specification Version Setting Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VER : versionPTP Field ValueThese bits are used to set the versionPTP field value of the PTP v2 header.When a message is received, this value is compared with the versionPTP field of the received frame.In generating messages, the value is used for the versionPTP field of the frame for transmission.Set these bits to 0010b (PTP v2).
bits : 0 - 2 (3 bit)
access : read-write
TRSP : transportSpecific Field ValueThese bits are used to set the transportSpecific field value of the PTP v2 header.When a message is received, this value is compared with the transportSpecific field of the received frame.In generating messages, the value is used for the transportSpecific field of the frame for transmission.Set these bits to 0000b (IEEE 1588).
bits : 4 - 6 (3 bit)
access : read-write
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRU : These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRL : These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
SYNFP Domain Number Setting Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DNUM : domainNumber Field Value SettingThese bits are used to set the domainNumber field value of the PTP v2 header.When a message is received, this value is compared with the domainNumber field of the received frame as a condition for PTP reception processing.In generating messages, the value is used for the domainNumber field of the frame for transmission.
bits : 0 - 6 (7 bit)
access : read-write
Announce Message Flag Field Setting Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG0 : leap61This bit is used to set the logical value of the leap61 member of timePropertiesDS.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
leap61 is set to FALSE.
#1 : 1
leap61 is set to TRUE.
End of enumeration elements list.
FLAG1 : leap59This bit is used to set the logical value of the leap59 member of timePropertiesDS.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
leap59 is set to FALSE.
#1 : 1
leap59 is set to TRUE.
End of enumeration elements list.
FLAG2 : currentUtcOffsetValidThis bit is used to set the logical value of the currentUtcOffsetValid member of timePropertiesDS.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
currentUtcOffsetValid is set to FALSE.
#1 : 1
currentUtcOffsetValid is set to TRUE.
End of enumeration elements list.
FLAG3 : ptpTimescaleThis bit is used to set the logical value of the ptpTimescale member of timePropertiesDS.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
ptpTimescale is set to FALSE.
#1 : 1
ptpTimescale is set to TRUE.
End of enumeration elements list.
FLAG4 : timeTraceableThis bit is used to set the logical value of the timeTraceable member of timePropertiesDS.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
timeTraceable is set to FALSE.
#1 : 1
timeTraceable is set to TRUE.
End of enumeration elements list.
FLAG5 : frequencyTraceableThis bit is used to set the logical value of the frequencyTraceable member of timePropertiesDS.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
frequencyTraceable is set to FALSE.
#1 : 1
frequencyTraceable is set to TRUE.
End of enumeration elements list.
FLAG8 : alternateMasterFlag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
alternateMasterFlag is set to FALSE.
#1 : 1
alternateMasterFlag is set to TRUE.
End of enumeration elements list.
FLAG10 : unicastFlag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
unicastFlag is set to FALSE.
#1 : 1
unicastFlag is set to TRUE.
End of enumeration elements list.
FLAG13 : PTP profile Specific 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 1 is set to FALSE.
#1 : 1
PTP profile Specific 1 is set to TRUE.
End of enumeration elements list.
FLAG14 : PTP profile Specific 2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 2 is set to FALSE.
#1 : 1
PTP profile Specific 2 is set to TRUE.
End of enumeration elements list.
Sync Message Flag Field Setting Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG8 : alternateMasterFlag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
alternateMasterFlag is set to FALSE.
#1 : 1
alternateMasterFlag is set to TRUE.
End of enumeration elements list.
FLAG9 : twoStepFlag
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Set this bit to 0 (FALSE).
#1 : 1
Setting prohibited
End of enumeration elements list.
FLAG10 : unicastFlag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
unicastFlag is set to FALSE.
#1 : 1
unicastFlag is set to TRUE.
End of enumeration elements list.
FLAG13 : PTP profile Specific 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 1 is set to FALSE.
#1 : 1
PTP profile Specific 1 is set to TRUE.
End of enumeration elements list.
FLAG14 : PTP profile Specific 2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 2 is set to FALSE.
#1 : 1
PTP profile Specific 2 is set to TRUE.
End of enumeration elements list.
Delay_Req Message Flag Field Setting Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG10 : unicastFlag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
unicastFlag is set to FALSE.
#1 : 1
unicastFlag is set to TRULE.
End of enumeration elements list.
FLAG13 : PTP profile Specific 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 1 is set to FALSE.
#1 : 1
PTP profile Specific 1 is set to TRULE.
End of enumeration elements list.
FLAG14 : PTP profile Specific 2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 2 is set to FALSE.
#1 : 1
PTP profile Specific 2 is set to TRULE.
End of enumeration elements list.
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRU : These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
Frame Reception Filter MAC Address Setting Registers
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMACRL : These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames.
bits : 0 - 22 (23 bit)
access : read-write
Delay_Resp Message Flag Field Setting Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG8 : alternateMasterFlag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
alternateMasterFlag is set to FALSE.
#1 : 1
alternateMasterFlag is set to TRUE.
End of enumeration elements list.
FLAG9 : woStepFlag
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Set this bit to 0 (FALSE).
#1 : 1
Setting prohibited
End of enumeration elements list.
FLAG10 : unicastFlag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
unicastFlag is set to FALSE.
#1 : 1
unicastFlag is set to TRUE.
End of enumeration elements list.
FLAG13 : PTP profile Specific 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 1 is set to FALSE.
#1 : 1
PTP profile Specific 1 is set to TRUE.
End of enumeration elements list.
FLAG14 : PTP profile Specific 2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
PTP profile Specific 2 is set to FALSE.
#1 : 1
PTP profile Specific 2 is set to TRUE.
End of enumeration elements list.
SYNFP Local Clock ID Registers
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYCIDRU : These bits hold the setting for the higher-order 32 bits of the clock-ID of your port.
bits : 0 - 30 (31 bit)
access : read-write
SYNFP Local Clock ID Registers
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYCIDRL : These bits hold the setting for the lower-order 32 bits of the clock-ID of your port.
bits : 0 - 30 (31 bit)
access : read-write
SYNFP Local Port Number Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PNUM : Local Port Number SettingThese bits hold the setting for the port number of the local port.
bits : 0 - 14 (15 bit)
access : read-write
SYNFP Register Value Load Directive Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BMUP : BMC Update
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers holding the MasterClock identifying information.
End of enumeration elements list.
STUP : State Update
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers related to the reception and transmission of PTP messages.
End of enumeration elements list.
ANUP : Announce Message Generation Information Update
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
Setting this bit to 1 leads to simultaneous reflection in the Announce message generation block of the values of the registers required for the generation of Announce messages.
End of enumeration elements list.
SYNFP Reception Filter Register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANCE0 : Announce Message Processing
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
ANCE1 : Announce Message Processing
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
SYNC0 : Sync Message Processing
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
SYNC1 : Sync Message Processing
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
SYNC2 : Sync Message Processing
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP processes messages.
End of enumeration elements list.
FUP0 : Follow_Up Message Processing
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
FUP1 : Follow_Up Message Processing
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
FUP2 : Follow_Up Message Processing
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP processes messages.
End of enumeration elements list.
DRQ0 : Delay_Req Message Processing
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
DRQ1 : Delay_Req Message Processing
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
DRQ2 : Delay_Req Message Processing
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP processes messages.
End of enumeration elements list.
DRP0 : Delay_Resp Message Processing
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
DRP1 : Delay_Resp Message Processing
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
DRP2 : Delay_Resp Message Processing
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP processes messages.
End of enumeration elements list.
PDRQ0 : Pdelay_Req Message Processing
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
PDRQ1 : Pdelay_Req Message Processing
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
PDRQ2 : Pdelay_Req Message Processing
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP processes messages.
End of enumeration elements list.
PDRP0 : Pdelay_Resp Message Processing
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
PDRP1 : Pdelay_Resp Message Processing
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
PDRP2 : Pdelay_Resp Message Processing
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP processes messages.
End of enumeration elements list.
PDFUP0 : Pdelay_Resp_Follow_Up Message Processing
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
PDFUP1 : Pdelay_Resp_Follow_Up Message Processing
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
PDFUP2 : Pdelay_Resp_Follow_Up Message Processing
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
The SYNFP does not process messages.
#1 : 1
The SYNFP does not process messages.
End of enumeration elements list.
SYNFP Reception Filter Register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAN0 : Management Message Processing Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
MAN1 : Management Message Processing Setting
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
SIG0 : Signaling Message Processing Setting
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
SIG1 : Signaling Message Processing Setting
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
ILL0 : Illegal Message Processing Setting
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Messages are not transferred to the PTPEDMAC.
#1 : 1
Messages are transferred to the PTPEDMAC.
End of enumeration elements list.
ILL1 : Illegal Message Processing Setting
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
The PRC-TC does not relay messages between ports 0 and 1.
#1 : 1
The PRC-TC relays messages between ports 0 and 1.
End of enumeration elements list.
SYNFP Transmission Enable Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANCE : Announce Message Transmission Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Announce messages are not transmitted.
#1 : 1
Announce messages are transmitted.
End of enumeration elements list.
SYNC : Sync Message Transmission Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Sync messages are not transmitted.
#1 : 1
Sync messages are transmitted.
End of enumeration elements list.
DRQ : Delay_Req Message Transmission Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay_Req messages are not transmitted.
#1 : 1
Delay_Req messages are transmitted.
End of enumeration elements list.
PDRQ : Pdelay_Req Message Transmission Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pdelay_Req messages are not transmitted.
#1 : 1
Pdelay_Req messages are transmitted.
End of enumeration elements list.
Master Clock ID Registers
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTCIDU : These bits hold the setting for the higher-order 32 bits of the clock-ID of the master clock.
bits : 0 - 30 (31 bit)
access : read-write
Master Clock ID Registers
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTCIDL : These bits hold the setting for the lower-order 32 bits of the clock-ID of the master clock.
bits : 0 - 30 (31 bit)
access : read-write
Master clock port number register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PNUM : Master Clock Port Number SettingThese bits hold the setting for the port number of the master clock.
bits : 0 - 14 (15 bit)
access : read-write
SYNFP Transmission Interval Setting Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANCE : Announce Message Transmission Interval SettingThese bits set the interval for the transmission of Announce messages.
bits : 0 - 6 (7 bit)
access : read-write
SYNC : Sync Message Transmission Interval SettingThese bits set the interval for the transmission of Sync messages. The setting is also placed in the logMessageInterval field of transmitted Sync messages.
bits : 8 - 14 (7 bit)
access : read-write
DREQ : Delay_Req Transmission Interval Average Value/ Pdelay_Req Transmission Interval SettingThe bits set the average interval for the transmission of Delay_Req messages and the interval for the transmission of Pdelay_Req messages.The setting is also placed in the logMessageInterval field of Delay_Resp messages.
bits : 16 - 22 (7 bit)
access : read-write
SYNFP Received logMessageInterval Value Indication Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ANCE : Announce Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Announce message.
bits : 0 - 6 (7 bit)
access : read-only
SYNC : Sync Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Sync message.
bits : 8 - 14 (7 bit)
access : read-only
DRESP : Delay_Resp Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Delay_Resp message.
bits : 16 - 22 (7 bit)
access : read-only
offsetFromMaster Value Registers
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OFMRU : These bits indicate the higher-order 32 bits of the calculated offsetFromMaster value.
bits : 0 - 30 (31 bit)
access : read-only
offsetFromMaster Value Registers
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OFMRL : These bits indicate the lower-order 32 bits of the calculated offsetFromMaster value.
bits : 0 - 30 (31 bit)
access : read-only
meanPathDelay Value Registers
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPDRU : These bits indicate the higher-order 32 bits of the calculated meanPathDelay value.
bits : 0 - 30 (31 bit)
access : read-only
meanPathDelay Value Registers
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPDRL : These bits indicate the lower-order 32 bits of the calculated meanPathDelay value.
bits : 0 - 30 (31 bit)
access : read-only
grandmasterPriority Field Setting Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GMPR2 : grandmasterPriority2 Field Value SettingThese bits are used to set the value of the grandmasterPriority2 fields of Announce messages.
bits : 0 - 6 (7 bit)
access : read-write
GMPR1 : grandmasterPriority1 Field Value SettingThese bits are used to set the value of the grandmasterPriority1 fields of Announce messages.
bits : 16 - 22 (7 bit)
access : read-write
grandmasterClockQuality Field Setting Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GMCQR : These bits are used to set the value of the grandmasterClockQuality fields of Announce messages. The correspondence between bits and the grandmasterClockQuality fields is as listed below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 to b0: offsetScaledLogVariance
bits : 0 - 30 (31 bit)
access : read-write
grandmasterIdentity Field Setting Registers
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GMIDRU : These bits hold the setting for the higher-order 32 bits of the value of the grandmasterIdentity fields of Announce messages.
bits : 0 - 30 (31 bit)
access : read-write
grandmasterIdentity Field Setting Registers
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GMIDRL : These bits hold the setting for the lower-order 32 bits of the value of the grandmasterIdentity fields of Announce messages.
bits : 0 - 30 (31 bit)
access : read-write
currentUtcOffset/timeSource Field Setting Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSRC : timeSource Field SettingThese bits set the value of the timeSource fields of Announce messages.
bits : 0 - 6 (7 bit)
access : read-write
CUTO : currentUtcOffset Field SettingThese bits set the value of the currentUtcOffset fields of Announce messages.
bits : 16 - 30 (15 bit)
access : read-write
stepsRemoved Field Setting Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRMV : stepsRemoved Field Value SettingThese bits set the value of the stepsRemoved fields of Announce messages.
bits : 0 - 14 (15 bit)
access : read-write
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