Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
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protection : not protected
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size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
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TM[5]-TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-STTRU
TM[5]-TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-STTRL
TM[5]-TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-CYCR
TM[5]-TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-PLSR
TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-STTRU
TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-STTRL
TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-CYCR
TM[4]-TM[3]-TM[2]-TM[1]-TM[0]-PLSR
MINT Interrupt Source Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : STCA Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No change in the state of the STCA module
#1 : 1
A change in the state of the STCA module
End of enumeration elements list.
SY0 : SYNFP0 Status Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
No change in the state of the SYNFP0 module
#1 : 1
A change in the state of the SYNFP0 module
End of enumeration elements list.
SY1 : SYNFP1 Status Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No change in the state of the SYNFP1 module
#1 : 1
A change in the state of the SYNFP1 module
End of enumeration elements list.
PRC : PRC-TC Status Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
No change in the state of the PRC-TC module
#1 : 1
A change in the state of the PRC-TC module
End of enumeration elements list.
CYC0 : Pulse Output Timer 0 Rising Edge Detection Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge in the periodic pulse signal from pulse output timer 0 is not detected.
#1 : 1
A rising edge in the periodic pulse signal from pulse output timer 0 is detected.
End of enumeration elements list.
CYC1 : Pulse Output Timer 1 Rising Edge Detection Flag
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge in the periodic pulse signal from pulse output timer 1 is not detected.
#1 : 1
A rising edge in the periodic pulse signal from pulse output timer 1 is detected.
End of enumeration elements list.
CYC2 : Pulse Output Timer 2 Rising Edge Detection Flag
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge in the periodic pulse signal from pulse output timer 2 is not detected.
#1 : 1
A rising edge in the periodic pulse signal from pulse output timer 2 is detected.
End of enumeration elements list.
CYC3 : Pulse Output Timer 3 Rising Edge Detection Flag
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge in the periodic pulse signal from pulse output timer 3 is not detected.
#1 : 1
A rising edge in the periodic pulse signal from pulse output timer 3 is detected.
End of enumeration elements list.
CYC4 : Pulse Output Timer 4 Rising Edge Detection Flag
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge in the periodic pulse signal from pulse output timer 4 is not detected.
#1 : 1
A rising edge in the periodic pulse signal from pulse output timer 4 is detected.
End of enumeration elements list.
CYC5 : Pulse Output Timer 5 Rising Edge Detection Flag
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge in the periodic pulse signal from pulse output timer 5 is not detected.
#1 : 1
A rising edge in the periodic pulse signal from pulse output timer 5 is detected.
End of enumeration elements list.
Timer Start Time Setting Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Channel Local MAC Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMACRU : These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
bits : 0 - 22 (23 bit)
access : read-write
ELC Output/ETHER_IPLS Interrupt Request Permission Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCP0 : Pulse Output Timer 0 Rising Edge Detection Event Output Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rising edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals.
#1 : 1
Rising edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCP1 : Pulse Output Timer 1 Rising Edge Detection Event Output Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rising edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals.
#1 : 1
Rising edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCP2 : Pulse Output Timer 2 Rising Edge Detection Event Output Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rising edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals.
#1 : 1
Rising edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCP3 : Pulse Output Timer 3 Rising Edge Detection Event Output Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rising edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals.
#1 : 1
Rising edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCP4 : Pulse Output Timer 4 Rising Edge Detection Event Output Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rising edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals.
#1 : 1
Rising edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCP5 : Pulse Output Timer 5 Rising Edge Detection Event Output Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Rising edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals.
#1 : 1
Rising edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCN0 : Pulse Output Timer 0 Falling Edge Detection Event Output Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals.
#1 : 1
Falling edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCN1 : Pulse Output Timer 1 Falling Edge Detection Event Output Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals.
#1 : 1
Falling edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCN2 : Pulse Output Timer 2 Falling Edge Detection Event Output Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals.
#1 : 1
Falling edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCN3 : Pulse Output Timer 3 Falling Edge Detection Event Output Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals.
#1 : 1
Falling edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCN4 : Pulse Output Timer 4 Falling Edge Detection Event Output Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals.
#1 : 1
Falling edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals.
End of enumeration elements list.
CYCN5 : Pulse Output Timer 5 Falling Edge Detection Event Output Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals.
#1 : 1
Falling edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals.
End of enumeration elements list.
PLSP : Pulse Output Timer Rising Edge Detection IPLS Interrupt Request Permission
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer.
#1 : 1
Permits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer.
End of enumeration elements list.
PLSN : Pulse Output Timer Falling Edge Detection IPLS Interrupt Request Permission
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer.
#1 : 1
Permits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer.
End of enumeration elements list.
Worst 10 Acquisition Directive Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GW10 : Worst 10 Acquisition Directive
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The worst-10 values are not acquired.
#1 : 1
Starts acquisition of the worst-10 values.
End of enumeration elements list.
Positive Gradient Limit Registers
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLIMITRU : These bits hold the setting for the higher-order 31 bits of the limit for the positive gradient.
bits : 0 - 29 (30 bit)
access : read-write
Positive Gradient Limit Registers
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLIMITRM : These bits hold the setting for the middle-order 32 bits of the limit for the positive gradient.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0x12F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0x12F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Cycle Setting Registers
address_offset : 0x12F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0x12FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
Positive Gradient Limit Registers
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLIMITRL : These bits hold the setting for the lower-order 32 bits of the limit for the positive gradient.
bits : 0 - 30 (31 bit)
access : read-write
Negative Gradient Limit Registers
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MLIMITRU : These bits hold the setting for the higher-order 31 bits of the limit for the negative gradient.
bits : 0 - 29 (30 bit)
access : read-write
Negative Gradient Limit Registers
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MLIMITRM : These bits hold the setting for the middle-order 32 bits of the limit for the negative gradient.
bits : 0 - 30 (31 bit)
access : read-write
Negative Gradient Limit Registers
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MLIMITRL : These bits hold the setting for the lower-order 32 bits of the limit for the negative gradient.
bits : 0 - 30 (31 bit)
access : read-write
ELC Output/IPLS Interrupt Permission Automatic Clearing Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCP0 : ELIPPR.CYCP0 Bit Automatic Clearing
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0.
#1 : 1
Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0.
End of enumeration elements list.
CYCP1 : ELIPPR.CYCP1 Bit Automatic Clearing
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1.
#1 : 1
Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1.
End of enumeration elements list.
CYCP2 : ELIPPR.CYCP2 Bit Automatic Clearing
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2.
#1 : 1
Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2.
End of enumeration elements list.
CYCP3 : ELIPPR.CYCP3 Bit Automatic Clearing
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3.
#1 : 1
Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3.
End of enumeration elements list.
CYCP4 : ELIPPR.CYCP4 Bit Automatic Clearing
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4.
#1 : 1
Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4.
End of enumeration elements list.
CYCP5 : ELIPPR.CYCP5 Bit Automatic Clearing
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5.
#1 : 1
Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5.
End of enumeration elements list.
CYCN0 : ELIPPR.CYCN0 Bit Automatic Clearing
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0.
#1 : 1
Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0.
End of enumeration elements list.
CYCN1 : ELIPPR.CYCN1 Bit Automatic Clearing
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1.
#1 : 1
Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1.
End of enumeration elements list.
CYCN2 : ELIPPR.CYCN2 Bit Automatic Clearing
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2.
#1 : 1
Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2.
End of enumeration elements list.
CYCN3 : ELIPPR.CYCN3 Bit Automatic Clearing
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3.
#1 : 1
Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3.
End of enumeration elements list.
CYCN4 : ELIPPR.CYCN4 Bit Automatic Clearing
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4.
#1 : 1
Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4.
End of enumeration elements list.
CYCN5 : ELIPPR.CYCN5 Bit Automatic Clearing
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5.
#1 : 1
Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5.
End of enumeration elements list.
PLSP : ELIPPR.PLSP Bit Automatic Clearing
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
#1 : 1
Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
End of enumeration elements list.
PLSN : ELIPPR.PLSN Bit Automatic Clearing
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
#1 : 1
Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
End of enumeration elements list.
Statistical Information Retention Control Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFO : Information Retention ControlNOTE: Once information fetching is directed, values of various statistical information read before completion of information fetching are not guaranteed.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Has no effects.(write) / Information retention is completed.(read)
#1 : 1
Information is retained.(write) / Processing for information retention is in progress.(read)
End of enumeration elements list.
Local Time Counters
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LCCVRU : These bits are for reading the higher-order 16 bits of the integer portion of the local timer counter's value.
bits : 0 - 14 (15 bit)
access : read-only
Local Time Counters
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LCCVRM : These bits are for reading the lower-order 32 bits of the integer portion of the local timer counter's value.
bits : 0 - 30 (31 bit)
access : read-only
Local Time Counters
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LCCVRL : These bits are for reading the fractional portion of the local timer counter's value (in nanoseconds).
bits : 0 - 30 (31 bit)
access : read-only
Positive Gradient Worst 10 Value Registers
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PW10VRU : These bits are for reading the higher-order 32 bits of the positive gradient value.
bits : 0 - 30 (31 bit)
access : read-only
Positive Gradient Worst 10 Value Registers
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PW10VRM : These bits are for reading the middle-order 32 bits of the positive gradient value.
bits : 0 - 30 (31 bit)
access : read-only
Positive Gradient Worst 10 Value Registers
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PW10VRL : These bits are for reading the lower-order 32 bits of the positive gradient value.
bits : 0 - 30 (31 bit)
access : read-only
Negative Gradient Worst 10 Value Registers
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MW10RU : These bits are for reading the higher-order 32 bits of the negative gradient value.
bits : 0 - 30 (31 bit)
access : read-only
Negative Gradient Worst 10 Value Registers
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MW10RM : These bits are for reading the middle-order 32 bits of the negative gradient value.
bits : 0 - 30 (31 bit)
access : read-only
Negative Gradient Worst 10 Value Registers
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MW10RL : These bits are for reading the lower-order 32 bits of the negative gradient value.
bits : 0 - 30 (31 bit)
access : read-only
Timer Start Time Setting Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Cycle Setting Registers
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
Timer Start Register
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN0 : Pulse Output Timer 0 Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops pulse output timer 0.
#1 : 1
Starts pulse output timer 0.
End of enumeration elements list.
EN1 : Pulse Output Timer 1 Start
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops pulse output timer 1.
#1 : 1
Starts pulse output timer 1.
End of enumeration elements list.
EN2 : Pulse Output Timer 2 Start
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops pulse output timer 2.
#1 : 1
Starts pulse output timer 2.
End of enumeration elements list.
EN3 : Pulse Output Timer 3 Start
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops pulse output timer 3.
#1 : 1
Starts pulse output timer 3.
End of enumeration elements list.
EN4 : Pulse Output Timer 4 Start
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops pulse output timer 4.
#1 : 1
Starts pulse output timer 4.
End of enumeration elements list.
EN5 : Pulse Output Timer 5 Start
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stops pulse output timer 5.
#1 : 1
Starts pulse output timer 5.
End of enumeration elements list.
MINT Interrupt Request Permission Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : STCA Status Interrupt Request Permission
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests by the STCA status flag.
#1 : 1
Permits the generation of MINT interrupt requests by the STCA status flag.
End of enumeration elements list.
SY0 : SYNFP0 Status Interrupt Request Permission
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests by the SYNFP0 status flag.
#1 : 1
Permits the generation of MINT interrupt requests by the SYNFP0 status flag.
End of enumeration elements list.
SY1 : SYNFP1 Status Interrupt Request Permission
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests by the SYNFP1 status flag.
#1 : 1
Permits the generation of MINT interrupt requests by the SYNFP1 status flag.
End of enumeration elements list.
PRC : PRC-TC Status Interrupt Request Permission
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests by the PRC-TC status flag.
#1 : 1
Permits the generation of MINT interrupt requests by the PRCTC status flag.
End of enumeration elements list.
CYC0 : Pulse Output Timer 0 Rising Edge Detection Interrupt Request Permission
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0.
#1 : 1
Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0.
End of enumeration elements list.
CYC1 : Pulse Output Timer 1 Rising Edge Detection Interrupt Request Permission
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1.
#1 : 1
Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1.
End of enumeration elements list.
CYC2 : Pulse Output Timer 2 Rising Edge Detection Interrupt Request Permission
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2.
#1 : 1
Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2.
End of enumeration elements list.
CYC3 : Pulse Output Timer 3 Rising Edge Detection Interrupt Request Permission
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3.
#1 : 1
Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3.
End of enumeration elements list.
CYC4 : Pulse Output Timer 4 Rising Edge Detection Interrupt Request Permission
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4.
#1 : 1
Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4.
End of enumeration elements list.
CYC5 : Pulse Output Timer 5 Rising Edge Detection Interrupt Request Permission
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5.
#1 : 1
Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5.
End of enumeration elements list.
Timer Start Time Setting Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Channel Local MAC Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMACRL : These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
bits : 0 - 22 (23 bit)
access : read-write
STCA Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchronized State Detection Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Synchronization not detected
#1 : 1
Synchronization detected
End of enumeration elements list.
SYNCOUT : Synchronization Loss Detection Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Loss of synchronization not detected
#1 : 1
Loss of synchronization detected
End of enumeration elements list.
SYNTOUT : Sync Message Reception Timeout Detection Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Sync message reception timeout not detected
#1 : 1
Sync message reception timeout detected
End of enumeration elements list.
W10D : Worst 10 Acquisition Completion Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Ten worst values not acquired yet
#1 : 1
Ten worst values acquired
End of enumeration elements list.
PRC-TC Status Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRE0 : Relay Packet Overflow Detection Flag 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow in transfer of data from SYNFP1 to PTPEDMAC.
#1 : 1
An overflow has been detected in transfer of data from SYNFP1 to PTPEDMAC.
End of enumeration elements list.
OVRE1 : Relay Packet Overflow Detection Flag 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow in transfer of data from SYNFP0 to PTPEDMAC.
#1 : 1
An overflow has been detected in transfer of data from SYNFP0 to PTPEDMAC.
End of enumeration elements list.
OVRE2 : Relay Packet Overflow Detection Flag 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow in transfer of data from SYNFP1 to SYNFP0.
#1 : 1
An overflow has been detected in transfer of data from SYNFP1 to SYNFP0.
End of enumeration elements list.
OVRE3 : Relay Packet Overflow Detection Flag 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow in transfer of data from SYNFP0 to SYNFP1.
#1 : 1
An overflow has been detected in transfer of data from SYNFP0 to SYNFP1.
End of enumeration elements list.
MACE : Originating MAC Address Mismatch Detection Flag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
A MAC address mismatch has not been detected.
#1 : 1
A MAC address mismatch has been detected.
End of enumeration elements list.
URE0 : Relay Packet Underflow Detection Flag 0
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
No underflow in transfer of data from SYNFP1 to SYNFP0.
#1 : 1
An underflow has been detected in transfer of data from SYNFP1 to SYNFP0.
End of enumeration elements list.
URE1 : Relay Packet Underflow Detection Flag 1
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
No underflow in transfer of data from SYNFP0 to SYNFP1.
#1 : 1
An underflow has been detected in transfer of data from SYNFP0 to SYNFP1.
End of enumeration elements list.
PRC-TC Status Notification Permission Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRE0 : PRSR.OVRE0 Status Notification Permission
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.OVRE0.
#1 : 1
Permits notification of the state of PRSR.OVRE0.
End of enumeration elements list.
OVRE1 : PRSR.OVRE1 Status Notification Permission
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.OVRE1.
#1 : 1
Permits notification of the state of PRSR.OVRE1.
End of enumeration elements list.
OVRE2 : PRSR.OVRE2 Status Notification Permission
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.OVRE2.
#1 : 1
Permits notification of the state of PRSR.OVRE2.
End of enumeration elements list.
OVRE3 : PRSR.OVRE3 Status Notification Permission
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.OVRE3.
#1 : 1
Permits notification of the state of PRSR.OVRE3.
End of enumeration elements list.
MACE : PRSR.MACE Status Notification Permission
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.MACE
#1 : 1
Permits notification of the state of PRSR.MACE
End of enumeration elements list.
URE0 : PRSR.URE0 Status Notification Permission
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.URE0.
#1 : 1
Permits notification of the state of PRSR.URE0.
End of enumeration elements list.
URE1 : PRSR.URE1 Status Notification Permission
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Prohibits notification of the state of PRSR.URE1.
#1 : 1
Permits notification of the state of PRSR.URE1.
End of enumeration elements list.
Channel Local MAC Address Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMACRU : These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
bits : 0 - 22 (23 bit)
access : read-write
Channel Local MAC Address Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMACRL : These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
bits : 0 - 22 (23 bit)
access : read-write
Packet Transmission Control Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIS : Packet Transmission Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
PTP packets are transmitted through both Ethernet port 0 and Ethernet port 1.
#01 : 01
PTP packets are only transmitted through Ethernet port 0.
#10 : 10
PTP packets are only transmitted through Ethernet port 1.
#11 : 11
Setting prohibited
End of enumeration elements list.
Relay Mode Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : Cut-Through Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Store-and-forward
#1 : 1
Cut-through
End of enumeration elements list.
FWD0 : Channel 0 Relay Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 0 to port 1.
#1 : 1
Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 0 to port 1.
End of enumeration elements list.
FWD1 : Channel 1 Relay Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 1 to port 0.
#1 : 1
Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 1 to port 0.
End of enumeration elements list.
Cut-Through Transfer Start Threshold Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THVAL : FIFO Read Start ThresholdThreshold for starting to read data from the relay FIFO in cut-through mode (specified as the number of bytes)NOTE1: A value cannot be set in the lower-order 2 bits. These bits are fixed to 0.NOTE2: A value of less than 96 bytes cannot be set.
bits : 0 - 9 (10 bit)
access : read-write
STCA Status Notification Permission Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC : SYNC Status Notification Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable notification of the STSR.SYNC state
#1 : 1
Enable notification of the STSR.SYNC state
End of enumeration elements list.
SYNCOUT : SYNCOUT Status Notification Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable notification of the STSR.SYNCOUT state
#1 : 1
Enable notification of the STSR.SYNCOUT state
End of enumeration elements list.
SYNTOUT : SYNTOUT Status Notification Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable notification of the STSR.SYNTOUT state
#1 : 1
Enable notification of the STSR.SYNTOUT state
End of enumeration elements list.
W10D : W10D Status Notification Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable notification of the STSR.W10D state
#1 : 1
Enable notification of the STSR.W10D state
End of enumeration elements list.
STCA Clock Frequency Setting Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCF : STCA Clock Frequency
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
20MHz
#01 : 01
25MHz
#10 : 10
50MHz
#11 : 11
100 MHz
End of enumeration elements list.
STCA Operating Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINT : Worst 10 Acquisition Time
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x00 : 0x00
The worst 10 values are not acquired.
: others
Sync message reception: (WINT) time
End of enumeration elements list.
CMOD : Time Synchronization Correction Mode
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Mode 1
#1 : 1
Mode 2
End of enumeration elements list.
W10S : Worst 10 Acquisition Control Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Measurement is started by hardware and the value acquired in the PW10VR or MW10R register is used as the limit for filtering.
#1 : 1
Measurement is started by the GETW10R.GW10 bit. Also, the value set in the PLIMITR or MLIMITR register is used as the limit for filtering.
End of enumeration elements list.
SYTH : Synchronized State Detection Threshold Setting
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
None
: others
(SYTH) time
End of enumeration elements list.
DVTH : Synchronization Loss Detection Threshold Setting
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
None
: others
(DVTH) time
End of enumeration elements list.
ALEN0 : Alarm Detection Enable 0
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
The STSR.SYNC or SYNCOUT flag is not set to 1 on detection of synchronization or loss of synchronization.
#1 : 1
The STSR.SYNC or SYNCOUT flag is set to 1 on detection of synchronization or loss of synchronization.
End of enumeration elements list.
ALEN1 : Alarm Detection Enable 1
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt.
#1 : 1
The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt.
End of enumeration elements list.
Sync Message Reception Timeout Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTOR : A Sync message not being received within 1024 x n (ns), where n is the setting, leads to a timeout for reception of Sync messages, leading to the STSR.SYNTOUT flag being set to 1.
bits : 0 - 30 (31 bit)
access : read-write
IPLS Interrupt Request Timer Select Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPTSEL0 : Pulse Output Timer 0 Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 0 is not selected as a source of IPLS interrupt requests.
#1 : 1
Pulse output timer 0 is selected as a source of IPLS interrupt requests.
End of enumeration elements list.
IPTSEL1 : Pulse Output Timer 1 Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 1 is not selected as a source of IPLS interrupt requests.
#1 : 1
Pulse output timer 1 is selected as a source of IPLS interrupt requests.
End of enumeration elements list.
IPTSEL2 : Pulse Output Timer 2 Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 2 is not selected as a source of IPLS interrupt requests.
#1 : 1
Pulse output timer 2 is selected as a source of IPLS interrupt requests.
End of enumeration elements list.
IPTSEL3 : Pulse Output Timer 3 Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 3 is not selected as a source of IPLS interrupt requests.
#1 : 1
Pulse output timer 3 is selected as a source of IPLS interrupt requests.
End of enumeration elements list.
IPTSEL4 : Pulse Output Timer 4 Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 4 is not selected as a source of IPLS interrupt requests.
#1 : 1
Pulse output timer 4 is selected as a source of IPLS interrupt requests.
End of enumeration elements list.
IPTSEL5 : Pulse Output Timer 5 Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 5 is not selected as a source of IPLS interrupt requests.
#1 : 1
Pulse output timer 5 is selected as a source of IPLS interrupt requests.
End of enumeration elements list.
Timer Start Time Setting Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Cycle Setting Registers
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
MINT Interrupt Request Timer Select Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MINTEN0 : Pulse Output Timer 0 MINT Interrupt Output Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output of rising edges by pulse output timer 0 is not reflected by the MIESR.CYC0 flag as a MINT interrupt source.
#1 : 1
Output of rising edges by pulse output timer 0 is reflected by the MIESR.CYC0 flag as a MINT interrupt source.
End of enumeration elements list.
MINTEN1 : Pulse Output Timer 1 MINT Interrupt Output Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output of rising edges by pulse output timer 1 is not reflected by the MIESR.CYC1 flag as a MINT interrupt source.
#1 : 1
Output of rising edges by pulse output timer 1 is reflected by the MIESR.CYC1 flag as a MINT interrupt source.
End of enumeration elements list.
MINTEN2 : Pulse Output Timer 2 MINT Interrupt Output Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output of rising edges by pulse output timer 2 is not reflected by the MIESR.CYC2 flag as a MINT interrupt source.
#1 : 1
Output of rising edges by pulse output timer 2 is reflected by the MIESR.CYC2 flag as a MINT interrupt source.
End of enumeration elements list.
MINTEN3 : Pulse Output Timer 3 MINT Interrupt Output Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output of rising edges by pulse output timer 3 is not reflected by the MIESR.CYC3 flag as a MINT interrupt source.
#1 : 1
Output of rising edges by pulse output timer 3 is reflected by the MIESR.CYC3 flag as a MINT interrupt source.
End of enumeration elements list.
MINTEN4 : Pulse Output Timer 4 MINT Interrupt Output Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output of rising edges by pulse output timer 4 is not reflected by the MIESR.CYC4 flag as a MINT interrupt source.
#1 : 1
Output of rising edges by pulse output timer 4 is reflected by the MIESR.CYC4 flag as a MINT interrupt source.
End of enumeration elements list.
MINTEN5 : Pulse Output Timer 5 MINT Interrupt Output Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output of rising edges by pulse output timer 5 is not reflected by the MIESR.CYC5 flag as a MINT interrupt source.
#1 : 1
Output of rising edges by pulse output timer 5 is reflected by the MIESR.CYC5 flag as a MINT interrupt source.
End of enumeration elements list.
ELC Output Timer Select Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELTDIS0 : Pulse Output Timer 0 Event Generation Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 0 is used for the generation of event signals for the ELC.
#1 : 1
Pulse output timer 0 is not used for the generation of event signals for the ELC.
End of enumeration elements list.
ELTDIS1 : Pulse Output Timer 1 Event Generation Disable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 1 is used for the generation of event signals for the ELC.
#1 : 1
Pulse output timer 1 is not used for the generation of event signals for the ELC.
End of enumeration elements list.
ELTDIS2 : Pulse Output Timer 2 Event Generation Disable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 2 is used for the generation of event signals for the ELC.
#1 : 1
Pulse output timer 2 is not used for the generation of event signals for the ELC.
End of enumeration elements list.
ELTDIS3 : Pulse Output Timer 3 Event Generation Disable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 3 is used for the generation of event signals for the ELC.
#1 : 1
Pulse output timer 3 is not used for the generation of event signals for the ELC.
End of enumeration elements list.
ELTDIS4 : Pulse Output Timer 4 Event Generation Disable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 4 is used for the generation of event signals for the ELC.
#1 : 1
Pulse output timer 4 is not used for the generation of event signals for the ELC.
End of enumeration elements list.
ELTDIS5 : Pulse Output Timer 5 Event Generation Disable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pulse output timer 5 is used for the generation of event signals for the ELC.
#1 : 1
Pulse output timer 5 is not used for the generation of event signals for the ELC.
End of enumeration elements list.
Time Synchronization Channel Select Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSEL : Timer Information Input SelectNOTE: Do not change the value of this bit while the SYNSTARTR.STR bit is 1.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Time information from synchronization from the SYNFP0 module is used.
#1 : 1
Time information from synchronization from the SYNFP1 module is used.
End of enumeration elements list.
Timer Cycle Setting Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Slave Time Synchronization Start Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STR : Slave Time Synchronization Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave time synchronization is stopped.
#1 : 1
Slave time synchronization is started.
End of enumeration elements list.
Channel Local MAC Address Register
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMACRU : These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
bits : 0 - 22 (23 bit)
access : read-write
Channel Local MAC Address Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMACRL : These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
bits : 0 - 22 (23 bit)
access : read-write
Local Time Counter Initial Value Load Directive Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOAD : Local Time Counter Initial Value Load Directive
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
The initial value is not loaded into the local time counter.
#1 : 1
The initial value is loaded into the local time counter.
End of enumeration elements list.
Synchronization Loss Detection Threshold Registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTDARU : These bits hold the setting for the higher-order 32 bits of the threshold for detection of loss of synchronization.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Cycle Setting Registers
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0x93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
Synchronization Loss Detection Threshold Registers
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTDARL : These bits hold the setting for the lower-order 32 bits of the threshold for detection of loss of synchronization.
bits : 0 - 30 (31 bit)
access : read-write
Synchronization Detection Threshold Registers
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTDBRU : These bits hold the setting for the higher-order 32 bits of the threshold for detection of synchronization.
bits : 0 - 30 (31 bit)
access : read-write
Synchronization Detection Threshold Registers
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNTDBRL : These bits hold the setting for the lower-order 32 bits of the threshold for detection of synchronization.
bits : 0 - 30 (31 bit)
access : read-write
Local Time Counter Initial Value Registers
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCIVRU : These bits hold the setting for the higher-order 16 bits of the integer portion of the initial value for the local timer counter.
bits : 0 - 14 (15 bit)
access : read-write
Local Time Counter Initial Value Registers
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCIVRM : These bits hold the setting for the lower-order 32 bits of the integer portion of the initial value for the local timer counter.
bits : 0 - 30 (31 bit)
access : read-write
Local Time Counter Initial Value Registers
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCIVRL : These bits hold the setting for the fractional portion of the initial value of the local timer counter in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0xC60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0xC64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Cycle Setting Registers
address_offset : 0xC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0xC6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRU : These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Start Time Setting Register
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSTTRL : These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
bits : 0 - 30 (31 bit)
access : read-write
Timer Cycle Setting Registers
address_offset : 0xFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMCYCR : These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
bits : 0 - 28 (29 bit)
access : read-write
Timer Pulse Width Setting Register
address_offset : 0xFAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPLSR : These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
bits : 0 - 27 (28 bit)
access : read-write
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