\n
address_offset : 0x100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x11C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
Flash Cache Enable Register
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCACHEEN : FCACHE Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable FCACHE
#1 : 1
Enable FCACHE
End of enumeration elements list.
Flash Cache Invalidate Register
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCACHEIV : Flash Cache Invalidate Register
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not invalidate reads, setting ignored on writes
#1 : 1
Invalidate on reads and writes.
End of enumeration elements list.
Flash Wait Cycle Register
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLWT : Flash Wait Cycle
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
0 waits (ICLK <= 80 MHz)
#001 : 001
1 wait (80 MHz < ICLK <= 160 MHz)
#010 : 010
2 waits (160 MHz < ICLK <= 240 MHz).
End of enumeration elements list.
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