Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA4 byte (0x0)
mem_usage : registers
protection : not protected
General PWM Timer Write-Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WP : Register Write Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write to the register is enabled
#1 : 1
Write to the register is disabled
End of enumeration elements list.
PRKEY : GTWP Key Code
bits : 8 - 14 (7 bit)
access : write-only
Enumeration:
0xA5 : 0xA5
Written to these bits, the WP bits write is permitted.
: others
The WP bits write is not permitted.
End of enumeration elements list.
General PWM Timer Start Source Select Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSGTRGAR : GTETRG Pin Rising Input Source Counter Start Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTETRG input
#1 : 1
Counter start is enable at the rising edge of GTETRG input
End of enumeration elements list.
SSGTRGAF : GTETRG Pin Falling Input Source Counter Start Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTETRG input
#1 : 1
Counter start is enable at the falling edge of GTETRG input
End of enumeration elements list.
SSGTRGBR : GTETRG Pin Rising Input Source Counter Start Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTETRG input
#1 : 1
Counter start is enable at the rising edge of GTETRG input
End of enumeration elements list.
SSGTRGBF : GTETRG Pin Falling Input Source Counter Start Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTETRG input
#1 : 1
Counter start is enable at the falling edge of GTETRG input
End of enumeration elements list.
SSGTRGCR : GTETRG Pin Rising Input Source Counter Start Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTETRG input
#1 : 1
Counter start is enable at the rising edge of GTETRG input
End of enumeration elements list.
SSGTRGCF : GTETRG Pin Falling Input Source Counter Start Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTETRG input
#1 : 1
Counter start is enable at the falling edge of GTETRG input
End of enumeration elements list.
SSGTRGDR : GTETRG Pin Rising Input Source Counter Start Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTETRG input
#1 : 1
Counter start is enable at the rising edge of GTETRG input
End of enumeration elements list.
SSGTRGDF : GTETRG Pin Falling Input Source Counter Start Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTETRG input
#1 : 1
Counter start is enable at the falling edge of GTETRG input
End of enumeration elements list.
SSCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
SSCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
SSCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
SSCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
SSCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
SSCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
SSCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
SSCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
SSELCA : ELC_GPT Event Source Counter Start Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCB : ELC_GPT Event Source Counter Start Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCC : ELC_GPT Event Source Counter Start Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCD : ELC_GPT Event Source Counter Start Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCE : ELC_GPT Event Source Counter Start Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCF : ELC_GPT Event Source Counter Start Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCG : ELC_GPT Event Source Counter Start Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
SSELCH : ELC_GPT Event Source Counter Start Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable at the ELC_GPT input
#1 : 1
Counter start is enable at the ELC_GPT input
End of enumeration elements list.
CSTRT : Software Source Counter Start Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start is disable by the GTSTR register
#1 : 1
Counter start is enable by the GTSTR register
End of enumeration elements list.
General PWM Timer Compare Capture Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCCR : Compare Capture Register A
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Stop Source Select Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSGTRGAR : GTETRG Pin Rising Input Source Counter Stop Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTETRG input
#1 : 1
Counter stop is enable at the rising edge of GTETRG input
End of enumeration elements list.
PSGTRGAF : GTETRG Pin Falling Input Source Counter Stop Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTETRG input
#1 : 1
Counter stop is enable at the falling edge of GTETRG input
End of enumeration elements list.
PSGTRGBR : GTETRG Pin Rising Input Source Counter Stop Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTETRG input
#1 : 1
Counter stop is enable at the rising edge of GTETRG input
End of enumeration elements list.
PSGTRGBF : GTETRG Pin Falling Input Source Counter Stop Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTETRG input
#1 : 1
Counter stop is enable at the falling edge of GTETRG input
End of enumeration elements list.
PSGTRGCR : GTETRG Pin Rising Input Source Counter Stop Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTETRG input
#1 : 1
Counter stop is enable at the rising edge of GTETRG input
End of enumeration elements list.
PSGTRGCF : GTETRG Pin Falling Input Source Counter Stop Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTETRG input
#1 : 1
Counter stop is enable at the falling edge of GTETRG input
End of enumeration elements list.
PSGTRGDR : GTETRG Pin Rising Input Source Counter Stop Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTETRG input
#1 : 1
Counter stop is enable at the rising edge of GTETRG input
End of enumeration elements list.
PSGTRGDF : GTETRG Pin Falling Input Source Counter Stop Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTETRG input
#1 : 1
Counter stop is enable at the falling edge of GTETRG input
End of enumeration elements list.
PSCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
PSCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
PSCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
PSCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
PSCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
PSCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
PSCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
PSCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
PSELCA : ELC_GPTA Event Source Counter Stop Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCB : ELC_GPTA Event Source Counter Stop Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCC : ELC_GPTA Event Source Counter Stop Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCD : ELC_GPTA Event Source Counter Stop Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCE : ELC_GPTA Event Source Counter Stop Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCF : ELC_GPTA Event Source Counter Stop Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCG : ELC_GPTA Event Source Counter Stop Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
PSELCH : ELC_GPTA Event Source Counter Stop Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable at the ELC_GPTA input
#1 : 1
Counter stop is enable at the ELC_GPTA input
End of enumeration elements list.
CSTOP : Software Source Counter Stop Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop is disable by the GTSTP register
#1 : 1
Counter stop is enable by the GTSTP register
End of enumeration elements list.
General PWM Timer Clear Source Select Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGTRGAR : GTETRG Pin Rising Input Source Counter Clear Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTETRG input
#1 : 1
Counter clear is enable at the rising edge of GTETRG input
End of enumeration elements list.
CSGTRGAF : GTETRG Pin Falling Input Source Counter Clear Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTETRG input
#1 : 1
Counter clear is enable at the falling edge of GTETRG input
End of enumeration elements list.
CSGTRGBR : GTETRG Pin Rising Input Source Counter Clear Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTETRG input
#1 : 1
Counter clear is enable at the rising edge of GTETRG input
End of enumeration elements list.
CSGTRGBF : GTETRG Pin Falling Input Source Counter Clear Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTETRG input
#1 : 1
Counter clear is enable at the falling edge of GTETRG input
End of enumeration elements list.
CSGTRGCR : GTETRG Pin Rising Input Source Counter Clear Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTETRG input
#1 : 1
Counter clear is enable at the rising edge of GTETRG input
End of enumeration elements list.
CSGTRGCF : GTETRG Pin Falling Input Source Counter Clear Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTETRG input
#1 : 1
Counter clear is enable at the falling edge of GTETRG input
End of enumeration elements list.
CSGTRGDR : GTETRG Pin Rising Input Source Counter Clear Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTETRG input
#1 : 1
Counter clear is enable at the rising edge of GTETRG input
End of enumeration elements list.
CSGTRGDF : GTETRG Pin Falling Input Source Counter Clear Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTETRG input
#1 : 1
Counter clear is enable at the falling edge of GTETRG input
End of enumeration elements list.
CSCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
CSCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
CSCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
CSCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
CSCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
CSCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
CSCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
CSCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
CSELCA : ELC_GPTA Event Source Counter Clear Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCB : ELC_GPTA Event Source Counter Clear Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCC : ELC_GPTA Event Source Counter Clear Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCD : ELC_GPTA Event Source Counter Clear Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCE : ELC_GPTA Event Source Counter Clear Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCF : ELC_GPTA Event Source Counter Clear Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCG : ELC_GPTA Event Source Counter Clear Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CSELCH : ELC_GPTA Event Source Counter Clear Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable at the ELC_GPTA input
#1 : 1
Counter clear is enable at the ELC_GPTA input
End of enumeration elements list.
CCLR : Software Source Counter Clear Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear is disable by the GTCLR register
#1 : 1
Counter clear is enable by the GTCLR register
End of enumeration elements list.
General PWM Timer Compare Capture Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCCR : Compare Capture Register A
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Up Count Source Select Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USGTRGAR : GTETRG Pin Rising Input Source Counter Count Up Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTETRG input
#1 : 1
Counter count up is enable at the rising edge of GTETRG input
End of enumeration elements list.
USGTRGAF : GTETRG Pin Falling Input Source Counter Count Up Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTETRG input
#1 : 1
Counter count up is enable at the falling edge of GTETRG input
End of enumeration elements list.
USGTRGBR : GTETRG Pin Rising Input Source Counter Count Up Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTETRG input
#1 : 1
Counter count up is enable at the rising edge of GTETRG input
End of enumeration elements list.
USGTRGBF : GTETRG Pin Falling Input Source Counter Count Up Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTETRG input
#1 : 1
Counter count up is enable at the falling edge of GTETRG input
End of enumeration elements list.
USGTRGCR : GTETRG Pin Rising Input Source Counter Count Up Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTETRG input
#1 : 1
Counter count up is enable at the rising edge of GTETRG input
End of enumeration elements list.
USGTRGCF : GTETRG Pin Falling Input Source Counter Count Up Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTETRG input
#1 : 1
Counter count up is enable at the falling edge of GTETRG input
End of enumeration elements list.
USGTRGDR : GTETRG Pin Rising Input Source Counter Count Up Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTETRG input
#1 : 1
Counter count up is enable at the rising edge of GTETRG input
End of enumeration elements list.
USGTRGDF : GTETRG Pin Falling Input Source Counter Count Up Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTETRG input
#1 : 1
Counter count up is enable at the falling edge of GTETRG input
End of enumeration elements list.
USCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
USCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
USCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
USCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
USCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
USCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
USCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
USCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
USELCA : ELC_GPT Event Source Counter Count Up Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCB : ELC_GPT Event Source Counter Count Up Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCC : ELC_GPT Event Source Counter Count Up Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCD : ELC_GPT Event Source Counter Count Up Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCE : ELC_GPT Event Source Counter Count Up Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCF : ELC_GPT Event Source Counter Count Up Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCG : ELC_GPT Event Source Counter Count Up Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
USELCH : ELC_GPT Event Source Counter Count Up Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up is disable at the ELC_GPT input
#1 : 1
Counter count up is enable at the ELC_GPT input
End of enumeration elements list.
General PWM Timer Compare Capture Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCCR : Compare Capture Register A
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Down Count Source Select Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSGTRGAR : GTETRG Pin Rising Input Source Counter Count Down Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTETRG input
#1 : 1
Counter count down is enable at the rising edge of GTETRG input
End of enumeration elements list.
DSGTRGAF : GTETRG Pin Falling Input Source Counter Count Down Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTETRG input
#1 : 1
Counter count down is enable at the falling edge of GTETRG input
End of enumeration elements list.
DSGTRGBR : GTETRG Pin Rising Input Source Counter Count Down Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTETRG input
#1 : 1
Counter count down is enable at the rising edge of GTETRG input
End of enumeration elements list.
DSGTRGBF : GTETRG Pin Falling Input Source Counter Count Down Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTETRG input
#1 : 1
Counter count down is enable at the falling edge of GTETRG input
End of enumeration elements list.
DSGTRGCR : GTETRG Pin Rising Input Source Counter Count Down Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTETRG input
#1 : 1
Counter count down is enable at the rising edge of GTETRG input
End of enumeration elements list.
DSGTRGCF : GTETRG Pin Falling Input Source Counter Count Down Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTETRG input
#1 : 1
Counter count down is enable at the falling edge of GTETRG input
End of enumeration elements list.
DSGTRGDR : GTETRG Pin Rising Input Source Counter Count Down Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTETRG input
#1 : 1
Counter count down is enable at the rising edge of GTETRG input
End of enumeration elements list.
DSGTRGDF : GTETRG Pin Falling Input Source Counter Count Down Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTETRG input
#1 : 1
Counter count down is enable at the falling edge of GTETRG input
End of enumeration elements list.
DSCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
DSCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
DSCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
DSCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
DSCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
DSCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
DSCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
DSCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
DSELCA : ELC_GPT Event Source Counter Count Down Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCB : ELC_GPT Event Source Counter Count Down Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCC : ELC_GPT Event Source Counter Count Down Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCD : ELC_GPT Event Source Counter Count Down Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCE : ELC_GPT Event Source Counter Count Down Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCF : ELC_GPT Event Source Counter Count Down Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCG : ELC_GPT Event Source Counter Count Down Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
DSELCH : ELC_GPT Event Source Counter Count Down Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down is disable at the ELC_GPT input
#1 : 1
Counter count down is enable at the ELC_GPT input
End of enumeration elements list.
General PWM Timer Input Capture Source Select Register A
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASGTRGAR : GTETRG Pin Rising Input Source GTCCRA Input Capture Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
ASGTRGAF : GTETRG Pin Falling Input Source GTCCRA Input Capture Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
ASGTRGBR : GTETRG Pin Rising Input Source GTCCRA Input Capture Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
ASGTRGBF : GTETRG Pin Falling Input Source GTCCRA Input Capture Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
ASGTRGCR : GTETRG Pin Rising Input Source GTCCRA Input Capture Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
ASGTRGCF : GTETRG Pin Falling Input Source GTCCRA Input Capture Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
ASGTRGDR : GTETRG Pin Rising Input Source GTCCRA Input Capture Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
ASGTRGDF : GTETRG Pin Falling Input Source GTCCRA Input Capture Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRA input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
ASCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
ASCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
ASCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
ASCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
ASCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
ASCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
ASCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
ASCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
ASELCA : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCB : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCC : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCD : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCE : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCF : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCG : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
ASELCH : ELC_GPT Event Source GTCCRA Input Capture Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture is disable at the ELC_GPT input
#1 : 1
GTCCRA input capture is enable at the ELC_GPT input
End of enumeration elements list.
General PWM Timer Compare Capture Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCCR : Compare Capture Register A
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Input Capture Source Select Register B
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSGTRGAR : GTETRG Pin Rising Input Source GTCCRB Input Capture Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
BSGTRGAF : GTETRG Pin Falling Input Source GTCCRB Input Capture Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
BSGTRGBR : GTETRG Pin Rising Input Source GTCCRB Input Capture Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
BSGTRGBF : GTETRG Pin Falling Input Source GTCCRB Input Capture Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
BSGTRGCR : GTETRG Pin Rising Input Source GTCCRB Input Capture Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
BSGTRGCF : GTETRG Pin Falling Input Source GTCCRB Input Capture Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
BSGTRGDR : GTETRG Pin Rising Input Source GTCCRB Input Capture Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the rising edge of GTETRG input
End of enumeration elements list.
BSGTRGDF : GTETRG Pin Falling Input Source GTCCRB Input Capture Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTETRG input
#1 : 1
GTCCRB input capture is enable at the falling edge of GTETRG input
End of enumeration elements list.
BSCARBL : GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0
#1 : 1
GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
BSCARBH : GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1
#1 : 1
GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
BSCAFBL : GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0
#1 : 1
GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0
End of enumeration elements list.
BSCAFBH : GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1
#1 : 1
GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1
End of enumeration elements list.
BSCBRAL : GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0
#1 : 1
GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
BSCBRAH : GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1
#1 : 1
GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
BSCBFAL : GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0
#1 : 1
GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0
End of enumeration elements list.
BSCBFAH : GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1
#1 : 1
GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1
End of enumeration elements list.
BSELCA : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCB : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCC : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCD : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCE : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCF : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCG : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
BSELCH : ELC_GPT Event Source GTCCRB Input Capture Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture is disable at the ELC_GPT input
#1 : 1
GTCCRB input capture is enable at the ELC_GPT input
End of enumeration elements list.
General PWM Timer Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CST : Count Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Count operation is stopped
#1 : 1
Count operation is performed
End of enumeration elements list.
MD : Mode Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
Saw-wave PWM mode (single buffer or double buffer possible)
#001 : 001
Saw-wave one-shot pulse mode (fixed buffer operation)
#010 : 010
Setting prohibited
#011 : 011
Setting prohibited
#100 : 100
Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible)
#101 : 101
Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible)
#110 : 110
Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation)
#111 : 111
Setting prohibited
End of enumeration elements list.
TPCS : Timer Prescaler Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#0000 : 0000
PCLK/1
#0001 : 0001
PCLK/2
#0010 : 0010
PCLK/4
#0011 : 0011
PCLK/8
#0100 : 0100
PCLK/16
#0101 : 0101
PCLK/32
#0110 : 0110
PCLK/64
#1000 : 1000
PCLK/256
#1010 : 1010
PCLK/1024
#1100 : 1100
GTETRGA
#1101 : 1101
GTETRGB
#1110 : 1110
GTETRGC
#1111 : 1111
GTETRGD
: others
Setting prohibied
End of enumeration elements list.
General PWM Timer Count Direction and Duty Setting Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UD : Count Direction Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counts down.
#1 : 1
GTCNT counts up.
End of enumeration elements list.
UDF : Forcible Count Direction Setting
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not forcibly set
#1 : 1
Forcibly set
End of enumeration elements list.
OADTY : GTIOCA Output Duty Setting
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 00
GTIOCA pin duty is depend on compare match
#01 : 01
GTIOCA pin duty is depend on compare match
#10 : 10
GTIOCA pin duty 0 percent
#11 : 11
GTIOCA pin duty 100 percent
End of enumeration elements list.
OADTYF : Forcible GTIOCA Output Duty Setting
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not forcibly set
#1 : 1
Forcibly set
End of enumeration elements list.
OADTYR : GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.
#1 : 1
Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.
End of enumeration elements list.
OBDTY : GTIOCB Output Duty Setting
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : 00
GTIOCB pin duty is depend on compare match
#01 : 01
GTIOCB pin duty is depend on compare match
#10 : 10
GTIOCB pin duty 0 percent
#11 : 11
GTIOCB pin duty 100 percent
End of enumeration elements list.
OBDTYF : Forcible GTIOCB Output Duty Setting
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not forcibly set
#1 : 1
Forcibly set
End of enumeration elements list.
OBDTYR : GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting.
#1 : 1
Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting.
End of enumeration elements list.
General PWM Timer I/O Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTIOA : GTIOCA Pin Function Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match.
#00001 : 00001
Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match.
#00010 : 00010
Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match.
#00011 : 00011
Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match.
#00100 : 00100
Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match.
#00101 : 00101
Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match.
#00110 : 00110
Initial output is Low. Low output at cycle end. High output at GTCCRA compare match.
#00111 : 00111
Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match.
#01000 : 01000
Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match.
#01001 : 01001
Initial output is Low. High output at cycle end. Low output at GTCCRA compare match.
#01010 : 01010
Initial output is Low. High output at cycle end. High output at GTCCRA compare match.
#01011 : 01011
Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match.
#01100 : 01100
Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match.
#01101 : 01101
Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match.
#01110 : 01110
Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match.
#01111 : 01111
Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match.
#10000 : 10000
Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match.
#10001 : 10001
Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match.
#10010 : 10010
Initial output is High. Output retained at cycle end. High output at GTCCRA compare match.
#10011 : 10011
Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match.
#10100 : 10100
Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match.
#10101 : 10101
Initial output is High. Low output at cycle end. Low output at GTCCRA compare match.
#10110 : 10110
Initial output is High. Low output at cycle end. High output at GTCCRA compare match.
#10111 : 10111
Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match.
#11000 : 11000
Initial output is High. High output at cycle end. Output retained at GTCCRA compare match.
#11001 : 11001
Initial output is High. High output at cycle end. Low output at GTCCRA compare match.
#11010 : 11010
Initial output is High. High output at cycle end. High output at GTCCRA compare match.
#11011 : 11011
Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match.
#11100 : 11100
Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match.
#11101 : 11101
Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match.
#11110 : 11110
Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match.
#11111 : 11111
Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match.
End of enumeration elements list.
OADFLT : GTIOCA Pin Output Value Setting at the Count Stop
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCA pin outputs low when counting is stopped.
#1 : 1
The GTIOCA pin outputs high when counting is stopped.
End of enumeration elements list.
OAHLD : GTIOCA Pin Output Setting at the Start/Stop Count
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCA pin output level at start/stop of counting depends on the register setting.
#1 : 1
The GTIOCA pin output level is retained at start/stop of counting.
End of enumeration elements list.
OAE : GTIOCA Pin Output Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output is disabled
#1 : 1
Output is enabled
End of enumeration elements list.
OADF : GTIOCA Pin Disable Value Setting
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output disable is prohibited.
#01 : 01
GTIOCA pin is set to Hi-Z when output disable is performed.
#10 : 10
GTIOCA pin is set to 0 when output disable is performed.
#11 : 11
GTIOCA pin is set to 1 when output disable is performed.
End of enumeration elements list.
NFAEN : Noise Filter A Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
The noise filter for the GTIOCA pin is disabled.
#1 : 1
The noise filter for the GTIOCA pin is enabled.
End of enumeration elements list.
NFCSA : Noise Filter A Sampling Clock Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK/1
#01 : 01
PCLK/4
#10 : 10
PCLK/16
#11 : 11
PCLK/64
End of enumeration elements list.
GTIOB : GTIOCB Pin Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match.
#00001 : 00001
Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match.
#00010 : 00010
Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match.
#00011 : 00011
Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match.
#00100 : 00100
Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match.
#00101 : 00101
Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match.
#00110 : 00110
Initial output is Low. Low output at cycle end. High output at GTCCRB compare match.
#00111 : 00111
Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match.
#01000 : 01000
Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match.
#01001 : 01001
Initial output is Low. High output at cycle end. Low output at GTCCRB compare match.
#01010 : 01010
Initial output is Low. High output at cycle end. High output at GTCCRB compare match.
#01011 : 01011
Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match.
#01100 : 01100
Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match.
#01101 : 01101
Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match.
#01110 : 01110
Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match.
#01111 : 01111
Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match.
#10000 : 10000
Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match.
#10001 : 10001
Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match.
#10010 : 10010
Initial output is High. Output retained at cycle end. High output at GTCCRB compare match.
#10011 : 10011
Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match.
#10100 : 10100
Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match.
#10101 : 10101
Initial output is High. Low output at cycle end. Low output at GTCCRB compare match.
#10110 : 10110
Initial output is High. Low output at cycle end. High output at GTCCRB compare match.
#10111 : 10111
Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match.
#11000 : 11000
Initial output is High. High output at cycle end. Output retained at GTCCRB compare match.
#11001 : 11001
Initial output is High. High output at cycle end. Low output at GTCCRB compare match.
#11010 : 11010
Initial output is High. High output at cycle end. High output at GTCCRB compare match.
#11011 : 11011
Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match.
#11100 : 11100
Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match.
#11101 : 11101
Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match.
#11110 : 11110
Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match.
#11111 : 11111
Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match.
End of enumeration elements list.
OBDFLT : GTIOCB Pin Output Value Setting at the Count Stop
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCB pin outputs low when counting is stopped.
#1 : 1
The GTIOCB pin outputs high when counting is stopped.
End of enumeration elements list.
OBHLD : GTIOCB Pin Output Setting at the Start/Stop Count
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCB pin output level at start/stop of counting depends on the register setting.
#1 : 1
The GTIOCB pin output level is retained at start/stop of counting.
End of enumeration elements list.
OBE : GTIOCB Pin Output Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output is disabled
#1 : 1
Output is enabled
End of enumeration elements list.
OBDF : GTIOCB Pin Disable Value Setting
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output disable is prohibited.
#01 : 01
GTIOCB pin is set to Hi-Z when output disable is performed.
#10 : 10
GTIOCB pin is set to 0 when output disable is performed.
#11 : 11
GTIOCB pin is set to 1 when output disable is performed.
End of enumeration elements list.
NFBEN : Noise Filter B Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
The noise filter for the GTIOCB pin is disabled.
#1 : 1
The noise filter for the GTIOCB pin is enabled.
End of enumeration elements list.
NFCSB : Noise Filter B Sampling Clock Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK/1
#01 : 01
PCLK/4
#10 : 10
PCLK/16
#11 : 11
PCLK/64
End of enumeration elements list.
General PWM Timer Interrupt Output Setting Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GRP : Output Disable Source Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : 00
Group A output disable request
#01 : 01
Group B output disable request
#10 : 10
Group C output disable request
#11 : 11
Group D output disable request
: others
Setting prohibited
End of enumeration elements list.
GRPDTE : Dead Time Error Output Disable Request Enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable dead time error output disable request
#1 : 1
Enable dead time error output disable request
End of enumeration elements list.
GRPABH : Same Time Output Level High Disable Request Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Same time output level high disable request is disabled.
#1 : 1
Same time output level high disable request is enabled.
End of enumeration elements list.
GRPABL : Same Time Output Level Low Disable Request Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Same time output level low disable request is disabled.
#1 : 1
Same time output level low disable request is enabled.
End of enumeration elements list.
General PWM Timer Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCFA : Input Capture/Compare Match Flag A
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No input capture/compare match of GTCCRA is generated.
#1 : 1
An input capture/compare match of GTCCRA is generated.
End of enumeration elements list.
TCFB : Input Capture/Compare Match Flag B
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No input capture/compare match of GTCCRB is generated.
#1 : 1
An input capture/compare match of GTCCRB is generated.
End of enumeration elements list.
TCFC : Input Compare Match Flag C
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRC is generated.
#1 : 1
A compare match of GTCCRC is generated.
End of enumeration elements list.
TCFD : Input Compare Match Flag D
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRD is generated.
#1 : 1
A compare match of GTCCRD is generated.
End of enumeration elements list.
TCFE : Input Compare Match Flag E
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRE is generated.
#1 : 1
A compare match of GTCCRE is generated.
End of enumeration elements list.
TCFF : Input Compare Match Flag F
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRF is generated.
#1 : 1
A compare match of GTCCRF is generated.
End of enumeration elements list.
TCFPO : Overflow Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow (crest) has occurred.
#1 : 1
An overflow (crest) has occurred.
End of enumeration elements list.
TCFPU : Underflow Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No underflow (trough) has occurred.
#1 : 1
An underflow (trough) has occurred.
End of enumeration elements list.
ITCNT : GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.)
bits : 8 - 9 (2 bit)
access : read-only
TUCF : Count Direction Flag
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
The GTCNT counter counts downward.
#1 : 1
The GTCNT counter counts upward.
End of enumeration elements list.
ADTRAUF : GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTADTRA at up-counting is generated.
#1 : 1
A compare match of GTADTRA at up-counting is generated.
End of enumeration elements list.
ADTRADF : GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTADTRA at down-counting is generated.
#1 : 1
A compare match of GTADTRA at down-counting is generated.
End of enumeration elements list.
ADTRBUF : GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTADTRB at up-counting is generated.
#1 : 1
A compare match of GTADTRB at up-counting is generated.
End of enumeration elements list.
ADTRBDF : GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTADTRB at down-counting is generated.
#1 : 1
A compare match of GTADTRB at down-counting is generated.
End of enumeration elements list.
ODF : Output Disable Flag
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
#0 : 0
No output disable request is generated.
#1 : 1
An output disable request is generated.
End of enumeration elements list.
DTEF : Dead Time Error Flag
bits : 28 - 27 (0 bit)
access : read-only
Enumeration:
#0 : 0
No dead time error has occurred.
#1 : 1
A dead time error has occurred.
End of enumeration elements list.
OABHF : Same Time Output Level High Disable Request Enable
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : 0
GTIOCA pin and GTIOCB pin don't output 1 at the same time.
#1 : 1
GTIOCA pin and GTIOCB pin output 1 at the same time.
End of enumeration elements list.
OABLF : Same Time Output Level Low Disable Request Enable
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
#0 : 0
GTIOCA pin and GTIOCB pin don't output 0 at the same time.
#1 : 1
GTIOCA pin and GTIOCB pin output 0 at the same time.
End of enumeration elements list.
General PWM Timer Software Start Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTRT0 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT1 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT2 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT3 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT4 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT5 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT6 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT7 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT8 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT9 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT10 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT11 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT12 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
CSTRT13 : Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter stop (read)
#1 : 1
GTCNT counter starts (write) / Counter running (read)
End of enumeration elements list.
General PWM Timer Buffer Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BD0 : BD[0]: GTCCR Buffer Operation Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Buffer operation is enabled
#1 : 1
Buffer operation is disabled
End of enumeration elements list.
BD1 : BD[1]: GTPR Buffer Operation Disable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Buffer operation is enabled
#1 : 1
Buffer operation is disabled
End of enumeration elements list.
BD2 : BD[2]: GTADTR Buffer Operation DisableBD
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable buffer operation
#1 : 1
Disable buffer operation
End of enumeration elements list.
BD3 : BD[3]: GTDV Buffer Operation DisableBD[2]
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable buffer operation
#1 : 1
Disable buffer operation
End of enumeration elements list.
CCRA : GTCCRA Buffer Operation
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 00
Buffer operation is not performed
#01 : 01
Single buffer operation (GTCCRA <--> GTCCRC)
#10 : 10
Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)
#11 : 11
Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)
End of enumeration elements list.
CCRB : GTCCRB Buffer Operation
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : 00
Buffer operation is not performed
#01 : 01
Single buffer operation (GTCCRB <--> GTCCRE)
#10 : 10
Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)
#11 : 11
Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)
End of enumeration elements list.
PR : GTPR Buffer Operation
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : 00
Buffer operation is not performed
#01 : 01
Single buffer operation (GTPBR --> GTPR)
: others
Setting prohibited
End of enumeration elements list.
CCRSWT : GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0.
bits : 22 - 21 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1.
End of enumeration elements list.
ADTTA : GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : 00
No transfer
#01 : 01
Transfer at crest
#10 : 10
Transfer at trough
#11 : 11
Transfer at both crest and trough
End of enumeration elements list.
ADTDA : GTADTRA Double Buffer Operation
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single buffer operation (GTADTBRA --> GTADTRA)
#1 : 1
Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA)
End of enumeration elements list.
ADTTB : GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#00 : 00
No transfer
#01 : 01
Transfer at crest
#10 : 10
Transfer at trough
#11 : 11
Transfer at both crest and trough
End of enumeration elements list.
ADTDB : GTADTRB Double Buffer Operation
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single buffer operation (GTADTBRB --> GTADTRB)
#1 : 1
Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB)
End of enumeration elements list.
General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITLA : GTCCRA Compare Match/Input Capture Interrupt Link
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
ITLB : GTCCRB Compare Match/Input Capture Interrupt Link
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
ITLC : GTCCRC Compare Match Interrupt Link
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
ITLD : GTCCRD Compare Match Interrupt Link
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
ITLE : GTCCRE Compare Match Interrupt Link
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
ITLF : GTCCRF Compare Match Interrupt Link
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
IVTC : GPT_OVF/GPT_UDF Interrupt Skipping Function Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not perform skipping
#01 : 01
Count and skip both overflow and underflow for saw waves and crest for triangle waves
#10 : 10
Count and skip both overflow and underflow for saw waves and trough for triangle waves
#11 : 11
Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves.
End of enumeration elements list.
IVTT : GPT_OVF/GPT_UDF Interrupt Skipping Count Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
No skipping
#001 : 001
Skipping count of 1
#010 : 010
Skipping count of 2
#011 : 011
Skipping count of 3
#100 : 100
Skipping count of 4
#101 : 101
Skipping count of 5
#110 : 110
Skipping count of 6
#111 : 111
Skipping count of 7.
End of enumeration elements list.
ADTAL : GTADTRA A/D Converter Start Request Link
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function
End of enumeration elements list.
ADTBL : GTADTRB A/D Converter Start Request Link
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
#1 : 1
Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
End of enumeration elements list.
General PWM Timer Counter
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCNT : Counter
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Cycle Setting Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTPR : Cycle Setting Register
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Cycle Setting Buffer Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTPBR : Cycle Setting Buffer Register
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Cycle Setting Double-Buffer Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTPDBR : Cycle Setting Double-Buffer Register
bits : 0 - 30 (31 bit)
access : read-write
A/D Converter Start Request Timing Register A
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTADTRA : A/D Converter Start Request Timing Register A
bits : 0 - 30 (31 bit)
access : read-write
A/D Converter Start Request Timing Buffer Register A
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTADTBRA : A/D Converter Start Request Timing Buffer Register A
bits : 0 - 30 (31 bit)
access : read-write
A/D Converter Start Request Timing Double-Buffer Register A
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTADTDBRA : A/D Converter Start Request Timing Double-Buffer Register A
bits : 0 - 30 (31 bit)
access : read-write
A/D Converter Start Request Timing Register B
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTADTRB : A/D Converter Start Request Timing Register B
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Software Stop Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTOP0 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP1 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP2 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP3 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP4 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP5 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP6 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP7 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP8 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP9 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP10 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP11 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP12 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
CSTOP13 : Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect (write) / counter running (read)
#1 : 1
GPT GTCNT counter stops (write) / Counter stop (read)
End of enumeration elements list.
A/D Converter Start Request Timing Buffer Register B
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTADTBRB : A/D Converter Start Request Timing Buffer Register B
bits : 0 - 30 (31 bit)
access : read-write
A/D Converter Start Request Timing Double-Buffer Register B
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTADTDBRB : A/D Converter Start Request Timing Double-Buffer Register B
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Dead Time Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDE : Negative-Phase Waveform Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB is set without using GTDVU and GTDVD.
#1 : 1
GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB.
End of enumeration elements list.
TDBUE : GTDVU Buffer Operation Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable GTDVU buffer operation
#1 : 1
Enable GTDVU buffer operation
End of enumeration elements list.
TDBDE : GTDVD Buffer Operation Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable GTDVD buffer operation
#1 : 1
Enable GTDVD buffer operation
End of enumeration elements list.
TDFER : GTDVD Setting
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Set GTDVU and GTDVD separately
#1 : 1
Automatically set the value written to GTDVU to GTDVD
End of enumeration elements list.
General PWM Timer Dead Time Value Register U
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTDVU : Dead Time Value Register U
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Dead Time Value Register D
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTDVD : Dead Time Value Register D
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Dead Time Buffer Register U
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTDVU : Dead Time Buffer Register U
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Compare Capture Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCCR : Compare Capture Register A
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Dead Time Buffer Register D
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTDBD : Dead Time Buffer Register D
bits : 0 - 30 (31 bit)
access : read-write
General PWM Timer Output Protection Function Status Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOS : Output Protection Function Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#00 : 00
Normal operation
#01 : 01
Protected state (GTCCRA = 0 is set during transfer at trough or crest)
#10 : 10
Protected state (GTCCRA >= GTPR is set during transfer at trough)
#11 : 11
Protected state (GTCCRA >= GTPR is set during transfer at crest)
End of enumeration elements list.
General PWM Timer Output Protection Function Temporary Release Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOTR : Output Protection Function Temporary Release
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not release protected state
#1 : 1
Release protected state
End of enumeration elements list.
General PWM Timer Software Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CCLR0 : Channel GTCNT Count Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR1 : Channel GTCNT Count Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR2 : Channel GTCNT Count Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR3 : Channel GTCNT Count Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR4 : Channel GTCNT Count Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR5 : Channel GTCNT Count Clear
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR6 : Channel GTCNT Count Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR7 : Channel GTCNT Count Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR8 : Channel GTCNT Count Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR9 : Channel GTCNT Count Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR10 : Channel GTCNT Count Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR11 : Channel GTCNT Count Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR12 : Channel GTCNT Count Clear
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
CCLR13 : Channel GTCNT Count Clear
bits : 13 - 12 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
GPT GTCNT counter clears
End of enumeration elements list.
General PWM Timer Compare Capture Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTCCR : Compare Capture Register A
bits : 0 - 30 (31 bit)
access : read-write
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