\n

R_GPT_ODC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GTDLYCR1

GTDLYR[0]-A

GTDLYR[0]-B

GTDLYCR2

GTDLYR[1]-GTDLYR[0]-A

GTDLYR[1]-GTDLYR[0]-B

GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A

GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B

GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A

GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B


GTDLYCR1

PWM Output Delay Control Register1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYCR1 GTDLYCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLLEN DLYRST DLLMOD

DLLEN : DLL Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DLL operation is disabled

#1 : 1

DLL operation is enabled

End of enumeration elements list.

DLYRST : PWM Delay Generation Circuit Reset
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Reset

End of enumeration elements list.

DLLMOD : DLL Mode Select
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

5 bit-mode

#1 : 1

4 bit-mode

End of enumeration elements list.


GTDLYR[0]-A

GTIOCA Output Delay Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[0]-A GTDLYR[0]-A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYR[0]-B

GTIOCB Output Delay Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[0]-B GTDLYR[0]-B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYCR2

PWM Output Delay Control Register2
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYCR2 GTDLYCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLYBS0 DLYBS1 DLYBS2 DLYBS3 DLYEN0 DLYDENB0

DLYBS0 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay generation circuit of channel is bypassed.

#1 : 1

Delay generation circuit of channel is not bypassed.

End of enumeration elements list.

DLYBS1 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay generation circuit of channel is bypassed.

#1 : 1

Delay generation circuit of channel is not bypassed.

End of enumeration elements list.

DLYBS2 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay generation circuit of channel is bypassed.

#1 : 1

Delay generation circuit of channel is not bypassed.

End of enumeration elements list.

DLYBS3 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay generation circuit of channel is bypassed.

#1 : 1

Delay generation circuit of channel is not bypassed.

End of enumeration elements list.

DLYEN0 : PWM Delay Generation Circuit enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay generation circuit of channel is enabled

#1 : 1

Delay generation circuit of channel is disabled.

End of enumeration elements list.

DLYDENB0 : PWM Delay Generation Circuit Disenable for GTIOCB
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Delay generation circuit of GTIOCB is based on DLYEN1.

#1 : 1

Delay generation circuit of GTIOCB is disabled.

End of enumeration elements list.


GTDLYR[1]-GTDLYR[0]-A

GTIOCA Output Delay Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[1]-GTDLYR[0]-A GTDLYR[1]-GTDLYR[0]-A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYR[1]-GTDLYR[0]-B

GTIOCB Output Delay Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[1]-GTDLYR[0]-B GTDLYR[1]-GTDLYR[0]-B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A

GTIOCA Output Delay Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B

GTIOCB Output Delay Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A

GTIOCA Output Delay Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.


GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B

GTIOCB Output Delay Register
address_offset : 0x7A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00000 : 00000

No delay on rising edges

End of enumeration elements list.



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