\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A
GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B
GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-A
GTDLYR[3]-GTDLYR[2]-GTDLYR[1]-GTDLYR[0]-B
PWM Output Delay Control Register1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLLEN : DLL Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DLL operation is disabled
#1 : 1
DLL operation is enabled
End of enumeration elements list.
DLYRST : PWM Delay Generation Circuit Reset
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
DLLMOD : DLL Mode Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
5 bit-mode
#1 : 1
4 bit-mode
End of enumeration elements list.
GTIOCA Output Delay Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
GTIOCB Output Delay Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
PWM Output Delay Control Register2
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLYBS0 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay generation circuit of channel is bypassed.
#1 : 1
Delay generation circuit of channel is not bypassed.
End of enumeration elements list.
DLYBS1 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay generation circuit of channel is bypassed.
#1 : 1
Delay generation circuit of channel is not bypassed.
End of enumeration elements list.
DLYBS2 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay generation circuit of channel is bypassed.
#1 : 1
Delay generation circuit of channel is not bypassed.
End of enumeration elements list.
DLYBS3 : PWM Delay Generation Circuit bypass
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay generation circuit of channel is bypassed.
#1 : 1
Delay generation circuit of channel is not bypassed.
End of enumeration elements list.
DLYEN0 : PWM Delay Generation Circuit enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay generation circuit of channel is enabled
#1 : 1
Delay generation circuit of channel is disabled.
End of enumeration elements list.
DLYDENB0 : PWM Delay Generation Circuit Disenable for GTIOCB
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay generation circuit of GTIOCB is based on DLYEN1.
#1 : 1
Delay generation circuit of GTIOCB is disabled.
End of enumeration elements list.
GTIOCA Output Delay Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
GTIOCB Output Delay Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
GTIOCA Output Delay Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
GTIOCB Output Delay Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
GTIOCA Output Delay Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
GTIOCB Output Delay Register
address_offset : 0x7A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : GTIOCnA Output Rising Edge Delay Setting
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No delay on rising edges
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.