Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1A0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection : not protected
IRQ Control Register %s
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
NMI Pin Interrupt Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIMD : NMI Detection Set
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge
#1 : 1
Rising edge
End of enumeration elements list.
NFCLKSEL : NMI Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
NFLTEN : NMI Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x102F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x10710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x10B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x10F5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x11388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x117B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0x11BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x11BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
Non-Maskable Interrupt Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTEN : IWDT Underflow/Refresh Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
WDTEN : WDT Underflow/Refresh Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
LVD1EN : Voltage-Monitoring 1 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
LVD2EN : Voltage-Monitoring 2 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
VBATTEN : VBATT monitor Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
OSTEN : Oscillation Stop Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
NMIEN : NMI Pin Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
RPEEN : RAM Parity Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
RECCEN : RAM ECC Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
BUSSEN : MPU Bus Slave Error Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
BUSMEN : MPU Bus Master Error Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
SPEEN : CPU Stack pointer monitor Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x12024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x12460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x128A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x12CE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
Non-Maskable Interrupt Status Clear Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTCLR : IWDT Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.IWDTST flag.
End of enumeration elements list.
WDTCLR : WDT Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.WDTST flag.
End of enumeration elements list.
LVD1CLR : LVD1 Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.LVD1ST flag.
End of enumeration elements list.
LVD2CLR : LVD2 Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.LVD2ST flag.
End of enumeration elements list.
VBATTCLR : VBATT Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.VBATTST flag.
End of enumeration elements list.
OSTCLR : OST Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.OSTST flag.
End of enumeration elements list.
NMICLR : NMI Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.NMIST flag.
End of enumeration elements list.
RPECLR : SRAM Parity Error Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.RPEST flag.
End of enumeration elements list.
RECCCLR : SRAM ECC Error Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.RECCST flag.
End of enumeration elements list.
BUSSCLR : Bus Slave Error Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.BUSSST flag.
End of enumeration elements list.
BUSMCLR : Bus Master Error Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.BUSMST flag.
End of enumeration elements list.
SPECLR : CPU Stack Pointer Monitor Interrupt Clear
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.SPEST flag.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x1312C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x13578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x139C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x13E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
Non-Maskable Interrupt Status Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IWDTST : IWDT Underflow/Refresh Error Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
WDTST : WDT Underflow/Refresh Error Status Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
LVD1ST : Voltage-Monitoring 1 Interrupt Status Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
LVD2ST : Voltage-Monitoring 2 Interrupt Status Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
VBATTST : VBATT monitor Interrupt Status Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
OSTST : Oscillation Stop Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested for main oscillation stop
#1 : 1
Interrupt requested for main oscillation stop.
End of enumeration elements list.
NMIST : NMI Status Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
RPEST : RAM Parity Error Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
RECCST : RAM ECC Error Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
BUSSST : MPU Bus Slave Error Interrupt Status Flag
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
BUSMST : MPU Bus Master Error Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
SPEST : CPU Stack pointer monitor Interrupt Status Flag
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x14274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0x1454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x146D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x14B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x14F94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x153FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x15868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x15CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x1614C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x165C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x16A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0x16F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
Wake Up Interrupt Enable Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQWUPEN0 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN1 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN2 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN3 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN4 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN5 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN6 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN7 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN8 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN9 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN10 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN11 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN12 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN13 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN14 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IRQWUPEN15 : IRQ interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ interrupt is disabled
#1 : 1
S/W standby returns by IRQ interrupt is enabled
End of enumeration elements list.
IWDTWUPEN : IWDT interrupt S/W standby returns enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IWDT interrupt is disabled
#1 : 1
S/W standby returns by IWDT interrupt is enabled
End of enumeration elements list.
KEYWUPEN : Key interrupt S/W standby returns enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by KEY interrupt is disabled
#1 : 1
S/W standby returns by KEY interrupt is enabled
End of enumeration elements list.
LVD1WUPEN : LVD1 interrupt S/W standby returns enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by LVD1 interrupt is disabled
#1 : 1
S/W standby returns by LVD1 interrupt is enabled
End of enumeration elements list.
LVD2WUPEN : LVD2 interrupt S/W standby returns enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by LVD2 interrupt is disabled
#1 : 1
S/W standby returns by LVD2 interrupt is enabled
End of enumeration elements list.
VBATTWUPEN : VBATT monitor interrupt S/W standby returns enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by VBATT monitor interrupt is disabled
#1 : 1
S/W standby returns by VBATT monitor interrupt is enabled
End of enumeration elements list.
ACMPHS0WUPEN : ACMPHS0 interrupt S/W standby returns enable bit
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by ACMPHS0 interrupt is disabled
#1 : 1
S/W standby returns by ACMPHS0 interrupt is enabled
End of enumeration elements list.
ACMPLP0WUPEN : ACMPLP0 interrupt S/W standby returns enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by ACMPLP0 interrupt is disabled
#1 : 1
S/W standby returns by ACMPLP0 interrupt is enabled
End of enumeration elements list.
RTCALMWUPEN : RTC alarm interrupt S/W standby returns enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by RTC alarm interrupt is disabled
#1 : 1
S/W standby returns by RTC alarm interrupt is enabled
End of enumeration elements list.
RTCPRDWUPEN : RCT period interrupt S/W standby returns enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by RTC period interrupt is disabled
#1 : 1
S/W standby returns by RTC period interrupt is enabled
End of enumeration elements list.
USBHSWUPEN : USBHS interrupt S/W standby returns enable bit
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by USBHS interrupt is disabled
#1 : 1
S/W standby returns by USBHS interrupt is enabled
End of enumeration elements list.
USBFSWUPEN : USBFS interrupt S/W standby returns enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by USBFS interrupt is disabled
#1 : 1
S/W standby returns by USBFS interrupt is enabled
End of enumeration elements list.
AGT1UDWUPEN : AGT1 underflow interrupt S/W standby returns enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 underflow interrupt is disabled
#1 : 1
S/W standby returns by AGT1 underflow interrupt is enabled
End of enumeration elements list.
AGT1CAWUPEN : AGT1 compare match A interrupt S/W standby returns enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 compare match A interrupt is disabled
#1 : 1
S/W standby returns by AGT1 compare match A interrupt is enabled
End of enumeration elements list.
AGT1CBWUPEN : AGT1 compare match B interrupt S/W standby returns enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 compare match B interrupt is disabled
#1 : 1
S/W standby returns by AGT1 compare match B interrupt is enabled
End of enumeration elements list.
IIC0WUPEN : IIC0 address match interrupt S/W standby returns enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IIC0 address match interrupt is disabled
#1 : 1
S/W standby returns by IIC0 address match interrupt is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x1E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
Snooze Event Link Setting Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELS : SYS Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x21B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x24DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x2808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x2B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x2E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x31A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x34E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x3820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x3B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x3EAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x41F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x4548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x489C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x4BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x4F50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x52B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x5614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x597C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x5CE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x6058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x63CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x6744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x69 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x6AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x6E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x71C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x754C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x78D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x7C68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x7FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x8394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x8730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x8AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x8E74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x921C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x95C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x9978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x9D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xA0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xA4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xA860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xAC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xAFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xB3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xB788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xBB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xBF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xC310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xC6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xCAD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xCEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xD2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xD698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xDA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xDE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xE280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xE680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xEA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xEE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
DMAC Event Link Setting Register
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
End of enumeration elements list.
IR : Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0x0
No interrupt request is generated.
#1 : 0x1
An interrupt request is generated.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xF298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xF6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xFABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0xFED4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.