\n

R_OPAMP

Peripheral Memory Blocks

address_offset : 0x8 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xE Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1F Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection : not protected

Registers

AMPIO[0]-P

AMPIO[1]-AMPIO[0]-O

AMPUOTE

AMPIO[1]-AMPIO[0]-M

AMPOT[0]-P

AMPIO[1]-AMPIO[0]-P

AMPOT[0]-N

AMPIO[2]-AMPIO[1]-AMPIO[0]-O

AMPIO[2]-AMPIO[1]-AMPIO[0]-M

AMPIO[2]-AMPIO[1]-AMPIO[0]-P

AMPOT[1]-AMPOT[0]-P

AMPOT[1]-AMPOT[0]-N

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-O

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-M

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-P

AMPOT[2]-AMPOT[1]-AMPOT[0]-P

AMPOT[2]-AMPOT[1]-AMPOT[0]-N

AMPMC

AMPTRM

AMPTRS

AMPC

AMPMON

AMPIO[0]-O

AMPIO[0]-M


AMPIO[0]-P

Plus Input Select Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[0]-P AMPIO[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPIO[1]-AMPIO[0]-O

Output Select Register
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[1]-AMPIO[0]-O AMPIO[1]-AMPIO[0]-O read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPUOTE

Operational Amplifier User Offset Trimming Enable Register
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPUOTE AMPUOTE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMP0TE AMP1TE AMP2TE

AMP0TE : AMP%sOT write enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not possible to write the AMPnOTP and AMPnOTN registers

#1 : 1

Possible to write the AMPnOTP and AMPnOTN registers

End of enumeration elements list.

AMP1TE : AMP%sOT write enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not possible to write the AMPnOTP and AMPnOTN registers

#1 : 1

Possible to write the AMPnOTP and AMPnOTN registers

End of enumeration elements list.

AMP2TE : AMP%sOT write enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not possible to write the AMPnOTP and AMPnOTN registers

#1 : 1

Possible to write the AMPnOTP and AMPnOTN registers

End of enumeration elements list.


AMPIO[1]-AMPIO[0]-M

Minus Input Select Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[1]-AMPIO[0]-M AMPIO[1]-AMPIO[0]-M read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPOT[0]-P

Operational Amplifier n Offset Trimming Pch Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPOT[0]-P AMPOT[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRMP

TRMP : AMPn input offset trimming Pch side
bits : 0 - 3 (4 bit)
access : read-write


AMPIO[1]-AMPIO[0]-P

Plus Input Select Register
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[1]-AMPIO[0]-P AMPIO[1]-AMPIO[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPOT[0]-N

Operational Amplifier n Offset Trimming Nch Register
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPOT[0]-N AMPOT[0]-N read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRMN

TRMN : AMPn input offset trimming Nch side
bits : 0 - 3 (4 bit)


AMPIO[2]-AMPIO[1]-AMPIO[0]-O

Output Select Register
address_offset : 0x33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[2]-AMPIO[1]-AMPIO[0]-O AMPIO[2]-AMPIO[1]-AMPIO[0]-O read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPIO[2]-AMPIO[1]-AMPIO[0]-M

Minus Input Select Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[2]-AMPIO[1]-AMPIO[0]-M AMPIO[2]-AMPIO[1]-AMPIO[0]-M read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPIO[2]-AMPIO[1]-AMPIO[0]-P

Plus Input Select Register
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[2]-AMPIO[1]-AMPIO[0]-P AMPIO[2]-AMPIO[1]-AMPIO[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPOT[1]-AMPOT[0]-P

Operational Amplifier n Offset Trimming Pch Register
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPOT[1]-AMPOT[0]-P AMPOT[1]-AMPOT[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRMP

TRMP : AMPn input offset trimming Pch side
bits : 0 - 3 (4 bit)
access : read-write


AMPOT[1]-AMPOT[0]-N

Operational Amplifier n Offset Trimming Nch Register
address_offset : 0x43 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPOT[1]-AMPOT[0]-N AMPOT[1]-AMPOT[0]-N read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRMN

TRMN : AMPn input offset trimming Nch side
bits : 0 - 3 (4 bit)


AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-O

Output Select Register
address_offset : 0x4A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-O AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-O read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-M

Minus Input Select Register
address_offset : 0x4B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-M AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-M read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-P

Plus Input Select Register
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-P AMPIO[3]-AMPIO[2]-AMPIO[1]-AMPIO[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPOT[2]-AMPOT[1]-AMPOT[0]-P

Operational Amplifier n Offset Trimming Pch Register
address_offset : 0x66 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPOT[2]-AMPOT[1]-AMPOT[0]-P AMPOT[2]-AMPOT[1]-AMPOT[0]-P read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRMP

TRMP : AMPn input offset trimming Pch side
bits : 0 - 3 (4 bit)
access : read-write


AMPOT[2]-AMPOT[1]-AMPOT[0]-N

Operational Amplifier n Offset Trimming Nch Register
address_offset : 0x67 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPOT[2]-AMPOT[1]-AMPOT[0]-N AMPOT[2]-AMPOT[1]-AMPOT[0]-N read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRMN

TRMN : AMPn input offset trimming Nch side
bits : 0 - 3 (4 bit)


AMPMC

Operational amplifier mode control register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPMC AMPMC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPPC0 AMPPC1 AMPPC2 AMPSP

AMPPC0 : Operational amplifier precharge control status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Precharging is stopped.

#1 : 1

Precharging is enabled.

End of enumeration elements list.

AMPPC1 : Operational amplifier precharge control status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Precharging is stopped.

#1 : 1

Precharging is enabled.

End of enumeration elements list.

AMPPC2 : Operational amplifier precharge control status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Precharging is stopped.

#1 : 1

Precharging is enabled.

End of enumeration elements list.

AMPSP : Operation mode selection
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Low-power mode (low-speed).

#1 : 1

High-speed mode.

End of enumeration elements list.


AMPTRM

Operational amplifier trigger mode control register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPTRM AMPTRM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPTRM0 AMPTRM2 AMPTRM4 AMPTRM6

AMPTRM0 : Operational amplifier function activation/stop trigger control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Software trigger mode.

#01 : 01

An activation and A/D trigger mode.

#10 : 10

Setting prohibited.

#11 : 11

An activation and A/D trigger mode.

End of enumeration elements list.

AMPTRM2 : Operational amplifier function activation/stop trigger control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Software trigger mode.

#01 : 01

An activation and A/D trigger mode.

#10 : 10

Setting prohibited.

#11 : 11

An activation and A/D trigger mode.

End of enumeration elements list.

AMPTRM4 : Operational amplifier function activation/stop trigger control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Software trigger mode.

#01 : 01

An activation and A/D trigger mode.

#10 : 10

Setting prohibited.

#11 : 11

An activation and A/D trigger mode.

End of enumeration elements list.

AMPTRM6 : Operational amplifier function activation/stop trigger control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Software trigger mode.

#01 : 01

An activation and A/D trigger mode.

#10 : 10

Setting prohibited.

#11 : 11

An activation and A/D trigger mode.

End of enumeration elements list.


AMPTRS

Operational Amplifier Activation Trigger Select Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPTRS AMPTRS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPTRS

AMPTRS : ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3

#01 : 01

Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1

#10 : 10

Setting prohibited

#11 : 11

Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0

End of enumeration elements list.


AMPC

Operational amplifier control register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPC AMPC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPE0 AMPE1 AMPE2 AMPE3 IREFE

AMPE0 : Operation control of operational amplifier
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operation amplifier is stopped.

#1 : 1

Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled.

End of enumeration elements list.

AMPE1 : Operation control of operational amplifier
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operation amplifier is stopped.

#1 : 1

Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled.

End of enumeration elements list.

AMPE2 : Operation control of operational amplifier
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operation amplifier is stopped.

#1 : 1

Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled.

End of enumeration elements list.

AMPE3 : Operation control of operational amplifier
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operation amplifier is stopped.

#1 : 1

Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled.

End of enumeration elements list.

IREFE : Operation control of operational amplifier reference current circuit
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operational amplifier reference current circuit is stopped.

#1 : 1

Operation of operational amplifier reference current circuit is enabled.

End of enumeration elements list.


AMPMON

Operational amplifier monitor register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AMPMON AMPMON read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPMON0 AMPMON1 AMPMON2 AMPMON3

AMPMON0 : Operational amplifier status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Operational amplifier is stopped.

#1 : 1

Operational amplifier is operating.

End of enumeration elements list.

AMPMON1 : Operational amplifier status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Operational amplifier is stopped.

#1 : 1

Operational amplifier is operating.

End of enumeration elements list.

AMPMON2 : Operational amplifier status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Operational amplifier is stopped.

#1 : 1

Operational amplifier is operating.

End of enumeration elements list.

AMPMON3 : Operational amplifier status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Operational amplifier is stopped.

#1 : 1

Operational amplifier is operating.

End of enumeration elements list.


AMPIO[0]-O

Output Select Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[0]-O AMPIO[0]-O read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

AMPIO[0]-M

Minus Input Select Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMPIO[0]-M AMPIO[0]-M read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.