Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
PDC Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCKE : Channel 0 GTCNT Count Clear
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operations for reception are stopped.
#1 : 1
Operations for reception are ongoing.
End of enumeration elements list.
VPS : VSYNC Signal Polarity Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
VSYNC signal is active high.
#1 : 1
VSYNC signal is active low.
End of enumeration elements list.
HPS : HSYNC Signal Polarity Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
HSYNC signal is active high.
#1 : 1
HSYNC signal is active low.
End of enumeration elements list.
PRST : PDC Reset
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
PDC reset is not applied.
#1 : 1
PDC is reset.
End of enumeration elements list.
DFIE : Receive Data Ready Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generation of receive data ready interrupt requests is disabled.
#1 : 1
Generation of receive data ready interrupt requests is enabled.
End of enumeration elements list.
FEIE : Frame End Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generation of frame end interrupt requests is disabled.
#1 : 1
Generation of frame end interrupt requests is enabled.
End of enumeration elements list.
OVIE : Overrun Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generation of overrun interrupt requests is disabled.
#1 : 1
Generation of overrun interrupt requests is enabled.
End of enumeration elements list.
UDRIE : Underrun Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generation of underrun interrupt requests is disabled.
#1 : 1
Generation of underrun interrupt requests is enabled.
End of enumeration elements list.
VERIE : Vertical Line Number Setting Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generation of vertical line number setting error interrupt requests is disabled.
#1 : 1
Generation of vertical line number setting error interrupt requests is enabled.
End of enumeration elements list.
HERIE : Horizontal Byte Number Setting Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generation of horizontal byte number setting error interrupt requests is disabled.
#1 : 1
Generation of horizontal byte number setting error interrupt requests is enabled.
End of enumeration elements list.
PCKOE : PCKO Output Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
PCKO output is disabled (fixed to the high level)
#1 : 1
PCKO output is enabled.
End of enumeration elements list.
PCKDIV : PCKO Frequency Division Ratio Select
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
#000 : 000
PCKO/2
#001 : 001
PCKO/4
#010 : 010
PCKO/6
#011 : 011
PCKO/8
#100 : 100
PCKO/10
#101 : 101
PCKO/12
#110 : 110
PCKO/14
#111 : 111
PCKO/16
End of enumeration elements list.
EDS : Endian Select
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
PDC Receive Data Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCDR : The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time.
bits : 0 - 30 (31 bit)
access : read-only
Vertical Capture Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VST : Vertical Capture Start Line PositionNumber of the line where capture is to start.
bits : 0 - 10 (11 bit)
access : read-write
VSZ : Vertical Capture Size Number of lines to be captured.
bits : 16 - 26 (11 bit)
access : read-write
Horizontal Capture Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HST : Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start.
bits : 0 - 10 (11 bit)
access : read-write
HSZ : Horizontal Capture Size Number of bytes to capture horizontally.
bits : 16 - 26 (11 bit)
access : read-write
PDC Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCE : PDC Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operations for reception are disabled.
#1 : 1
Operations for reception are enabled.
End of enumeration elements list.
PDC Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBSY : Frame Busy Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Operations for reception are stopped.
#1 : 1
Operations for reception are ongoing.
End of enumeration elements list.
FEMPF : FIFO Empty Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not empty.
#1 : 1
FIFO is empty.
End of enumeration elements list.
FEF : Frame End Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame end has not been generated.
#1 : 1
Frame end has been generated.
End of enumeration elements list.
OVRF : Overrun Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
FIFO overrun has not been generated.
#1 : 1
FIFO overrun has been generated.
End of enumeration elements list.
UDRF : Underrun Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Underrun has not been generated.
#1 : 1
Underrun has been generated.
End of enumeration elements list.
VERF : Vertical Line Number Setting Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Vertical line number setting error has not been generated.
#1 : 1
Vertical line number setting error has been generated.
End of enumeration elements list.
HERF : Horizontal Byte Number Setting Error Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Horizontal byte number setting error has not been generated.
#1 : 1
Horizontal byte number setting error has been generated.
End of enumeration elements list.
PDC Pin Monitor Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VSYNC : VSYNC Signal Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
VSYNC signal is at the low level.
#1 : 1
VSYNC signal is at the high level.
End of enumeration elements list.
HSYNC : HSYNC Signal Status Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
HSYNC signal is at the low level.
#1 : 1
HSYNC signal is at the high level.
End of enumeration elements list.
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