Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1D byte (0x0)
mem_usage : registers
protection : not protected
Serial Mode Register (SCMR.SMIF = 0)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKS : Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK clock
#01 : 01
PCLK/4 clock
#10 : 10
PCLK/16 clock
#11 : 11
PCLK/64 clock
End of enumeration elements list.
MP : Multi-Processor Mode(Valid only in asynchronous mode)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Multi-processor communications function is disabled
#1 : 1
Multi-processor communications function is enabled
End of enumeration elements list.
STOP : Stop Bit Length(Valid only in asynchronous mode)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
1 stop bit
#1 : 1
2 stop bits
End of enumeration elements list.
PM : Parity Mode (Valid only when the PE bit is 1)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Selects even parity
#1 : 1
Selects odd parity
End of enumeration elements list.
PE : Parity Enable(Valid only in asynchronous mode)
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving )
#1 : 1
The parity bit is added (transmitting) / The parity bit is checked (receiving)
End of enumeration elements list.
CHR : Character Length(Valid only in asynchronous mode)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1)
#1 : 1
Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1)
End of enumeration elements list.
CM : Communication Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous mode or simple I2C mode
#1 : 1
Clock synchronous mode
End of enumeration elements list.
Serial mode register (SCMR.SMIF = 1)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SMR
reset_Mask : 0x0
CKS : Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK clock
#01 : 01
PCLK/4 clock
#10 : 10
PCLK/16 clock
#11 : 11
PCLK/64 clock
End of enumeration elements list.
BCP : Base Clock Pulse(Valid only in asynchronous mode)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : 00
93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1)
#01 : 01
128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1)
#10 : 10
186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1)
#11 : 11
512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1)
End of enumeration elements list.
PM : Parity Mode (Valid only when the PE bit is 1)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Selects even parity
#1 : 1
Selects odd parity
End of enumeration elements list.
PE : Parity Enable(Valid only in asynchronous mode)
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Setting Prohibited
#1 : 1
Set this bit to 1 in smart card interface mode.
End of enumeration elements list.
BLK : Block Transfer Mode
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode operation
#1 : 1
Block transfer mode operation
End of enumeration elements list.
GM : GSM Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode operation
#1 : 1
GSM mode operation
End of enumeration elements list.
Bit Rate Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRR : BRR is an 8-bit register that adjusts the bit rate.
bits : 0 - 6 (7 bit)
access : read-write
Receive 9-bit Data Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRHL : RDRHL is an 16-bit register that stores receive data.
bits : 0 - 14 (15 bit)
access : read-only
Receive FIFO Data Register HL
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : RDRHL
reset_Mask : 0x0
RDAT : Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
bits : 0 - 7 (8 bit)
access : read-only
MPB : Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Data transmission cycles
#1 : 1
ID transmission cycles
End of enumeration elements list.
DR : Receive data ready flag(It is same as SSR.DR)
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving.
#1 : 1
Next receive data has not been received for a period after normal completed receiving.
End of enumeration elements list.
PER : Parity error flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
No parity error occurred at the first data of FRDRH and FRDRL.
#1 : 1
A parity error has occurred at the first data of FRDRH and FRDRL.
End of enumeration elements list.
FER : Framing error flag
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
No framing error occurred at the first data of FRDRH and FRDRL.
#1 : 1
A framing error has occurred at the first data of FRDRH and FRDRL.
End of enumeration elements list.
ORER : Overrun error flag(It is same as SSR.ORER)
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred.
#1 : 1
An overrun error has occurred.
End of enumeration elements list.
RDF : Receive FIFO data full flag(It is same as SSR.RDF)
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number.
#1 : 1
The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number.
End of enumeration elements list.
Receive FIFO Data Register H
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
alternate_register : RDRHL
reset_Mask : 0x0
RDATH : Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
bits : 0 - -1 (0 bit)
access : read-only
MPB : Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Data transmission cycles
#1 : 1
ID transmission cycles
End of enumeration elements list.
DR : Receive data ready flag(It is same as SSR.DR)
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving.
#1 : 1
Next receive data has not been received for a period after normal completed receiving.
End of enumeration elements list.
PER : Parity error flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
No parity error occurred at the first data of FRDRH and FRDRL
#1 : 1
A parity error has occurred at the first data of FRDRH and FRDRL
End of enumeration elements list.
FER : Framing error flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
No framing error occurred at the first data of FRDRH and FRDRL
#1 : 1
A framing error has occurred at the first data of FRDRH and FRDRL
End of enumeration elements list.
ORER : Overrun error flag(It is same as SSR.ORER)
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
An overrun error has occurred
End of enumeration elements list.
RDF : Receive FIFO data full flag(It is same as SSR.RDF)
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number.
#1 : 1
The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number.
End of enumeration elements list.
Receive FIFO Data Register L
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
alternate_register : RDRHL
reset_Mask : 0x0
RDATL : Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register.
bits : 0 - 6 (7 bit)
access : read-only
Modulation Duty Register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDDR : MDDR corrects the bit rate adjusted by the BRR register.
bits : 0 - 6 (7 bit)
access : read-write
Data Compare Match Control Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMF : Data Compare Match Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No matched
#1 : 1
Matched
End of enumeration elements list.
DPER : Data Compare Match Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
A parity error has occurred
End of enumeration elements list.
DFER : Data Compare Match Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No framing error occurred
#1 : 1
A framing error has occurred
End of enumeration elements list.
IDSEL : ID frame select(Valid only in asynchronous mode(including multi-processor)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Always compare data regardless of the value of the MPB bit.
#1 : 1
Compare data when the MPB bit is 1 (ID frame) only.
End of enumeration elements list.
DCME : Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Address match function is disabled.
#1 : 1
Address match function is enabled
End of enumeration elements list.
FIFO Control Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FM : FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-FIFO mode(Selects o TDR/RDR for communication)
#1 : 1
FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication)
End of enumeration elements list.
RFRST : Receive FIFO Data Register Reset(Valid only in FCR.FM=1)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
The number of data stored in FRDRH and FRDRL register are NOT made 0
#1 : 1
The number of data stored in FRDRH and FRDRL register are made 0
End of enumeration elements list.
TFRST : Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The number of data stored in FTDRH and FTDRL register are NOT made 0
#1 : 1
The number of data stored in FTDRH and FTDRL register are made 0
End of enumeration elements list.
DRES : Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
reception data full interrupt (RXI)
#1 : 1
receive error interrupt (ERI)
End of enumeration elements list.
TTRG : Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Trigger number 0
End of enumeration elements list.
RTRG : Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Trigger number 0
End of enumeration elements list.
RSTRG : RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Trigger number 0
End of enumeration elements list.
FIFO Data Count Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R : Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1)
bits : 0 - 3 (4 bit)
access : read-only
T : Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1)
bits : 8 - 11 (4 bit)
access : read-only
Line Status Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ORER : Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
An overrun error has occurred
End of enumeration elements list.
FNUM : Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL).
bits : 2 - 5 (4 bit)
access : read-only
PNUM : Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL).
bits : 8 - 11 (4 bit)
access : read-only
Compare Match Data Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPD : Compare Match DataCompare data pattern for address match wake-up function
bits : 0 - 7 (8 bit)
access : read-write
Serial Port Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMON : Serial input data monitor bit(The state of the RXD terminal is shown.)
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
RXD pin is low.
#1 : 1
RXD pin is high.
End of enumeration elements list.
SPB2DT : Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Low level is output on TXD pin
#1 : 1
High level is output on TXD pin
End of enumeration elements list.
SPB2IO : Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The value of SPB2DT bit is not output in TXD pin.
#1 : 1
The value of SPB2DT bit is output in TXD pin.
End of enumeration elements list.
Serial Control Register (SCMR.SMIF = 0)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKE : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)
#01 : 01
The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)
End of enumeration elements list.
TEIE : Transmit End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
SCI_TEI interrupt request is disabled
#1 : 1
SCI_TEI interrupt request is enabled
End of enumeration elements list.
MPIE : Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal reception
#1 : 1
When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed.
End of enumeration elements list.
RE : Receive Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Serial reception is disabled
#1 : 1
Serial reception is enabled
End of enumeration elements list.
TE : Transmit Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Serial transmission is disabled
#1 : 1
Serial transmission is enabled
End of enumeration elements list.
RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
SCI_RXI and SCI_ERI interrupt requests are disabled
#1 : 1
SCI_RXI and SCI_ERI interrupt requests are enabled
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
SCI_TXI interrupt request is disabled
#1 : 1
SCI_TXI interrupt request is enabled
End of enumeration elements list.
Serial Control Register (SCMR.SMIF =1)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SCR
reset_Mask : 0x0
CKE : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1)
#01 : 01
Clock Output
#10 : 10
Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1)
#11 : 11
Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1)
End of enumeration elements list.
TEIE : Transmit End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
MPIE : Multi-Processor Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
RE : Receive Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Serial reception is disabled
#1 : 1
Serial reception is enabled
End of enumeration elements list.
TE : Transmit Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Serial transmission is disabled
#1 : 1
Serial transmission is enabled
End of enumeration elements list.
RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
SCI_RXI and SCI_ERI interrupt requests are disabled
#1 : 1
SCI_RXI and SCI_ERI interrupt requests are enabled
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
A SCI_TXI interrupt request is disabled
#1 : 1
A SCI_TXI interrupt request is enabled
End of enumeration elements list.
Transmit Data Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDR : TDR is an 8-bit register that stores transmit data.
bits : 0 - 6 (7 bit)
access : read-write
Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPBT : Multi-Processor Bit Transfer
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data transmission cycles
#1 : 1
ID transmission cycles
End of enumeration elements list.
MPB : Multi-Processor
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Data transmission cycles
#1 : 1
ID transmission cycles
End of enumeration elements list.
TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
A character is being transmitted.
#1 : 1
Character transfer has been completed.
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
A parity error has occurred
End of enumeration elements list.
FER : Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No framing error occurred
#1 : 1
A framing error has occurred
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
An overrun error has occurred
End of enumeration elements list.
RDRF : Receive Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No received data is in RDR register
#1 : 1
Received data is in RDR register
End of enumeration elements list.
TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is in TDR register
#1 : 1
No transmit data is in TDR register
End of enumeration elements list.
Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SSR
reset_Mask : 0x0
DR : Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty)
#1 : 1
Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number.
End of enumeration elements list.
TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A character is being transmitted or standing by for transmission.
#1 : 1
Character transfer has been completed.
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred.
#1 : 1
A parity error has occurred.
End of enumeration elements list.
FER : Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No framing error occurred.
#1 : 1
A framing error has occurred.
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
An overrun error has occurred
End of enumeration elements list.
RDF : Receive FIFO data full flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The quantity of receive data written in FRDR falls below the specified receive triggering number.
#1 : 1
The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number.
End of enumeration elements list.
TDFE : Transmit FIFO data empty flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The quantity of transmit data written in FTDR exceeds the specified transmit triggering number.
#1 : 1
The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number
End of enumeration elements list.
Serial Status Register(SCMR.SMIF = 1)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SSR
reset_Mask : 0x0
MPBT : Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode.
bits : 0 - -1 (0 bit)
access : read-write
MPB : Multi-ProcessorThis bit should be 0 in smart card interface mode.
bits : 1 - 0 (0 bit)
access : read-only
TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
A character is being transmitted.
#1 : 1
Character transfer has been completed.
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
A parity error has occurred
End of enumeration elements list.
ERS : Error Signal Status Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Low error signal not responded
#1 : 1
Low error signal responded
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
An overrun error has occurred
End of enumeration elements list.
RDRF : Receive Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No received data is in RDR register
#1 : 1
Received data is in RDR register
End of enumeration elements list.
TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is in TDR register
#1 : 1
No transmit data is in TDR register
End of enumeration elements list.
Receive Data Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : RDR is an 8-bit register that stores receive data.
bits : 0 - 6 (7 bit)
access : read-only
Smart Card Mode Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMIF : Smart Card Interface Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode)
#1 : 1
Smart card interface mode
End of enumeration elements list.
SINV : Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TDR contents are transmitted as they are. Receive data is stored as it is in RDR.
#1 : 1
TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR.
End of enumeration elements list.
SDIR : Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer with LSB first
#1 : 1
Transfer with MSB first
End of enumeration elements list.
CHR1 : Character Length 1(Only valid in asynchronous mode)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit/receive in 9-bit data length
#1 : 1
Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1)
End of enumeration elements list.
BCP2 : Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11)
#1 : 1
S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11)
End of enumeration elements list.
Serial Extended Mode Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRME : Bit Rate Modulation Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bit rate modulation function is disabled.
#1 : 1
Bit rate modulation function is enabled.
End of enumeration elements list.
ABCSE : Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR.
#1 : 1
Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator.
End of enumeration elements list.
ABCS : Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Selects 16 base clock cycles for 1-bit period.
#1 : 1
Selects 8 base clock cycles for 1-bit period.
End of enumeration elements list.
NFEN : Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled.
#1 : 1
Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled.
End of enumeration elements list.
BGDM : Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode).
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Baud rate generator outputs the clock with normal frequency.
#1 : 1
Baud rate generator outputs the clock with doubled frequency.
End of enumeration elements list.
RXDESEL : Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The low level on the RXDn pin is detected as the start bit.
#1 : 1
A falling edge on the RXDn pin is detected as the start bit.
End of enumeration elements list.
Noise Filter Setting Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFCS : Noise Filter Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
The clock signal divided by 1 is used with the noise filter.(In asynchronous mode)
#001 : 001
The clock signal divided by 1 is used with the noise filter.(In simple I2C mode)
#010 : 010
The clock signal divided by 2 is used with the noise filter.(In simple I2C mode)
#011 : 011
The clock signal divided by 4 is used with the noise filter.(In simple I2C mode)
#100 : 100
The clock signal divided by 8 is used with the noise filter.(In simple I2C mode)
End of enumeration elements list.
I2C Mode Register 1
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IICM : Simple I2C Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1)
#1 : 1
Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1)
End of enumeration elements list.
IICDL : SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
#00000 : 00000
No output delay
End of enumeration elements list.
I2C Mode Register 2
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IICINTM : I2C Interrupt Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Use ACK/NACK interrupts.
#1 : 1
Use reception and transmission interrupts
End of enumeration elements list.
IICCSC : Clock Synchronization
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No synchronization with the clock signal
#1 : 1
Synchronization with the clock signal
End of enumeration elements list.
IICACKT : ACK Transmission Data
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
ACK transmission
#1 : 1
NACK transmission and reception of ACK/NACK
End of enumeration elements list.
I2C Mode Register 3
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IICSTAREQ : Start Condition Generation
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A start condition is not generated.
#1 : 1
A start condition is generated.
End of enumeration elements list.
IICRSTAREQ : Restart Condition Generation
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
A restart condition is not generated.
#1 : 1
A restart condition is generated.
End of enumeration elements list.
IICSTPREQ : Stop Condition Generation
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A stop condition is not generated.
#1 : 1
A stop condition is generated.
End of enumeration elements list.
IICSTIF : Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
There are no requests for generating conditions or a condition is being generated.
#1 : 1
A start, restart, or stop condition is completely generated.
End of enumeration elements list.
IICSDAS : SDA Output Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
Serial data output
#01 : 01
Generate a start, restart, or stop condition.
#10 : 10
Output the low level on the SSDAn pin.
#11 : 11
Place the SSDAn pin in the high-impedance state.
End of enumeration elements list.
IICSCLS : SCL Output Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Serial clock output
#01 : 01
Generate a start, restart, or stop condition.
#10 : 10
Output the low level on the SSCLn pin.
#11 : 11
Place the SSCLn pin in the high-impedance state.
End of enumeration elements list.
I2C Status Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IICACKR : ACK Reception Data Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
ACK received
#1 : 1
NACK received
End of enumeration elements list.
SPI Mode Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSE : SSn Pin Function Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSn pin function is disabled.
#1 : 1
SSn pin function is enabled.
End of enumeration elements list.
CTSE : CTS Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
CTS function is disabled (RTS output function is enabled).
#1 : 1
CTS function is enabled.
End of enumeration elements list.
MSS : Master Slave Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission is through the TXDn pin and reception is through the RXDn pin (master mode).
#1 : 1
Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode).
End of enumeration elements list.
MFF : Mode Fault Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No mode fault error
#1 : 1
Mode fault error
End of enumeration elements list.
CKPOL : Clock Polarity Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clock polarity is not inverted.
#1 : 1
Clock polarity is inverted
End of enumeration elements list.
CKPH : Clock Phase Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clock is not delayed.
#1 : 1
Clock is delayed.
End of enumeration elements list.
Transmit 9-bit Data Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRHL : TDRHL is a 16-bit register that stores transmit data.
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Data Register HL
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : TDRHL
reset_Mask : 0x0
TDAT : Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
bits : 0 - 7 (8 bit)
access : write-only
MPBT : Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
Data transmission cycles
#1 : 1
ID transmission cycles
End of enumeration elements list.
Transmit FIFO Data Register H
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
alternate_register : TDRHL
reset_Mask : 0x0
TDATH : Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
bits : 0 - -1 (0 bit)
access : write-only
MPBT : Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
Data transmission cycles
#1 : 1
ID transmission cycles
End of enumeration elements list.
Transmit FIFO Data Register L
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
alternate_register : TDRHL
reset_Mask : 0x0
TDATL : Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
bits : 0 - 6 (7 bit)
access : write-only
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