R_SYSTEM

VBTBKR : VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset.
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR[50]

VBATT Backup Register [%s]
address_offset : 0x108FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[51]

VBATT Backup Register [%s]
address_offset : 0x10E2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[52]

VBATT Backup Register [%s]
address_offset : 0x11362 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[53]

VBATT Backup Register [%s]
address_offset : 0x11897 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[54]

VBATT Backup Register [%s]
address_offset : 0x11DCD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[55]

VBATT Backup Register [%s]
address_offset : 0x12304 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[56]

VBATT Backup Register [%s]
address_offset : 0x1283C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[57]

VBATT Backup Register [%s]
address_offset : 0x12D75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[58]

VBATT Backup Register [%s]
address_offset : 0x132AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[59]

VBATT Backup Register [%s]
address_offset : 0x137EA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[60]

VBATT Backup Register [%s]
address_offset : 0x13D26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[2]

VBATT Backup Register [%s]
address_offset : 0x1403 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[61]

VBATT Backup Register [%s]
address_offset : 0x14263 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[62]

VBATT Backup Register [%s]
address_offset : 0x147A1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[63]

VBATT Backup Register [%s]
address_offset : 0x14CE0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[64]

VBATT Backup Register [%s]
address_offset : 0x15220 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[65]

VBATT Backup Register [%s]
address_offset : 0x15761 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[66]

VBATT Backup Register [%s]
address_offset : 0x15CA3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[67]

VBATT Backup Register [%s]
address_offset : 0x161E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[68]

VBATT Backup Register [%s]
address_offset : 0x1672A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[69]

VBATT Backup Register [%s]
address_offset : 0x16C6F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[70]

VBATT Backup Register [%s]
address_offset : 0x171B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[71]

VBATT Backup Register [%s]
address_offset : 0x176FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[72]

VBATT Backup Register [%s]
address_offset : 0x17C44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[73]

VBATT Backup Register [%s]
address_offset : 0x1818D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[74]

VBATT Backup Register [%s]
address_offset : 0x186D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[75]

VBATT Backup Register [%s]
address_offset : 0x18C22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[3]

VBATT Backup Register [%s]
address_offset : 0x1906 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[76]

VBATT Backup Register [%s]
address_offset : 0x1916E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[77]

VBATT Backup Register [%s]
address_offset : 0x196BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[78]

VBATT Backup Register [%s]
address_offset : 0x19C09 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[79]

VBATT Backup Register [%s]
address_offset : 0x1A158 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[80]

VBATT Backup Register [%s]
address_offset : 0x1A6A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[81]

VBATT Backup Register [%s]
address_offset : 0x1ABF9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[82]

VBATT Backup Register [%s]
address_offset : 0x1B14B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[83]

VBATT Backup Register [%s]
address_offset : 0x1B69E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[84]

VBATT Backup Register [%s]
address_offset : 0x1BBF2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTPCRA

Module Stop Control Register A
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTPA0 : RAM0 Module Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.

MSTPA1 : RAM1 Module Stop
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.

MSTPA5 : High-Speed RAM Module Stop
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.

MSTPA6 : ECCRAM Module Stop
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.

MSTPA7 : Standby RAM Module Stop
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.

MSTPA22 : DMA Controller/Data Transfer Controller Module Stop
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.

LVD1CR1

Voltage Monitor %s Circuit Control Register 1
address_offset : 0x1C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDTSEL : Voltage Monitor Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Generate when VCC>=Vdet (rise) is detected

#01 : 01

Generate when VCC

#10 : 10

Generate when drop and rise are detected

#11 : 11

Settings prohibited

End of enumeration elements list.

IRQSEL : Voltage Monitor Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Maskable interrupt

End of enumeration elements list.

VBTBKR[85]

VBATT Backup Register [%s]
address_offset : 0x1C147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1SR

Voltage Monitor %s Circuit Status Register
address_offset : 0x1C2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DET : Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not detected

#1 : 1

Vdet1 passage detection

End of enumeration elements list.

MON : Voltage Monitor 1 Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

VCC < Vdet

#1 : 1

VCC >= Vdet or MON bit is disabled

End of enumeration elements list.

VBTBKR[86]

VBATT Backup Register [%s]
address_offset : 0x1C69D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[87]

VBATT Backup Register [%s]
address_offset : 0x1CBF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[88]

VBATT Backup Register [%s]
address_offset : 0x1D14C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[89]

VBATT Backup Register [%s]
address_offset : 0x1D6A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[90]

VBATT Backup Register [%s]
address_offset : 0x1DBFF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[4]

VBATT Backup Register [%s]
address_offset : 0x1E0A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[91]

VBATT Backup Register [%s]
address_offset : 0x1E15A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[92]

VBATT Backup Register [%s]
address_offset : 0x1E6B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[93]

VBATT Backup Register [%s]
address_offset : 0x1EC13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[94]

VBATT Backup Register [%s]
address_offset : 0x1F171 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[95]

VBATT Backup Register [%s]
address_offset : 0x1F6D0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[96]

VBATT Backup Register [%s]
address_offset : 0x1FC30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCKDIVCR

System Clock Division Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCKD : Peripheral Module Clock D (PCLKD) Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

PCKC : Peripheral Module Clock C (PCLKC) Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

PCKB : Peripheral Module Clock B (PCLKB) Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

PCKA : Peripheral Module Clock A (PCLKA) Select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

BCK : External Bus Clock (BCLK) Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

ICK : System Clock (ICLK) Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

FCK : Flash IF Clock (FCLK) Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

End of enumeration elements list.

VBTBKR[97]

VBATT Backup Register [%s]
address_offset : 0x20191 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[98]

VBATT Backup Register [%s]
address_offset : 0x206F3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[99]

VBATT Backup Register [%s]
address_offset : 0x20C56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[100]

VBATT Backup Register [%s]
address_offset : 0x211BA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[101]

VBATT Backup Register [%s]
address_offset : 0x2171F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[102]

VBATT Backup Register [%s]
address_offset : 0x21C85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[103]

VBATT Backup Register [%s]
address_offset : 0x221EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[104]

VBATT Backup Register [%s]
address_offset : 0x22754 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[105]

VBATT Backup Register [%s]
address_offset : 0x22CBD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[5]

VBATT Backup Register [%s]
address_offset : 0x230F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[106]

VBATT Backup Register [%s]
address_offset : 0x23227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[107]

VBATT Backup Register [%s]
address_offset : 0x23792 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[108]

VBATT Backup Register [%s]
address_offset : 0x23CFE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCKDIVCR2

System Clock Division Control Register 2
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCK : USB Clock (UCLK) Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#010 : 010

#011 : 011

#100 : 100

End of enumeration elements list.

VBTBKR[109]

VBATT Backup Register [%s]
address_offset : 0x2426B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[110]

VBATT Backup Register [%s]
address_offset : 0x247D9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[111]

VBATT Backup Register [%s]
address_offset : 0x24D48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[112]

VBATT Backup Register [%s]
address_offset : 0x252B8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[113]

VBATT Backup Register [%s]
address_offset : 0x25829 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[114]

VBATT Backup Register [%s]
address_offset : 0x25D9B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCKSCR

System Clock Source Control Register
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKSEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

HOCO

#001 : 001

MOCO

#010 : 010

LOCO

#011 : 011

Main clock oscillator

#100 : 100

Sub-clock oscillator

#101 : 101

PLL

End of enumeration elements list.

VBTBKR[115]

VBATT Backup Register [%s]
address_offset : 0x2630E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[116]

VBATT Backup Register [%s]
address_offset : 0x26882 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[117]

VBATT Backup Register [%s]
address_offset : 0x26DF7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[118]

VBATT Backup Register [%s]
address_offset : 0x2736D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[119]

VBATT Backup Register [%s]
address_offset : 0x278E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[120]

VBATT Backup Register [%s]
address_offset : 0x27E5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCCR

PLL Clock Control Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLIDIV : PLL Input Frequency Division Ratio Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

#01 : 01

#10 : 10

#11 : 11

Setting prohibited

End of enumeration elements list.

PLSRCSEL : PLL Clock Source Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Main clock oscillator

#1 : 1

HOCO

End of enumeration elements list.

PLLMUL : PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VBTBKR[6]

VBATT Backup Register [%s]
address_offset : 0x2815 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[121]

VBATT Backup Register [%s]
address_offset : 0x283D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[122]

VBATT Backup Register [%s]
address_offset : 0x2894F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[123]

VBATT Backup Register [%s]
address_offset : 0x28ECA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[124]

VBATT Backup Register [%s]
address_offset : 0x29446 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[125]

VBATT Backup Register [%s]
address_offset : 0x299C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[126]

VBATT Backup Register [%s]
address_offset : 0x29F41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCR

PLL Control Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSTP : PLL Stop Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the PLL

#1 : 1

Stop the PLL.

End of enumeration elements list.

LVD2CR1

Voltage Monitor %s Circuit Control Register 1
address_offset : 0x2A2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDTSEL : Voltage Monitor Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Generate when VCC>=Vdet (rise) is detected

#01 : 01

Generate when VCC

#10 : 10

Generate when drop and rise are detected

#11 : 11

Settings prohibited

End of enumeration elements list.

IRQSEL : Voltage Monitor Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Maskable interrupt

End of enumeration elements list.

VBTBKR[127]

VBATT Backup Register [%s]
address_offset : 0x2A4C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD2SR

Voltage Monitor %s Circuit Status Register
address_offset : 0x2A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

#0 : 0

Not detected

#1 : 1

Vdet1 passage detection

End of enumeration elements list.

MON : Voltage Monitor 1 Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

VCC < Vdet

#1 : 1

VCC >= Vdet or MON bit is disabled

End of enumeration elements list.

VBTBKR[128]

VBATT Backup Register [%s]
address_offset : 0x2AA40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[129]

VBATT Backup Register [%s]
address_offset : 0x2AFC1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCCR2

PLL Clock Control Register2
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLMUL : PLL Frequency Multiplication Factor Select
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#1111 : 1111

Settings prohibited.

End of enumeration elements list.

PLODIV : PLL Output Frequency Division Ratio Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

/1.

#01 : 01

/2.

#10 : 10

/4.

#11 : 11

Setting prohibited.

End of enumeration elements list.

VBTBKR[130]

VBATT Backup Register [%s]
address_offset : 0x2B543 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[131]

VBATT Backup Register [%s]
address_offset : 0x2BAC6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[132]

VBATT Backup Register [%s]
address_offset : 0x2C04A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[133]

VBATT Backup Register [%s]
address_offset : 0x2C5CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[134]

VBATT Backup Register [%s]
address_offset : 0x2CB55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[135]

VBATT Backup Register [%s]
address_offset : 0x2D0DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[7]

VBATT Backup Register [%s]
address_offset : 0x2D1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[136]

VBATT Backup Register [%s]
address_offset : 0x2D664 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[137]

VBATT Backup Register [%s]
address_offset : 0x2DBED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[138]

VBATT Backup Register [%s]
address_offset : 0x2E177 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[139]

VBATT Backup Register [%s]
address_offset : 0x2E702 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[140]

VBATT Backup Register [%s]
address_offset : 0x2EC8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[141]

VBATT Backup Register [%s]
address_offset : 0x2F21B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[142]

VBATT Backup Register [%s]
address_offset : 0x2F7A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[143]

VBATT Backup Register [%s]
address_offset : 0x2FD38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCKCR

External Bus Clock Control Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCLKDIV : BCLK Pin Output Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

BCLK

#1 : 1

BCLK/2

End of enumeration elements list.

VBTBKR[144]

VBATT Backup Register [%s]
address_offset : 0x302C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[145]

VBATT Backup Register [%s]
address_offset : 0x30859 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[146]

VBATT Backup Register [%s]
address_offset : 0x30DEB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMWAIT

Memory Wait Cycle Control Register
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMWAIT : Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz).
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

no wait

#1 : 1

wait

End of enumeration elements list.

VBTBKR[147]

VBATT Backup Register [%s]
address_offset : 0x3137E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[148]

VBATT Backup Register [%s]
address_offset : 0x31912 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[149]

VBATT Backup Register [%s]
address_offset : 0x31EA7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSCCR

Main Clock Oscillator Control Register
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSTP : Main Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Main clock oscillator is operating.

#1 : 1

Main clock oscillator is stopped.

End of enumeration elements list.

VBTBKR[8]

VBATT Backup Register [%s]
address_offset : 0x3224 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[150]

VBATT Backup Register [%s]
address_offset : 0x3243D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[151]

VBATT Backup Register [%s]
address_offset : 0x329D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[152]

VBATT Backup Register [%s]
address_offset : 0x32F6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[153]

VBATT Backup Register [%s]
address_offset : 0x33505 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[154]

VBATT Backup Register [%s]
address_offset : 0x33A9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[155]

VBATT Backup Register [%s]
address_offset : 0x3403A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[156]

VBATT Backup Register [%s]
address_offset : 0x345D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[157]

VBATT Backup Register [%s]
address_offset : 0x34B73 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[158]

VBATT Backup Register [%s]
address_offset : 0x35111 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[159]

VBATT Backup Register [%s]
address_offset : 0x356B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[160]

VBATT Backup Register [%s]
address_offset : 0x35C50 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOCR

High-Speed On-Chip Oscillator Control Register
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCSTP : HOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the HOCO clock

#1 : 1

Stop the HOCO clock

End of enumeration elements list.

VBTBKR[161]

VBATT Backup Register [%s]
address_offset : 0x361F1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[162]

VBATT Backup Register [%s]
address_offset : 0x36793 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[163]

VBATT Backup Register [%s]
address_offset : 0x36D36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[9]

VBATT Backup Register [%s]
address_offset : 0x372D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[164]

VBATT Backup Register [%s]
address_offset : 0x372DA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[165]

VBATT Backup Register [%s]
address_offset : 0x3787F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[166]

VBATT Backup Register [%s]
address_offset : 0x37E25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOCR

Middle-Speed On-Chip Oscillator Control Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCSTP : MOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the MOCO clock

#1 : 1

Stop the MOCO clock

End of enumeration elements list.

VBTBKR[167]

VBATT Backup Register [%s]
address_offset : 0x383CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[168]

VBATT Backup Register [%s]
address_offset : 0x38974 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[169]

VBATT Backup Register [%s]
address_offset : 0x38F1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLLCR1

FLL Control Register 1
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLLEN : FLL Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

FLL function is disabled.

#1 : 1

FLL function is enabled.

End of enumeration elements list.

VBTBKR[170]

VBATT Backup Register [%s]
address_offset : 0x394C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[171]

VBATT Backup Register [%s]
address_offset : 0x39A72 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLLCR2

FLL Control Register 2
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLLCNTL : FLL Multiplication ControlMultiplication ratio of the FLL reference clock select
bits : 0 - 9 (10 bit)
access : read-write

VBTBKR[172]

VBATT Backup Register [%s]
address_offset : 0x3A01E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[173]

VBATT Backup Register [%s]
address_offset : 0x3A5CB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[174]

VBATT Backup Register [%s]
address_offset : 0x3AB79 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[175]

VBATT Backup Register [%s]
address_offset : 0x3B128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[176]

VBATT Backup Register [%s]
address_offset : 0x3B6D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[177]

VBATT Backup Register [%s]
address_offset : 0x3BC89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCSF

Oscillation Stabilization Flag Register
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOCOSF : HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1.
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

HOCO clock is stopped or is not yet stable

#1 : 1

HOCO clock is stable, so is available for use as the system clock

End of enumeration elements list.

MOSCSF : Main Clock Oscillation Stabilization Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Main clock oscillator is stopped (MOSTP = 1) or is not yet stable

#1 : 1

Main clock oscillator is stable, so is available for use as the system clock

End of enumeration elements list.

PLLSF : PLL Clock Oscillation Stabilization Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

PLL clock is stopped or is not yet stable

#1 : 1

PLL clock is stable, so is available for use as the system clock

End of enumeration elements list.

VBTBKR[178]

VBATT Backup Register [%s]
address_offset : 0x3C23B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[10]

VBATT Backup Register [%s]
address_offset : 0x3C37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[179]

VBATT Backup Register [%s]
address_offset : 0x3C7EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[180]

VBATT Backup Register [%s]
address_offset : 0x3CDA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[181]

VBATT Backup Register [%s]
address_offset : 0x3D357 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[182]

VBATT Backup Register [%s]
address_offset : 0x3D90D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[183]

VBATT Backup Register [%s]
address_offset : 0x3DEC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKOCR

Clock Out Control Register
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKOSEL : Clock out source select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

HOCO

#001 : 001

MOCO

#010 : 010

LOCO

#011 : 011

MOSC

#100 : 100

SOSC

End of enumeration elements list.

CKODIV : Clock out input frequency Division Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

#001 : 001

#010 : 010

#011 : 011

#100 : 100

/16

#101 : 101

/32

#110 : 110

/64

#111 : 111

/128

End of enumeration elements list.

CKOEN : Clock out enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable clock out

#1 : 1

Enable clock out

End of enumeration elements list.

VBTBKR[184]

VBATT Backup Register [%s]
address_offset : 0x3E47C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[185]

VBATT Backup Register [%s]
address_offset : 0x3EA35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[186]

VBATT Backup Register [%s]
address_offset : 0x3EFEF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCKCR

Trace Clock Control Register
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRCK : Trace Clock operating frequency select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

#0001 : 0001

#0010 : 0010

End of enumeration elements list.

TRCKEN : Trace Clock operating Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

VBTBKR[187]

VBATT Backup Register [%s]
address_offset : 0x3F5AA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[188]

VBATT Backup Register [%s]
address_offset : 0x3FB66 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRCR

Protect Register
address_offset : 0x3FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRC0 : Enables writing to the registers related to the clock generation circuit.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writes protected.

#1 : 1

Writes not protected.

End of enumeration elements list.

PRC1 : Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function.
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writes protected.

#1 : 1

Writes not protected.

End of enumeration elements list.

PRC3 : Enables writing to the registers related to the LVD.
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writes protected.

#1 : 1

Writes not protected.

End of enumeration elements list.

PRKEY : PRKEY Key Code
bits : 8 - 14 (7 bit)
access : write-only

Enumeration:

0x5A : 0x5A

Enables writing to the PRCR register.

End of enumeration elements list.

OSTDCR

Oscillation Stop Detection Control Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTDIE : Oscillation Stop Detection Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable oscillation stop detection interrupt (do not notify the POEG)

#1 : 1

Enable oscillation stop detection interrupt (notify the POEG)

End of enumeration elements list.

OSTDE : Oscillation Stop Detection Function Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable oscillation stop detection function

#1 : 1

Enable oscillation stop detection function

End of enumeration elements list.

DPSBYCR

Deep Standby Control Register
address_offset : 0x400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEEPCUT : Power-Supply Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode.

#01 : 01

Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode.

#10 : 10

Setting prohibited.

#11 : 11

Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.

End of enumeration elements list.

IOKEEP : I/O Port Retention
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.

#1 : 1

When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode.

End of enumeration elements list.

DPSBY : Deep Software Standby
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)

#1 : 1

Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)

End of enumeration elements list.

VBTBKR[189]

VBATT Backup Register [%s]
address_offset : 0x40123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIER2

Deep Standby Interrupt Enable Register 2
address_offset : 0x404 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLVD1IE : LVD1 Deep Standby Cancel Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DLVD2IE : LVD2 Deep Standby Cancel Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DTRTCIIE : RTC Interval interrupt Deep Standby Cancel Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DRTCAIE : RTC Alarm interrupt Deep Standby Cancel Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DNMIE : NMI Pin Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DPSIER3

Deep Standby Interrupt Enable Register 3
address_offset : 0x405 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUSBFSIE : USBFS Suspend/Resume Deep Standby Cancel Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DUSBHSIE : USBHS Suspend/Resume Deep Standby Cancel Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DAGT1IE : AGT1 Underflow Deep Standby Cancel Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

VBTBKR[190]

VBATT Backup Register [%s]
address_offset : 0x406E1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIFR2

Deep Standby Interrupt Flag Register 2
address_offset : 0x408 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLVD1IF : LVD1 Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DLVD2IF : LVD2 Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DTRTCIIF : RTC Interval interrupt Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DRTCAIF : RTC Alarm interrupt Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DNMIF : NMI Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIFR3

Deep Standby Interrupt Flag Register 3
address_offset : 0x409 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUSBFSIF : USBFS Suspend/Resume Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DUSBHSIF : USBHS Suspend/Resume Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DAGT1IF : AGT1 Underflow Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIEGR2

Deep Standby Interrupt Edge Register 2
address_offset : 0x40C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLVD1IEG : LVD1 Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated when VCC

#1 : 1

A cancel request is generated when VCC>=Vdet1 (rise) is detected

End of enumeration elements list.

DLVD2IEG : LVD2 Edge Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated when VCC

#1 : 1

A cancel request is generated when VCC>=Vdet2 (rise) is detected

End of enumeration elements list.

DNMIEG : NMI Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

VBTBKR[191]

VBATT Backup Register [%s]
address_offset : 0x40CA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYOCDCR

System Control OCD Control Register
address_offset : 0x40E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOCDF : Deep Standby OCD flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

On-chip debugger is disabled

#1 : 1

On-chip debugger is enabled

End of enumeration elements list.

DBGEN : Debugger Enable bit
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

On-chip debugger is disabled

#1 : 1

On-chip debugger is enabled

End of enumeration elements list.

STCONR

Standby Condition Register
address_offset : 0x40F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCON : SSTBY condition bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

set this value in case of transferring to Software Standby Mode in using HOCO.

#11 : 11

set this value in case of transferring to Software Standby Mode in using expect for HOCO.

End of enumeration elements list.

OSTDSR

Oscillation Stop Detection Status Register
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTDF : Oscillation Stop Detection Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Main clock oscillation stop not detected

#1 : 1

Main clock oscillation stop detected

End of enumeration elements list.

RSTSR0

Reset Status Register 0
address_offset : 0x410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORF : Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Power-on reset not detected.

#1 : 1

Power-on reset detected.

End of enumeration elements list.

LVD0RF : Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor 0 reset not detected.

#1 : 1

Voltage Monitor 0 reset detected.

End of enumeration elements list.

LVD1RF : Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor 1 reset not detected.

#1 : 1

Voltage Monitor 1 reset detected.

End of enumeration elements list.

LVD2RF : Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor 2 reset not detected.

#1 : 1

Voltage Monitor 2 reset detected.

End of enumeration elements list.

DPSRSTF : Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Deep software standby mode cancelation not requested by an interrupt.

#1 : 1

Deep software standby mode cancelation requested by an interrupt.

End of enumeration elements list.

RSTSR2

Reset Status Register 2
address_offset : 0x411 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWSF : Cold/Warm Start Determination Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cold start

#1 : 1

Warm start

End of enumeration elements list.

VBTBKR[192]

VBATT Backup Register [%s]
address_offset : 0x41260 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOMCR

Main Clock Oscillator Mode Oscillation Control Register
address_offset : 0x413 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODRV1 : Main Clock Oscillator Drive Capability 1 Switching
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

10 MHz to 20 MHz

#1 : 1

1 MHz to 10 MHz.

End of enumeration elements list.

MODRV0 : Main Clock Oscillator Drive Capability 0 Switching
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

20MHz to 24MHz

#01 : 01

16MHz to 20MHz

#10 : 10

8MHz to 16MHz

#11 : 11

8MHz

End of enumeration elements list.

MOSEL : Main Clock Oscillator Switching
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Resonator

#1 : 1

External clock input

End of enumeration elements list.

AUTODRVEN : Main Clock Oscillator Drive Capability Auto Switching Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable.

End of enumeration elements list.

VBTBKR[11]

VBATT Backup Register [%s]
address_offset : 0x4142 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FWEPROR

Flash P/E Protect Register
address_offset : 0x416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLWE : Flash Programming and Erasure
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Prohibits programming and erasure of the code flash, data flash or blank checking.

#01 : 01

Permits programming and erasure of the code flash, data flash or blank checking.

#10 : 10

Prohibits programming and erasure of the code flash, data flash or blank checking.

#11 : 11

Prohibits programming and erasure of the code flash, data flash or blank checking.

End of enumeration elements list.

LVCMPCR

Voltage Monitor Circuit Control Register
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1E : Voltage Detection 1 Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage detection 1 circuit disabled

#1 : 1

Voltage detection 1 circuit enabled

End of enumeration elements list.

LVD2E : Voltage Detection 2 Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage detection 2 circuit disabled

#1 : 1

Voltage detection 2 circuit enabled

End of enumeration elements list.

LVDLVLR

Voltage Detection Level Select Register
address_offset : 0x418 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1LVL : Voltage Detection 1 Level Select (Standard voltage during fall in voltage)
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#10001 : 10001

2.99V (Vdet1_1)

#10010 : 10010

2.92V (Vdet1_2)

#10011 : 10011

2.85V (Vdet1_3)

End of enumeration elements list.

LVD2LVL : Voltage Detection 2 Level Select (Standard voltage during fall in voltage)
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#101 : 101

2.99V (Vdet2_1)

#110 : 110

2.92V (Vdet2_2)

#111 : 111

2.85V (Vdet2_3)

End of enumeration elements list.

VBTBKR[193]

VBATT Backup Register [%s]
address_offset : 0x41821 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[194]

VBATT Backup Register [%s]
address_offset : 0x41DE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTCR1

VBATT Control Register1
address_offset : 0x41F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BPWSWSTP : Battery Power supply Switch Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Battery Power supply Switch Enable

#1 : 1

Battery Power supply Switch stop

End of enumeration elements list.

VBTBKR[195]

VBATT Backup Register [%s]
address_offset : 0x423A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[196]

VBATT Backup Register [%s]
address_offset : 0x4296A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[197]

VBATT Backup Register [%s]
address_offset : 0x42F2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[198]

VBATT Backup Register [%s]
address_offset : 0x434F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[199]

VBATT Backup Register [%s]
address_offset : 0x43ABC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[200]

VBATT Backup Register [%s]
address_offset : 0x44084 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[201]

VBATT Backup Register [%s]
address_offset : 0x4464D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[202]

VBATT Backup Register [%s]
address_offset : 0x44C17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[203]

VBATT Backup Register [%s]
address_offset : 0x451E2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[204]

VBATT Backup Register [%s]
address_offset : 0x457AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[205]

VBATT Backup Register [%s]
address_offset : 0x45D7B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[206]

VBATT Backup Register [%s]
address_offset : 0x46349 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[12]

VBATT Backup Register [%s]
address_offset : 0x464E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[207]

VBATT Backup Register [%s]
address_offset : 0x46918 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[208]

VBATT Backup Register [%s]
address_offset : 0x46EE8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[209]

VBATT Backup Register [%s]
address_offset : 0x474B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[210]

VBATT Backup Register [%s]
address_offset : 0x47A8B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSCCR

Sub-Clock Oscillator Control Register
address_offset : 0x480 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSTP : Sub-Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Sub-clock oscillator is operating.

#1 : 1

Sub-clock oscillator is stopped.

End of enumeration elements list.

VBTBKR[211]

VBATT Backup Register [%s]
address_offset : 0x4805E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOMCR

Sub Clock Oscillator Mode Control Register
address_offset : 0x481 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SODRV : Sub-Clock Oscillator Drive Capability Switching
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Normal mode

#01 : 01

Low power mode 1

#10 : 10

Low power mode 2

#11 : 11

Low power mode 3.

End of enumeration elements list.

VBTBKR[212]

VBATT Backup Register [%s]
address_offset : 0x48632 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[213]

VBATT Backup Register [%s]
address_offset : 0x48C07 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCOCR

Low-Speed On-Chip Oscillator Control Register
address_offset : 0x490 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCSTP : LOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

LOCO is operating.

#1 : 1

LOCO is stopped.

End of enumeration elements list.

VBTBKR[214]

VBATT Backup Register [%s]
address_offset : 0x491DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCOUTCR

LOCO User Trimming Control Register
address_offset : 0x492 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCOUTRM : LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR[215]

VBATT Backup Register [%s]
address_offset : 0x497B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[216]

VBATT Backup Register [%s]
address_offset : 0x49D8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[217]

VBATT Backup Register [%s]
address_offset : 0x4A365 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[218]

VBATT Backup Register [%s]
address_offset : 0x4A93F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[219]

VBATT Backup Register [%s]
address_offset : 0x4AF1A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTCR2

VBATT Control Register2
address_offset : 0x4B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTLVDEN : VBATT Pin Low Voltage Detect Enable Bit
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT pin low voltage detect disable

#1 : 1

VBATT pin low voltage detect enable

End of enumeration elements list.

VBTLVDLVL : VBATT Pin Voltage Low Voltage Detect Level Select Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

2.7V

#01 : 01

Setting prohibited

#10 : 10

2.3V

#11 : 11

2.1V

End of enumeration elements list.

VBTSR

VBATT Status Register
address_offset : 0x4B1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTRDF : VBAT_R Reset Detect Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT_R voltage power-on reset not detected

#1 : 1

VBATT_R selected voltage power-on reset detected.

End of enumeration elements list.

VBTBLDF : VBATT Battery Low voltage Detect Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT pin low voltage not detected

#1 : 1

VBATT pin low voltage detected.

End of enumeration elements list.

VBTRVLD : VBATT_R Valid
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

VBATT_R area not valid

#1 : 1

VBATT_R area valid

End of enumeration elements list.

VBTCMPCR

VBATT Comparator Control Register
address_offset : 0x4B2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTCMPE : VBATT pin low voltage detect circuit output enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT pin low voltage detect circuit output disabled

#1 : 1

VBATT pin low voltage detect circuit output enabled

End of enumeration elements list.

VBTLVDICR

VBATT Pin Low Voltage Detect Interrupt Control Register
address_offset : 0x4B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTLVDIE : VBATT Pin Low Voltage Detect Interrupt Enable bit
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT Pin Low Voltage Detect Interrupt Disable

#1 : 1

VBATT Pin Low Voltage Detect Interrupt Enable

End of enumeration elements list.

VBTLVDISEL : Pin Low Voltage Detect Interrupt Select bit
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non Maskable Interrupt

#1 : 1

Maskable Interrupt

End of enumeration elements list.

VBTBKR[220]

VBATT Backup Register [%s]
address_offset : 0x4B4F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[13]

VBATT Backup Register [%s]
address_offset : 0x4B5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTWCTLR

VBATT Wakeup function Control Register
address_offset : 0x4B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VWEN : VBATT wakeup enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable Wakeup function

#1 : 1

Enable Wakeup function

End of enumeration elements list.

VBTWCH0OTSR

VBATT Wakeup I/O 0 Output Trigger Select Register
address_offset : 0x4B8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0VCH1TE : VBATWIO0 Output VBATWIO1 Trigger Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled

#1 : 1

VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled.

End of enumeration elements list.

CH0VCH2TE : VBATWIO0 Output VBATWIO2 Trigger Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled

#1 : 1

VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled.

End of enumeration elements list.

CH0VRTCTE : VBATWIO0 Output RTC Periodic Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled

#1 : 1

VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled.

End of enumeration elements list.

CH0VRTCATE : VBATWIO0 Output RTC Alarm Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled

#1 : 1

VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled.

End of enumeration elements list.

CH0VAGTUTE : CH0 Output AGT(ch1) underflow Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is disabled

#1 : 1

VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is enabled

End of enumeration elements list.

VBTWCH1OTSR

VBATT Wakeup I/O 1 Output Trigger Select Register
address_offset : 0x4B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1VCH0TE : VBATWIO1 Output VBATWIO0 Trigger Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled

#1 : 1

VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled.

End of enumeration elements list.

CH1VCH2TE : VBATWIO1 Output VBATWIO2 Trigger Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled

#1 : 1

VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled.

End of enumeration elements list.

CH1VRTCTE : VBATWIO1 Output RTC Periodic Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled

#1 : 1

VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled

End of enumeration elements list.

CH1VRTCATE : VBATWIO1 Output RTC Alarm Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled

#1 : 1

VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled.

End of enumeration elements list.

CH1VAGTUTE : CH1 Output AGT(ch1) underflow Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is disabled

#1 : 1

VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is enabled

End of enumeration elements list.

VBTWCH2OTSR

VBATT Wakeup I/O 2 Output Trigger Select Register
address_offset : 0x4BA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2VCH0TE : VBATWIO2 Output VBATWIO0 Trigger Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled

#1 : 1

VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled.

End of enumeration elements list.

CH2VCH1TE : VBATWIO2 Output VBATWIO1 Trigger Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled

#1 : 1

VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled.

End of enumeration elements list.

CH2VRTCTE : VBATWIO2 Output RTC Periodic Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled

#1 : 1

VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled.

End of enumeration elements list.

CH2VRTCATE : VBATWIO2 Output RTC Alarm Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled

#1 : 1

VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled.

End of enumeration elements list.

CH2VAGTUTE : CH2 Output AGT(CH2) underflow Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is disabled

#1 : 1

VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is enabled

End of enumeration elements list.

VBTBKR[221]

VBATT Backup Register [%s]
address_offset : 0x4BAD3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTICTLR

VBATT Input Control Register
address_offset : 0x4BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCH0INEN : RTCIC0 Input Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

VCH1INEN : RTCIC1 Input Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

VCH2INEN : RTCIC2 Input Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

VBTOCTLR

VBATT Output Control Register
address_offset : 0x4BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCH0OEN : VBATT Wakeup I/O 0 Output Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATWIO0 output disabled

#1 : 1

VBATWIO0 output enabled

End of enumeration elements list.

VCH1OEN : VBATT Wakeup I/O 1 Output Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATWIO1 output disabled

#1 : 1

VBATWIO1 output enabled

End of enumeration elements list.

VCH2OEN : VBATT Wakeup I/O 2 Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATWIO2 output disabled

#1 : 1

VBATWIO2 output enabled

End of enumeration elements list.

VOUT0LSEL : VBATT Wakeup I/O 0 Output Level Selection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output L before VBATT wakeup trigger

#1 : 1

Output H before VBATT wakeup trigger

End of enumeration elements list.

VCOU1LSEL : VBATT Wakeup I/O 1 Output Level Selection
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output L before VBATT wake up trigger

#1 : 1

Output H before VBATT wake up trigger

End of enumeration elements list.

VOUT2LSEL : VBATT Wakeup I/O 2 Output Level Selection
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output L before VBATT wake up trigger

#1 : 1

Output H before VBATT wake up trigger

End of enumeration elements list.

VBTWTER

VBATT Wakeup Trigger source Enable Register
address_offset : 0x4BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCH0E : VBATWIO0 Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup triggered by the VBATWIO0 pin is disabled

#1 : 1

VBATT wakeup triggered by the VBATWIO0 pin is enabled.

End of enumeration elements list.

VCH1E : VBATWIO1 Pin Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup triggered by the VBATWIO1 pin is disabled

#1 : 1

VBATT wakeup triggered by the VBATWIO1 pin is enabled.

End of enumeration elements list.

VCH2E : VBATWIO2 Pin Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup triggered by the VBATWIO2 pin is disabled

#1 : 1

VBATT wakeup triggered by the VBATWIO2 pin is enabled.

End of enumeration elements list.

VRTCIE : RTC Periodic Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup triggered by RTC periodic signal is disabled

#1 : 1

VBATT wakeup triggered by RTC periodic signal is enabled.

End of enumeration elements list.

VRTCAE : RTC Alarm Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup triggered by RTC alarm signal is disabled

#1 : 1

VBATT wakeup triggered by RTC alarm signal is enabled.

End of enumeration elements list.

VAGTUE : AGT(ch1) underflow Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBATT wakeup triggered by the AGT(ch1) underflow signal is disabled

#1 : 1

VBATT wakeup triggered by the AGT(ch1) underflow signal is enabled

End of enumeration elements list.

VBTWEGR

VBATT Wakeup Trigger source Edge Register
address_offset : 0x4BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCH0EG : VBATWIO0 Wakeup Trigger Source Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Wakeup trigger is generated at a falling edge

#1 : 1

Wakeup trigger is generated at a rising edge.

End of enumeration elements list.

VCH1EG : VBATWIO1 Wakeup Trigger Source Edge Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Wakeup trigger is generated at a falling edge

#1 : 1

Wakeup trigger is generated at a rising edge.

End of enumeration elements list.

VCH2EG : VBATWIO2 Wakeup Trigger Source Edge Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Wakeup trigger is generated at a falling edge

#1 : 1

Wakeup trigger is generated at a rising edge.

End of enumeration elements list.

VBTWFR

VBATT Wakeup trigger source Flag Register
address_offset : 0x4BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCH0F : VBATWIO0 Wakeup Trigger Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wakeup trigger by the VBATWIO0 pin is generated

#1 : 1

A wakeup trigger by the VBATWIO0 pin is generated

End of enumeration elements list.

VCH1F : VBATWIO1 Wakeup Trigger Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wakeup trigger by the VBATWIO1 pin is generated

#1 : 1

A wakeup trigger by the VBATWIO1 pin is generated

End of enumeration elements list.

VCH2F : VBATWIO2 Wakeup Trigger Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wakeup trigger by the VBATWIO2 pin is generated

#1 : 1

A wakeup trigger by the VBATWIO2 pin is generated

End of enumeration elements list.

VRTCIF : VBATT RTC-Interval Wakeup Trigger Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wakeup trigger by the RTC interval is generated

#1 : 1

A wakeup trigger by the RTC interval is generated

End of enumeration elements list.

VRTCAF : VBATT RTC-Alarm Wakeup Trigger Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wakeup trigger by the RTC alarm is generated

#1 : 1

A wakeup trigger by the RTC alarm is generated

End of enumeration elements list.

VAGTUF : AGT(ch1) underflow VBATT Wakeup Trigger Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wakeup trigger by the AGT(ch1) underflow is generated

#1 : 1

A wakeup trigger by the AGT(ch1) underflow is generated

End of enumeration elements list.

VBTBKR[222]

VBATT Backup Register [%s]
address_offset : 0x4C0B1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[223]

VBATT Backup Register [%s]
address_offset : 0x4C690 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[224]

VBATT Backup Register [%s]
address_offset : 0x4CC70 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[225]

VBATT Backup Register [%s]
address_offset : 0x4D251 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[226]

VBATT Backup Register [%s]
address_offset : 0x4D833 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[227]

VBATT Backup Register [%s]
address_offset : 0x4DE16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[228]

VBATT Backup Register [%s]
address_offset : 0x4E3FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[229]

VBATT Backup Register [%s]
address_offset : 0x4E9DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[230]

VBATT Backup Register [%s]
address_offset : 0x4EFC5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[231]

VBATT Backup Register [%s]
address_offset : 0x4F5AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[232]

VBATT Backup Register [%s]
address_offset : 0x4FB94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLCDSCKCR

Segment LCD Source Clock Control Register
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCDSCKSEL : LCD Source Clock (LCDSRCCLK) Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

LOCO

#001 : 001

SOSC

#010 : 010

MOSC

#100 : 100

HOCO

End of enumeration elements list.

LCDSCKEN : LCD Source Clock Out Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

LCD source clock out disabled

#1 : 1

LCD source clock out enabled.

End of enumeration elements list.

VBTBKR[233]

VBATT Backup Register [%s]
address_offset : 0x5017D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[14]

VBATT Backup Register [%s]
address_offset : 0x5069 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[234]

VBATT Backup Register [%s]
address_offset : 0x50767 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[235]

VBATT Backup Register [%s]
address_offset : 0x50D52 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[236]

VBATT Backup Register [%s]
address_offset : 0x5133E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[237]

VBATT Backup Register [%s]
address_offset : 0x5192B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[238]

VBATT Backup Register [%s]
address_offset : 0x51F19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EBCKOCR

External Bus Clock Output Control Register
address_offset : 0x52 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EBCKOEN : BCLK Pin Output Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable EBCLK pin output (fixed high)

#1 : 1

Enable EBCLK pin output

End of enumeration elements list.

VBTBKR[239]

VBATT Backup Register [%s]
address_offset : 0x52508 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[240]

VBATT Backup Register [%s]
address_offset : 0x52AF8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCKOCR

SDRAM Clock Output Control Register
address_offset : 0x53 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCKOEN : SDCLK Pin Output Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SDCLK pin output (fixed high)

#1 : 1

Enable SDCLK pin output

End of enumeration elements list.

VBTBKR[241]

VBATT Backup Register [%s]
address_offset : 0x530E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[242]

VBATT Backup Register [%s]
address_offset : 0x536DB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[243]

VBATT Backup Register [%s]
address_offset : 0x53CCE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[244]

VBATT Backup Register [%s]
address_offset : 0x542C2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[245]

VBATT Backup Register [%s]
address_offset : 0x548B7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[246]

VBATT Backup Register [%s]
address_offset : 0x54EAD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[247]

VBATT Backup Register [%s]
address_offset : 0x554A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[15]

VBATT Backup Register [%s]
address_offset : 0x5578 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[248]

VBATT Backup Register [%s]
address_offset : 0x55A9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[249]

VBATT Backup Register [%s]
address_offset : 0x56095 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[250]

VBATT Backup Register [%s]
address_offset : 0x5668F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[251]

VBATT Backup Register [%s]
address_offset : 0x56C8A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[252]

VBATT Backup Register [%s]
address_offset : 0x57286 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[253]

VBATT Backup Register [%s]
address_offset : 0x57883 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[254]

VBATT Backup Register [%s]
address_offset : 0x57E81 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[255]

VBATT Backup Register [%s]
address_offset : 0x58480 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[256]

VBATT Backup Register [%s]
address_offset : 0x58A80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[257]

VBATT Backup Register [%s]
address_offset : 0x59081 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[258]

VBATT Backup Register [%s]
address_offset : 0x59683 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[259]

VBATT Backup Register [%s]
address_offset : 0x59C86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[260]

VBATT Backup Register [%s]
address_offset : 0x5A28A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[16]

VBATT Backup Register [%s]
address_offset : 0x5A88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[261]

VBATT Backup Register [%s]
address_offset : 0x5A88F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[262]

VBATT Backup Register [%s]
address_offset : 0x5AE95 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[263]

VBATT Backup Register [%s]
address_offset : 0x5B49C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[264]

VBATT Backup Register [%s]
address_offset : 0x5BAA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[265]

VBATT Backup Register [%s]
address_offset : 0x5C0AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[266]

VBATT Backup Register [%s]
address_offset : 0x5C6B7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[267]

VBATT Backup Register [%s]
address_offset : 0x5CCC2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[268]

VBATT Backup Register [%s]
address_offset : 0x5D2CE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[269]

VBATT Backup Register [%s]
address_offset : 0x5D8DB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[270]

VBATT Backup Register [%s]
address_offset : 0x5DEE9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[271]

VBATT Backup Register [%s]
address_offset : 0x5E4F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[272]

VBATT Backup Register [%s]
address_offset : 0x5EB08 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[273]

VBATT Backup Register [%s]
address_offset : 0x5F119 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[274]

VBATT Backup Register [%s]
address_offset : 0x5F72B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[17]

VBATT Backup Register [%s]
address_offset : 0x5F99 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[275]

VBATT Backup Register [%s]
address_offset : 0x5FD3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[276]

VBATT Backup Register [%s]
address_offset : 0x60352 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[277]

VBATT Backup Register [%s]
address_offset : 0x60967 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[278]

VBATT Backup Register [%s]
address_offset : 0x60F7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOUTCR

MOCO User Trimming Control Register
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOUTRM : MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR[279]

VBATT Backup Register [%s]
address_offset : 0x61594 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[280]

VBATT Backup Register [%s]
address_offset : 0x61BAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOUTCR

HOCO User Trimming Control Register
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOUTRM : HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits
bits : 0 - 6 (7 bit)
access : read-write

VBTBKR[281]

VBATT Backup Register [%s]
address_offset : 0x621C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[282]

VBATT Backup Register [%s]
address_offset : 0x627DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[283]

VBATT Backup Register [%s]
address_offset : 0x62DFA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[284]

VBATT Backup Register [%s]
address_offset : 0x63416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[285]

VBATT Backup Register [%s]
address_offset : 0x63A33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[286]

VBATT Backup Register [%s]
address_offset : 0x64051 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[287]

VBATT Backup Register [%s]
address_offset : 0x64670 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[18]

VBATT Backup Register [%s]
address_offset : 0x64AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[288]

VBATT Backup Register [%s]
address_offset : 0x64C90 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[289]

VBATT Backup Register [%s]
address_offset : 0x652B1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[290]

VBATT Backup Register [%s]
address_offset : 0x658D3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[291]

VBATT Backup Register [%s]
address_offset : 0x65EF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[292]

VBATT Backup Register [%s]
address_offset : 0x6651A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[293]

VBATT Backup Register [%s]
address_offset : 0x66B3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[294]

VBATT Backup Register [%s]
address_offset : 0x67165 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[295]

VBATT Backup Register [%s]
address_offset : 0x6778C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[296]

VBATT Backup Register [%s]
address_offset : 0x67DB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[297]

VBATT Backup Register [%s]
address_offset : 0x683DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[298]

VBATT Backup Register [%s]
address_offset : 0x68A07 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[299]

VBATT Backup Register [%s]
address_offset : 0x69032 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[300]

VBATT Backup Register [%s]
address_offset : 0x6965E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[19]

VBATT Backup Register [%s]
address_offset : 0x69BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[301]

VBATT Backup Register [%s]
address_offset : 0x69C8B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[302]

VBATT Backup Register [%s]
address_offset : 0x6A2B9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[303]

VBATT Backup Register [%s]
address_offset : 0x6A8E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[304]

VBATT Backup Register [%s]
address_offset : 0x6AF18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[305]

VBATT Backup Register [%s]
address_offset : 0x6B549 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[306]

VBATT Backup Register [%s]
address_offset : 0x6BB7B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[307]

VBATT Backup Register [%s]
address_offset : 0x6C1AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[308]

VBATT Backup Register [%s]
address_offset : 0x6C7E2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[309]

VBATT Backup Register [%s]
address_offset : 0x6CE17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[310]

VBATT Backup Register [%s]
address_offset : 0x6D44D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[311]

VBATT Backup Register [%s]
address_offset : 0x6DA84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[312]

VBATT Backup Register [%s]
address_offset : 0x6E0BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[313]

VBATT Backup Register [%s]
address_offset : 0x6E6F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[20]

VBATT Backup Register [%s]
address_offset : 0x6ED2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[314]

VBATT Backup Register [%s]
address_offset : 0x6ED2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[315]

VBATT Backup Register [%s]
address_offset : 0x6F36A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[316]

VBATT Backup Register [%s]
address_offset : 0x6F9A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[317]

VBATT Backup Register [%s]
address_offset : 0x6FFE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[318]

VBATT Backup Register [%s]
address_offset : 0x70621 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[319]

VBATT Backup Register [%s]
address_offset : 0x70C60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[320]

VBATT Backup Register [%s]
address_offset : 0x712A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[321]

VBATT Backup Register [%s]
address_offset : 0x718E1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[322]

VBATT Backup Register [%s]
address_offset : 0x71F23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[323]

VBATT Backup Register [%s]
address_offset : 0x72566 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[324]

VBATT Backup Register [%s]
address_offset : 0x72BAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[325]

VBATT Backup Register [%s]
address_offset : 0x731EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[326]

VBATT Backup Register [%s]
address_offset : 0x73835 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[21]

VBATT Backup Register [%s]
address_offset : 0x73E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[327]

VBATT Backup Register [%s]
address_offset : 0x73E7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[328]

VBATT Backup Register [%s]
address_offset : 0x744C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[329]

VBATT Backup Register [%s]
address_offset : 0x74B0D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[330]

VBATT Backup Register [%s]
address_offset : 0x75157 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[331]

VBATT Backup Register [%s]
address_offset : 0x757A2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[332]

VBATT Backup Register [%s]
address_offset : 0x75DEE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[333]

VBATT Backup Register [%s]
address_offset : 0x7643B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[334]

VBATT Backup Register [%s]
address_offset : 0x76A89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[335]

VBATT Backup Register [%s]
address_offset : 0x770D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[336]

VBATT Backup Register [%s]
address_offset : 0x77728 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[337]

VBATT Backup Register [%s]
address_offset : 0x77D79 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[338]

VBATT Backup Register [%s]
address_offset : 0x783CB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[339]

VBATT Backup Register [%s]
address_offset : 0x78A1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[22]

VBATT Backup Register [%s]
address_offset : 0x78FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[340]

VBATT Backup Register [%s]
address_offset : 0x79072 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[341]

VBATT Backup Register [%s]
address_offset : 0x796C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[342]

VBATT Backup Register [%s]
address_offset : 0x79D1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[343]

VBATT Backup Register [%s]
address_offset : 0x7A374 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[344]

VBATT Backup Register [%s]
address_offset : 0x7A9CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[345]

VBATT Backup Register [%s]
address_offset : 0x7B025 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[346]

VBATT Backup Register [%s]
address_offset : 0x7B67F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[347]

VBATT Backup Register [%s]
address_offset : 0x7BCDA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[348]

VBATT Backup Register [%s]
address_offset : 0x7C336 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[349]

VBATT Backup Register [%s]
address_offset : 0x7C993 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[350]

VBATT Backup Register [%s]
address_offset : 0x7CFF1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[351]

VBATT Backup Register [%s]
address_offset : 0x7D650 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[352]

VBATT Backup Register [%s]
address_offset : 0x7DCB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[23]

VBATT Backup Register [%s]
address_offset : 0x7E14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[353]

VBATT Backup Register [%s]
address_offset : 0x7E311 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[354]

VBATT Backup Register [%s]
address_offset : 0x7E973 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[355]

VBATT Backup Register [%s]
address_offset : 0x7EFD6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[356]

VBATT Backup Register [%s]
address_offset : 0x7F63A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[357]

VBATT Backup Register [%s]
address_offset : 0x7FC9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[358]

VBATT Backup Register [%s]
address_offset : 0x80305 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIER0

Deep Standby Interrupt Enable Register %s
address_offset : 0x804 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ0E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ1E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ2E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ3E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ4E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ5E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ6E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

DIRQ7E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

VBTBKR[359]

VBATT Backup Register [%s]
address_offset : 0x8096C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIFR0

Deep Standby Interrupt Flag Register %s
address_offset : 0x80C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ0F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ1F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ2F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ3F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ4F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ5F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ6F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DIRQ7F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

VBTBKR[360]

VBATT Backup Register [%s]
address_offset : 0x80FD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIEGR0

Deep Standby Interrupt Edge Register %s
address_offset : 0x814 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ0EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ1EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ2EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ3EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ4EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ5EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ6EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

DIRQ7EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

VBTBKR[361]

VBATT Backup Register [%s]
address_offset : 0x8163D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[362]

VBATT Backup Register [%s]
address_offset : 0x81CA7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[363]

VBATT Backup Register [%s]
address_offset : 0x82312 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[364]

VBATT Backup Register [%s]
address_offset : 0x8297E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[365]

VBATT Backup Register [%s]
address_offset : 0x82FEB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[24]

VBATT Backup Register [%s]
address_offset : 0x832C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1CR0

Voltage Monitor %s Circuit Control Register 0
address_offset : 0x834 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIE : Voltage Monitor Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

DFDIS : Voltage Monitor Digital Filter Disable Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable digital filter

#1 : 1

Disable digital filter

End of enumeration elements list.

CMPE : Voltage Monitor Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable voltage monitor 1 circuit comparison result output

#1 : 1

Enable voltage monitor 1 circuit comparison result output.

End of enumeration elements list.

FSAMP : Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

1/2 LOCO frequency

#01 : 01

1/4 LOCO frequency

#10 : 10

1/8 LOCO frequency

#11 : 11

1/16 LOCO frequency

End of enumeration elements list.

RI : Voltage Monitor Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor interrupt during Vdet1 passage

#1 : 1

Voltage Monitor reset enabled when the voltage falls to and below Vdet1

End of enumeration elements list.

RN : Voltage Monitor Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negation follows a stabilization time (tLVD) after VCC > Vdet is detected.

#1 : 1

Negation follows a stabilization time (tLVD) after assertion of the LVD reset.

End of enumeration elements list.

VBTBKR[366]

VBATT Backup Register [%s]
address_offset : 0x83659 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[367]

VBATT Backup Register [%s]
address_offset : 0x83CC8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[368]

VBATT Backup Register [%s]
address_offset : 0x84338 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[369]

VBATT Backup Register [%s]
address_offset : 0x849A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[370]

VBATT Backup Register [%s]
address_offset : 0x8501B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[371]

VBATT Backup Register [%s]
address_offset : 0x8568E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[372]

VBATT Backup Register [%s]
address_offset : 0x85D02 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[373]

VBATT Backup Register [%s]
address_offset : 0x86377 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[374]

VBATT Backup Register [%s]
address_offset : 0x869ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[375]

VBATT Backup Register [%s]
address_offset : 0x87064 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[376]

VBATT Backup Register [%s]
address_offset : 0x876DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[377]

VBATT Backup Register [%s]
address_offset : 0x87D55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[378]

VBATT Backup Register [%s]
address_offset : 0x883CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[25]

VBATT Backup Register [%s]
address_offset : 0x8845 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[379]

VBATT Backup Register [%s]
address_offset : 0x88A4A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[380]

VBATT Backup Register [%s]
address_offset : 0x890C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[381]

VBATT Backup Register [%s]
address_offset : 0x89743 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[382]

VBATT Backup Register [%s]
address_offset : 0x89DC1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[383]

VBATT Backup Register [%s]
address_offset : 0x8A440 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[384]

VBATT Backup Register [%s]
address_offset : 0x8AAC0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[385]

VBATT Backup Register [%s]
address_offset : 0x8B141 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[386]

VBATT Backup Register [%s]
address_offset : 0x8B7C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[387]

VBATT Backup Register [%s]
address_offset : 0x8BE46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[388]

VBATT Backup Register [%s]
address_offset : 0x8C4CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[389]

VBATT Backup Register [%s]
address_offset : 0x8CB4F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[390]

VBATT Backup Register [%s]
address_offset : 0x8D1D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[26]

VBATT Backup Register [%s]
address_offset : 0x8D5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[391]

VBATT Backup Register [%s]
address_offset : 0x8D85C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[392]

VBATT Backup Register [%s]
address_offset : 0x8DEE4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[393]

VBATT Backup Register [%s]
address_offset : 0x8E56D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[394]

VBATT Backup Register [%s]
address_offset : 0x8EBF7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[395]

VBATT Backup Register [%s]
address_offset : 0x8F282 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[396]

VBATT Backup Register [%s]
address_offset : 0x8F90E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[397]

VBATT Backup Register [%s]
address_offset : 0x8FF9B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[398]

VBATT Backup Register [%s]
address_offset : 0x90629 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[399]

VBATT Backup Register [%s]
address_offset : 0x90CB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[400]

VBATT Backup Register [%s]
address_offset : 0x91348 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[401]

VBATT Backup Register [%s]
address_offset : 0x919D9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZCR

Snooze Control Register
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXDREQEN : RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Ignore RXD0 falling edge in Standby mode.

#1 : 1

Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode.

End of enumeration elements list.

SNZDTCEN : DTC Enable in Snooze Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable DTC operation

#1 : 1

Enable DTC operation

End of enumeration elements list.

SNZE : Snooze Mode Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable Snooze Mode

#1 : 1

Enable Snooze Mode

End of enumeration elements list.

VBTBKR[402]

VBATT Backup Register [%s]
address_offset : 0x9206B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[403]

VBATT Backup Register [%s]
address_offset : 0x926FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[27]

VBATT Backup Register [%s]
address_offset : 0x927A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[404]

VBATT Backup Register [%s]
address_offset : 0x92D92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[405]

VBATT Backup Register [%s]
address_offset : 0x93427 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[406]

VBATT Backup Register [%s]
address_offset : 0x93ABD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZEDCR

Snooze End Control Register
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGT1UNFED : AGT1 underflow Snooze End Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

DTCZRED : Last DTC transmission completion Snooze End Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

DTCNZRED : Not Last DTC transmission completion Snooze End Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD0MATED : AD compare match 0 Snooze End Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD0UMTED : AD compare mismatch 0 Snooze End Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD1MATED : AD compare match 1 Snooze End Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

AD1UMTED : AD compare mismatch 1 Snooze End Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

SCI0UMTED : SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode.
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Snooze End request

#1 : 1

Enable the Snooze End request

End of enumeration elements list.

VBTBKR[407]

VBATT Backup Register [%s]
address_offset : 0x94154 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[408]

VBATT Backup Register [%s]
address_offset : 0x947EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[409]

VBATT Backup Register [%s]
address_offset : 0x94E85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[410]

VBATT Backup Register [%s]
address_offset : 0x9551F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[411]

VBATT Backup Register [%s]
address_offset : 0x95BBA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[412]

VBATT Backup Register [%s]
address_offset : 0x96256 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[413]

VBATT Backup Register [%s]
address_offset : 0x968F3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[414]

VBATT Backup Register [%s]
address_offset : 0x96F91 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[415]

VBATT Backup Register [%s]
address_offset : 0x97630 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[28]

VBATT Backup Register [%s]
address_offset : 0x9796 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[416]

VBATT Backup Register [%s]
address_offset : 0x97CD0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZREQCR

Snooze Request Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZREQEN0 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN1 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN2 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN3 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN4 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN5 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN6 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN7 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN8 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN9 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN10 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN11 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN12 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN13 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN14 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN15 : Snooze Request Enable 0Enable IRQ %s pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN17 : Snooze Request Enable 17Enable KR snooze request
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN22 : Snooze Request Enable 22Enable Comparator-HS0 snooze request
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN23 : Snooze Request Enable 23Enable Comparator-LP0 snooze request
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN24 : Snooze Request Enable 24Enable RTC alarm snooze request
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN25 : Snooze Request Enable 25Enable RTC period snooze request
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN28 : Snooze Request Enable 28Enable AGT1 underflow snooze request
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN29 : Snooze Request Enable 29Enable AGT1 compare match A snooze request
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

SNZREQEN30 : Snooze Request Enable 30Enable AGT1 compare match B snooze request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable snooze request

#1 : 1

Enable snooze request

End of enumeration elements list.

VBTBKR[417]

VBATT Backup Register [%s]
address_offset : 0x98371 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[418]

VBATT Backup Register [%s]
address_offset : 0x98A13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[419]

VBATT Backup Register [%s]
address_offset : 0x990B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[420]

VBATT Backup Register [%s]
address_offset : 0x9975A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[421]

VBATT Backup Register [%s]
address_offset : 0x99DFF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[422]

VBATT Backup Register [%s]
address_offset : 0x9A4A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[423]

VBATT Backup Register [%s]
address_offset : 0x9AB4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[424]

VBATT Backup Register [%s]
address_offset : 0x9B1F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[425]

VBATT Backup Register [%s]
address_offset : 0x9B89D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[426]

VBATT Backup Register [%s]
address_offset : 0x9BF47 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[427]

VBATT Backup Register [%s]
address_offset : 0x9C5F2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[29]

VBATT Backup Register [%s]
address_offset : 0x9CB3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[428]

VBATT Backup Register [%s]
address_offset : 0x9CC9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[429]

VBATT Backup Register [%s]
address_offset : 0x9D34B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[430]

VBATT Backup Register [%s]
address_offset : 0x9D9F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLSTOP

Flash Operation Control Register
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLSTOP : Selecting ON/OFF of the Flash Memory Operation
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Code flash and data flash memory operates

#1 : 1

Code flash and data flash memory stops.

End of enumeration elements list.

FLSTPF : Flash Memory Operation Status Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition (from the flash-stop-status to flash-operating-status or vice versa)

End of enumeration elements list.

VBTBKR[431]

VBATT Backup Register [%s]
address_offset : 0x9E0A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[432]

VBATT Backup Register [%s]
address_offset : 0x9E758 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[433]

VBATT Backup Register [%s]
address_offset : 0x9EE09 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMCR

Power Save Memory Control Register
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMC : Power save memory control.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

All RAM is on Software Standby mode.

#01 : 01

48KB RAM is on in Software Standby mode.

End of enumeration elements list.

VBTBKR[434]

VBATT Backup Register [%s]
address_offset : 0x9F4BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[435]

VBATT Backup Register [%s]
address_offset : 0x9FB6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCCR

Operating Power Control Register
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCM : Operating Power Control Mode Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

High-speed mode

#01 : 01

Prohibited

#10 : 10

Prohibited

#11 : 11

Low-speed mode

End of enumeration elements list.

OPCMTSF : Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition

End of enumeration elements list.

VBTBKR[0]

VBATT Backup Register [%s]
address_offset : 0xA00 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[436]

VBATT Backup Register [%s]
address_offset : 0xA0222 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[437]

VBATT Backup Register [%s]
address_offset : 0xA08D7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[438]

VBATT Backup Register [%s]
address_offset : 0xA0F8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[439]

VBATT Backup Register [%s]
address_offset : 0xA1644 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[440]

VBATT Backup Register [%s]
address_offset : 0xA1CFC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[30]

VBATT Backup Register [%s]
address_offset : 0xA1D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSCWTCR

Main Clock Oscillator Wait Control Register
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTS : Main clock oscillator wait time setting
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0001 : 0001

Wait time = 35 cycles (133.5 us)

#0010 : 0010

Wait time = 67 cycles (255.6 us)

#0011 : 0011

Wait time = 131 cycles (499.7 us)

#0100 : 0100

Wait time = 259 cycles (988.0 us)

#0101 : 0101

Wait time = 547 cycles (2086.6 us) (value after reset)

#0110 : 0110

Wait time = 1059 cycles (4039.8 us)

#0111 : 0111

Wait time = 2147 cycles (8190.2 us)

#1000 : 1000

Wait time = 4291 cycles (16368.9 us)

#1001 : 1001

Wait time = 8163 cycles (31139.4 us).

End of enumeration elements list.

VBTBKR[441]

VBATT Backup Register [%s]
address_offset : 0xA23B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[442]

VBATT Backup Register [%s]
address_offset : 0xA2A6F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[443]

VBATT Backup Register [%s]
address_offset : 0xA312A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[444]

VBATT Backup Register [%s]
address_offset : 0xA37E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[445]

VBATT Backup Register [%s]
address_offset : 0xA3EA3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[446]

VBATT Backup Register [%s]
address_offset : 0xA4561 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[447]

VBATT Backup Register [%s]
address_offset : 0xA4C20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOWTCR

High-speed on-chip oscillator wait control register
address_offset : 0xA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTS : HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)
bits : 0 - 1 (2 bit)
access : read-write

VBTBKR[448]

VBATT Backup Register [%s]
address_offset : 0xA52E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[449]

VBATT Backup Register [%s]
address_offset : 0xA59A1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[450]

VBATT Backup Register [%s]
address_offset : 0xA6063 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[451]

VBATT Backup Register [%s]
address_offset : 0xA6726 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[452]

VBATT Backup Register [%s]
address_offset : 0xA6DEA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[31]

VBATT Backup Register [%s]
address_offset : 0xA6F0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[453]

VBATT Backup Register [%s]
address_offset : 0xA74AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[454]

VBATT Backup Register [%s]
address_offset : 0xA7B75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[455]

VBATT Backup Register [%s]
address_offset : 0xA823C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[456]

VBATT Backup Register [%s]
address_offset : 0xA8904 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[457]

VBATT Backup Register [%s]
address_offset : 0xA8FCD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[458]

VBATT Backup Register [%s]
address_offset : 0xA9697 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[459]

VBATT Backup Register [%s]
address_offset : 0xA9D62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOPCCR

Sub Operating Power Control Register
address_offset : 0xAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOPCM : Sub Operating Power Control Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Other than Subosc-speed mode

#1 : 1

Subosc-speed mode

End of enumeration elements list.

SOPCMTSF : Sub Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition

End of enumeration elements list.

VBTBKR[460]

VBATT Backup Register [%s]
address_offset : 0xAA42E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[461]

VBATT Backup Register [%s]
address_offset : 0xAAAFB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[462]

VBATT Backup Register [%s]
address_offset : 0xAB1C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[463]

VBATT Backup Register [%s]
address_offset : 0xAB898 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[464]

VBATT Backup Register [%s]
address_offset : 0xABF68 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[32]

VBATT Backup Register [%s]
address_offset : 0xAC10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[465]

VBATT Backup Register [%s]
address_offset : 0xAC639 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[466]

VBATT Backup Register [%s]
address_offset : 0xACD0B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[467]

VBATT Backup Register [%s]
address_offset : 0xAD3DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[468]

VBATT Backup Register [%s]
address_offset : 0xADAB2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[469]

VBATT Backup Register [%s]
address_offset : 0xAE187 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[470]

VBATT Backup Register [%s]
address_offset : 0xAE85D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[471]

VBATT Backup Register [%s]
address_offset : 0xAEF34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[472]

VBATT Backup Register [%s]
address_offset : 0xAF60C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[473]

VBATT Backup Register [%s]
address_offset : 0xAFCE5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[474]

VBATT Backup Register [%s]
address_offset : 0xB03BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[475]

VBATT Backup Register [%s]
address_offset : 0xB0A9A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[476]

VBATT Backup Register [%s]
address_offset : 0xB1176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[33]

VBATT Backup Register [%s]
address_offset : 0xB131 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[477]

VBATT Backup Register [%s]
address_offset : 0xB1853 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[478]

VBATT Backup Register [%s]
address_offset : 0xB1F31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[479]

VBATT Backup Register [%s]
address_offset : 0xB2610 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[480]

VBATT Backup Register [%s]
address_offset : 0xB2CF0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[481]

VBATT Backup Register [%s]
address_offset : 0xB33D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[482]

VBATT Backup Register [%s]
address_offset : 0xB3AB3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[483]

VBATT Backup Register [%s]
address_offset : 0xB4196 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[484]

VBATT Backup Register [%s]
address_offset : 0xB487A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[485]

VBATT Backup Register [%s]
address_offset : 0xB4F5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[486]

VBATT Backup Register [%s]
address_offset : 0xB5645 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[487]

VBATT Backup Register [%s]
address_offset : 0xB5D2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[488]

VBATT Backup Register [%s]
address_offset : 0xB6414 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[34]

VBATT Backup Register [%s]
address_offset : 0xB653 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[489]

VBATT Backup Register [%s]
address_offset : 0xB6AFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[490]

VBATT Backup Register [%s]
address_offset : 0xB71E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[491]

VBATT Backup Register [%s]
address_offset : 0xB78D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[492]

VBATT Backup Register [%s]
address_offset : 0xB7FBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[493]

VBATT Backup Register [%s]
address_offset : 0xB86AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[494]

VBATT Backup Register [%s]
address_offset : 0xB8D99 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[495]

VBATT Backup Register [%s]
address_offset : 0xB9488 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[496]

VBATT Backup Register [%s]
address_offset : 0xB9B78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[497]

VBATT Backup Register [%s]
address_offset : 0xBA269 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[498]

VBATT Backup Register [%s]
address_offset : 0xBA95B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[499]

VBATT Backup Register [%s]
address_offset : 0xBB04E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[500]

VBATT Backup Register [%s]
address_offset : 0xBB742 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[35]

VBATT Backup Register [%s]
address_offset : 0xBB76 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[501]

VBATT Backup Register [%s]
address_offset : 0xBBE37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[502]

VBATT Backup Register [%s]
address_offset : 0xBC52D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[503]

VBATT Backup Register [%s]
address_offset : 0xBCC24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[504]

VBATT Backup Register [%s]
address_offset : 0xBD31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[505]

VBATT Backup Register [%s]
address_offset : 0xBDA15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[506]

VBATT Backup Register [%s]
address_offset : 0xBE10F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[507]

VBATT Backup Register [%s]
address_offset : 0xBE80A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[508]

VBATT Backup Register [%s]
address_offset : 0xBEF06 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[509]

VBATT Backup Register [%s]
address_offset : 0xBF603 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[510]

VBATT Backup Register [%s]
address_offset : 0xBFD01 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBYCR

Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPE : Output Port Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state.

#1 : 1

In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state..

End of enumeration elements list.

SSBY : Software Standby
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Sleep mode

#1 : 1

Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1)

End of enumeration elements list.

RSTSR1

Reset Status Register 1
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDTRF : Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Independent watchdog timer reset not detected.

#1 : 1

Independent watchdog timer reset detected.

End of enumeration elements list.

WDTRF : Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset not detected.

#1 : 1

Watchdog timer reset detected.

End of enumeration elements list.

SWRF : Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software reset not detected.

#1 : 1

Software reset detected.

End of enumeration elements list.

RPERF : RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

RAM parity error reset not detected.

#1 : 1

RAM parity error reset detected.

End of enumeration elements list.

REERF : RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

RAM ECC error reset not detected.

#1 : 1

RAM ECC error reset detected.

End of enumeration elements list.

BUSSRF : Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Slave MPU reset not detected.

#1 : 1

Bus Slave MPU reset detected.

End of enumeration elements list.

BUSMRF : Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus Master MPU reset not detected.

#1 : 1

Bus Master MPU reset detected.

End of enumeration elements list.

SPERF : SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

SP error reset not detected.

#1 : 1

SP error reset detected.

End of enumeration elements list.

VBTBKR[511]

VBATT Backup Register [%s]
address_offset : 0xC0400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIER1

Deep Standby Interrupt Enable Register %s
address_offset : 0xC07 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ7E : IRQ-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Canceling deep software standby mode is disabled

#1 : 1

Canceling deep software standby mode is enabled

End of enumeration elements list.

VBTBKR[36]

VBATT Backup Register [%s]
address_offset : 0xC09A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPSIFR1

Deep Standby Interrupt Flag Register %s
address_offset : 0xC13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ7F : IRQ-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The cancel request is not generated

#1 : 1

The cancel request is generated

End of enumeration elements list.

DPSIEGR1

Deep Standby Interrupt Edge Register %s
address_offset : 0xC1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRQ7EG : IRQ-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

A cancel request is generated at a falling edge

#1 : 1

A cancel request is generated at a rising edge

End of enumeration elements list.

LVD2CR0

Voltage Monitor %s Circuit Control Register 0
address_offset : 0xC4F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIE : Voltage Monitor Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

DFDIS : Voltage Monitor Digital Filter Disable Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable digital filter

#1 : 1

Disable digital filter

End of enumeration elements list.

CMPE : Voltage Monitor Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable voltage monitor 1 circuit comparison result output

#1 : 1

Enable voltage monitor 1 circuit comparison result output.

End of enumeration elements list.

FSAMP : Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

1/2 LOCO frequency

#01 : 01

1/4 LOCO frequency

#10 : 10

1/8 LOCO frequency

#11 : 11

1/16 LOCO frequency

End of enumeration elements list.

RI : Voltage Monitor Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Monitor interrupt during Vdet1 passage

#1 : 1

Voltage Monitor reset enabled when the voltage falls to and below Vdet1

End of enumeration elements list.

RN : Voltage Monitor Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negation follows a stabilization time (tLVD) after VCC > Vdet is detected.

#1 : 1

Negation follows a stabilization time (tLVD) after assertion of the LVD reset.

End of enumeration elements list.

VBTBKR[37]

VBATT Backup Register [%s]
address_offset : 0xC5BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[38]

VBATT Backup Register [%s]
address_offset : 0xCAE5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[39]

VBATT Backup Register [%s]
address_offset : 0xD00C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDADCCKCR

24-bit Sigma-Delta A/D Converter Clock Control Register
address_offset : 0xD1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDADCCKSEL : 24-bit Sigma-Delta A/D Converter Clock Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

MOSC is chosen by a source clock of 24-bit Sigma-Delta A/D Converter Clock.

#1 : 1

HOCO is chosen by a source clock of 24-bit Sigma-Delta AA/D Converter Clock.

End of enumeration elements list.

SDADCCKEN : 24-bit Sigma-Delta A/D Converter Clock Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

24-bit Sigma-Delta A/D Converter Clock is disabled

#1 : 1

24-bit Sigma-Delta A/D Converter Clock is enabled.

End of enumeration elements list.

VBTBKR[40]

VBATT Backup Register [%s]
address_offset : 0xD534 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[41]

VBATT Backup Register [%s]
address_offset : 0xDA5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[42]

VBATT Backup Register [%s]
address_offset : 0xDF87 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[43]

VBATT Backup Register [%s]
address_offset : 0xE4B2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[44]

VBATT Backup Register [%s]
address_offset : 0xE9DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[45]

VBATT Backup Register [%s]
address_offset : 0xEF0B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[1]

VBATT Backup Register [%s]
address_offset : 0xF01 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[46]

VBATT Backup Register [%s]
address_offset : 0xF439 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[47]

VBATT Backup Register [%s]
address_offset : 0xF968 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VBTBKR[48]

VBATT Backup Register [%s]
address_offset : 0xFE98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

R_SYSTEM

Peripheral Memory Blocks

Registers

VBTBKR[49]

VBTBKR[50]

VBTBKR[51]

VBTBKR[52]

VBTBKR[53]

VBTBKR[54]

VBTBKR[55]

VBTBKR[56]

VBTBKR[57]

VBTBKR[58]

VBTBKR[59]

VBTBKR[60]

VBTBKR[2]

VBTBKR[61]

VBTBKR[62]

VBTBKR[63]

VBTBKR[64]

VBTBKR[65]

VBTBKR[66]

VBTBKR[67]

VBTBKR[68]

VBTBKR[69]

VBTBKR[70]

VBTBKR[71]

VBTBKR[72]

VBTBKR[73]

VBTBKR[74]

VBTBKR[75]

VBTBKR[3]

VBTBKR[76]

VBTBKR[77]

VBTBKR[78]

VBTBKR[79]

VBTBKR[80]

VBTBKR[81]

VBTBKR[82]

VBTBKR[83]

VBTBKR[84]

MSTPCRA

LVD1CR1

VBTBKR[85]

LVD1SR

VBTBKR[86]

VBTBKR[87]

VBTBKR[88]

VBTBKR[89]

VBTBKR[90]

VBTBKR[4]

VBTBKR[91]

VBTBKR[92]

VBTBKR[93]

VBTBKR[94]

VBTBKR[95]

VBTBKR[96]

SCKDIVCR

VBTBKR[97]

VBTBKR[98]

VBTBKR[99]

VBTBKR[100]

VBTBKR[101]

VBTBKR[102]

VBTBKR[103]

VBTBKR[104]

VBTBKR[105]

VBTBKR[5]

VBTBKR[106]

VBTBKR[107]

VBTBKR[108]

SCKDIVCR2

VBTBKR[109]

VBTBKR[110]

VBTBKR[111]

VBTBKR[112]

VBTBKR[113]

VBTBKR[114]

SCKSCR