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R_USB_FS0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x68 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x64 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xF0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xD0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x144 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x46 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x54 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x6C Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xCC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x400 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x36 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x160 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSCFG

LPCTRL

LPSTS

PIPE_TR[1]-PIPE_TR[0]-E

PIPE_TR[1]-PIPE_TR[0]-N

CFIFOL

CFIFOLL

CFIFO

BCCTRL

PL1CTRL1

PL1CTRL2

HL1CTRL1

HL1CTRL2

PIPE_CTR[1]

CFIFOH

DPUSR0R

DPUSR1R

DPUSR2R

DPUSRCR

CFIFOHH

D0FIFOL

D0FIFOLL

D0FIFO

D0FIFOH

DEVADD[0]

D0FIFOHH

PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E

PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N

D1FIFOL

D1FIFOLL

D1FIFO

PIPE_CTR[2]

D1FIFOH

D1FIFOHH

BUSWAIT

CFIFOSEL

CFIFOCTR

PIPE_CTR[3]

PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E

PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N

DEVADD[1]

D0FIFOSEL

D0FIFOCTR

PIPE_CTR[4]

D1FIFOSEL

D1FIFOCTR

PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E

PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N

INTENB0

INTENB1

PIPE_CTR[5]

DEVADD[2]

BRDYENB

NRDYENB

BEMPENB

PIPE_CTR[6]

SOFCFG

PHYSET

SYSSTS0

INTSTS0

DPUSR0R_FS

DPUSR1R_FS

DEVADD[3]

INTSTS1

PIPE_CTR[7]

BRDYSTS

NRDYSTS

BEMPSTS

PIPE_CTR[8]

FRMNUM

UFRMNUM

DEVADD[4]

USBADDR

USBREQ

USBVAL

USBINDX

USBLENG

DCPCFG

DEVADD[5]

DCPMAXP

PLLSTA

DCPCTR

PIPESEL

PIPECFG

DEVADD[6]

PIPEMAXP

PIPEPERI

DEVADD[7]

DVSTCTR0

DEVADD[8]

PIPE_TR[0]-E

PIPE_TR[0]-N

DEVADD[9]

USBBCCTRL0

TESTMODE

UCKSEL

USBMC

PIPE_CTR[0]

PHYSLEW


SYSCFG

System Configuration Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG SYSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBE DMRPU DPRPU DRPD DCFM CNEN SCKE

USBE : USB Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled.

End of enumeration elements list.

DMRPU : D- Line Resistor Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Line pull-up disabled

#1 : 1

Line pull-up enabled.

End of enumeration elements list.

DPRPU : D+ Line Resistor Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Line pull-down disabled

#1 : 1

Line pull-down enabled.

End of enumeration elements list.

DRPD : D+/D- Line Resistor Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Line pull-down disabled

#1 : 1

Line pull-down enabled.

End of enumeration elements list.

DCFM : Controller Function Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Device controller selected

#1 : 1

Host controller selected.

End of enumeration elements list.

CNEN : CNEN Single End Receiver Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Single end receiver disabled

#1 : 1

Single end receiver enabled

End of enumeration elements list.

SCKE : USB Clock Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Clock supply to the USBFS stopped

#1 : 1

Clock supply to the USBFS enabled.

End of enumeration elements list.


LPCTRL

Low Power Control Register
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPCTRL LPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HWUPM

HWUPM : Resume Return Mode Setting
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Hardware does not recover while CPU clock inactive

#1 : 1

Hardware recovers while CPU clock inactive.

End of enumeration elements list.


LPSTS

Low Power Status Register
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPSTS LPSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPENDM

SUSPENDM : UTMI SuspendM Control
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

UTMI suspension mode

#1 : 1

UTMI normal mode

End of enumeration elements list.


PIPE_TR[1]-PIPE_TR[0]-E

Pipe Transaction Counter Enable Register
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[1]-PIPE_TR[0]-E PIPE_TR[1]-PIPE_TR[0]-E read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

The current counter value is cleared.

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transaction counter is disabled.

#1 : 1

Transaction counter is enabled.

End of enumeration elements list.


PIPE_TR[1]-PIPE_TR[0]-N

Pipe Transaction Counter Register
address_offset : 0x126 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[1]-PIPE_TR[0]-N PIPE_TR[1]-PIPE_TR[0]-N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNCNT

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write


CFIFOL

CFIFO Port Register L
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFIFOL CFIFOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFIFOLL

CFIFO Port Register LL
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFOL
reset_Mask : 0x0

CFIFOLL CFIFOLL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CFIFO

CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFOL
reset_Mask : 0x0

CFIFO CFIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BCCTRL

Battery Charging Control Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCCTRL BCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDPSRCE IDMSINKE VDPSRCE IDPSINKE VDMSRCE DCPMODE CHGDETSTS PDDETSTS

IDPSRCE : IDPSRC Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The IDP_SRC circuit is disabled. (Initial value)

#1 : 1

The IDP_SRC circuit is enabled.

End of enumeration elements list.

IDMSINKE : IDMSINK Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The IDM_SINK circuit is disabled. (Initial value)

#1 : 1

The IDM_SINK circuit is enabled.

End of enumeration elements list.

VDPSRCE : VDPSRC Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The VDP_SRC circuit is disabled. (Initial value)

#1 : 1

The VDP_SRC circuit is enabled.

End of enumeration elements list.

IDPSINKE : IDPSINK Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

The IDP_SINK circuit is disabled. (Initial value)

#1 : 1

The IDP_SINK circuit is enabled.

End of enumeration elements list.

VDMSRCE : VDMSRC Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The VDM_SRC circuit is disabled. (Initial value)

#1 : 1

The VDM_SRC circuit is enabled.

End of enumeration elements list.

DCPMODE : DCP Mode Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

The RDCP_DAT resistor is disabled

#1 : 1

The RDCP_DAT resistor is enabled.

End of enumeration elements list.

CHGDETSTS : CHGDET Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

The CHGDET pin is at low level.

#1 : 1

The CHGDET pin is at high level.

End of enumeration elements list.

PDDETSTS : PDDET Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

The PDDET pin is at low level.

#1 : 1

The PDDET pin is at high level.

End of enumeration elements list.


PL1CTRL1

Function L1 Control Register 1
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PL1CTRL1 PL1CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L1RESPEN L1RESPMD L1NEGOMD DVSQ HIRDTHR L1EXTMD

L1RESPEN : L1 Response Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

LPM is not supported.

#1 : 1

LPM is supported.

End of enumeration elements list.

L1RESPMD : L1 Response Mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#00 : 00

NYET

#01 : 01

ACK

#10 : 10

STALL

#11 : 11

According to the L1NEGOMD bit

End of enumeration elements list.

L1NEGOMD : L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11.
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned.

#1 : 1

When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned.

End of enumeration elements list.

DVSQ : DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0].
bits : 4 - 6 (3 bit)
access : read-only

Enumeration:

#0000 : 0000

Powered state

#0001 : 0001

Default state

#0010 : 0010

Address state

#0011 : 0011

Configured state

#0100 : 0100

Suspended state

#0101 : 0101

Suspended state

#0110 : 0110

Suspended state

#0111 : 0111

Suspended state

#1000 : 1000

L1 state

#1001 : 1001

L1 state

#1010 : 1010

L1 state

#1011 : 1011

L1 state

End of enumeration elements list.

HIRDTHR : L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL.
bits : 8 - 10 (3 bit)
access : read-write

L1EXTMD : PHY Control Mode at L1 Return
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

SUSPENDM is not set by hardware when Host K is received.

#1 : 1

SUSPENDM is set by hardware when Host K is received.

End of enumeration elements list.


PL1CTRL2

Function L1 Control Register 2
address_offset : 0x146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PL1CTRL2 PL1CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRDMON RWEMON

HIRDMON : HIRD Value Monitor
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0 : 0

The HIRD field value of the LPM token received last is reflected.

#1 : 1

The HIRD field value of the LPM token received last is reflected.

End of enumeration elements list.

RWEMON : RWE Value Monitor
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

The RWE bit value of the LPM token received last is reflected.

#1 : 1

The RWE bit value of the LPM token received last is reflected.

End of enumeration elements list.


HL1CTRL1

Host L1 Control Register 1
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HL1CTRL1 HL1CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L1REQ L1STATUS

L1REQ : L1 Transition Request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

This bit is cleared to 0 by hardware when the LPM transaction is completed.

#1 : 1

Set this bit to 1 when requesting a transition to the L1 state.

End of enumeration elements list.

L1STATUS : L1 Request Completion Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#00 : 00

ACK received

#01 : 01

NYET received

#10 : 10

STALL received

#11 : 11

Transaction error

End of enumeration elements list.


HL1CTRL2

Host L1 Control Register 2
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HL1CTRL2 HL1CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L1ADDR HIRD L1RWE BESL

L1ADDR : LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token.
bits : 0 - 2 (3 bit)
access : read-write

HIRD : LPM Token HIRD
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1)

#0001 : 0001

125 us(BESL = 0) / 100 us(BESL = 1)

#0010 : 0010

200 us(BESL = 0) / 150 us(BESL = 1)

#0011 : 0011

275 us(BESL = 0) / 250 us(BESL = 1)

#0100 : 0100

350 us(BESL = 0) / 350 us(BESL = 1)

#0101 : 0101

425 us(BESL = 0) / 450 us(BESL = 1)

#0110 : 0110

500 us(BESL = 0) / 950 us(BESL = 1)

#0111 : 0111

575 us(BESL = 0) / 1950 us(BESL = 1)

#1000 : 1000

650 us(BESL = 0) / 2950 us(BESL = 1)

#1001 : 1001

725 us(BESL = 0) / 3950 us(BESL = 1)

#1010 : 1010

800 us(BESL = 0) / 4950 us(BESL = 1)

#1011 : 1011

875 us(BESL = 0) / 5950 us(BESL = 1)

#1100 : 1100

950 us(BESL = 0) / 6950 us(BESL = 1)

#1101 : 1101

1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1)

#1110 : 1110

1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1)

#1111 : 1111

1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1)

End of enumeration elements list.

L1RWE : LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token.
bits : 12 - 11 (0 bit)
access : read-write

BESL : BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume.
bits : 15 - 14 (0 bit)
access : read-write


PIPE_CTR[1]

Pipe %s Control Register
address_offset : 0x152 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[1] PIPE_CTR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


CFIFOH

CFIFO Port Register H
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0

CFIFOH CFIFOH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPUSR0R

Deep Standby USB Transceiver Control/Pin Monitor Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DPUSR0R DPUSR0R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOVCAHM DOVCBHM DVBSTSHM

DOVCAHM : OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port.
bits : 20 - 19 (0 bit)
access : read-only

DOVCBHM : OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port.
bits : 21 - 20 (0 bit)
access : read-only

DVBSTSHM : VBUS InputIndicates VBUS input signal on the HS side of USB port.
bits : 23 - 22 (0 bit)
access : read-only


DPUSR1R

Deep Standby USB Suspend/Resume Interrupt Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPUSR1R DPUSR1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOVCAHE DOVCBHE DVBSTSHE DOVCAH DOVCBH DVBSTSH

DOVCAHE : OVRCURA Interrupt Enable Clear
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables return from deep software standby mode

#1 : 1

Enables return from deep software standby mode

End of enumeration elements list.

DOVCBHE : OVRCURB Interrupt Enable Clear
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables return from deep software standby mode

#1 : 1

Enables return from deep software standby mode

End of enumeration elements list.

DVBSTSHE : VBUS Interrupt Enable/Clear
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables return from deep software standby mode

#1 : 1

Enables return from deep software standby mode

End of enumeration elements list.

DOVCAH : Indication of Return from OVRCURA Interrupt Source
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : 0

Indicates deep software standby mode

#1 : 1

Indicates return from deep software standby mode

End of enumeration elements list.

DOVCBH : Indication of Return from OVRCURB Interrupt Source
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

#0 : 0

Indicates deep software standby mode

#1 : 1

Indicates return from deep software standby mode

End of enumeration elements list.

DVBSTSH : Indication of Return from VBUS Interrupt Source
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

#0 : 0

Indicates deep software standby mode

#1 : 1

Indicates return from deep software standby mode

End of enumeration elements list.


DPUSR2R

Deep Standby USB Suspend/Resume Interrupt Register
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPUSR2R DPUSR2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPINT DMINT DPVAL DMVAL DPINTE DMINTE

DPINT : Indication of Return from DP Interrupt Source
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Indicates deep software standby mode

#1 : 1

Indicates return from deep software standby mode

End of enumeration elements list.

DMINT : Indication of Return from DM Interrupt Source
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Indicates deep software standby mode

#1 : 1

Indicates return from deep software standby mode

End of enumeration elements list.

DPVAL : DP InputIndicates DP input signal on the HS side of USB port.
bits : 4 - 3 (0 bit)
access : read-only

DMVAL : DM InputIndicates DM input signal on the HS side of USB port.
bits : 5 - 4 (0 bit)
access : read-only

DPINTE : DP Interrupt Enable Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables return from deep software standby mode

#1 : 1

Enables return from deep software standby mode

End of enumeration elements list.

DMINTE : DM Interrupt Enable Clear
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables return from deep software standby mode

#1 : 1

Enables return from deep software standby mode

End of enumeration elements list.


DPUSRCR

Deep Standby USB Suspend/Resume Command Register
address_offset : 0x16A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPUSRCR DPUSRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIXPHY FIXPHYPD

FIXPHY : USB Transceiver Control Fix
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Go to/Return from deep software standby mode

End of enumeration elements list.

FIXPHYPD : USB Transceiver Control Fix for PLL
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Go to/Return from deep software standby mode

End of enumeration elements list.


CFIFOHH

CFIFO Port Register HH
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFOH
reset_Mask : 0x0

CFIFOHH CFIFOHH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

D0FIFOL

D0FIFO Port Register L
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D0FIFOL D0FIFOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D0FIFOLL

D0FIFO Port Register LL
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFOL
reset_Mask : 0x0

D0FIFOLL D0FIFOLL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

D0FIFO

D0FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFOL
reset_Mask : 0x0

D0FIFO D0FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D0FIFOH

D0FIFO Port Register H
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

D0FIFOH D0FIFOH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVADD[0]

Device Address Configuration Register
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[0] DEVADD[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


D0FIFOHH

D0FIFO Port Register HH
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFOH
reset_Mask : 0x0

D0FIFOHH D0FIFOHH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E

Pipe Transaction Counter Enable Register
address_offset : 0x1BC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

The current counter value is cleared.

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transaction counter is disabled.

#1 : 1

Transaction counter is enabled.

End of enumeration elements list.


PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N

Pipe Transaction Counter Register
address_offset : 0x1BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNCNT

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write


D1FIFOL

D1FIFO Port Register L
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1FIFOL D1FIFOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D1FIFOLL

D1FIFO Port Register LL
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFOL
reset_Mask : 0x0

D1FIFOLL D1FIFOLL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

D1FIFO

D1FIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFOL
reset_Mask : 0x0

D1FIFO D1FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_CTR[2]

Pipe %s Control Register
address_offset : 0x1C6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[2] PIPE_CTR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


D1FIFOH

D1FIFO Port Register H
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFO
reset_Mask : 0x0

D1FIFOH D1FIFOH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D1FIFOHH

D1FIFO Port Register HH
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFOH
reset_Mask : 0x0

D1FIFOHH D1FIFOHH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BUSWAIT

CPU Bus Wait Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSWAIT BUSWAIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BWAIT

BWAIT : CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CFIFOSEL

CFIFO Port Select Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFIFOSEL CFIFOSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURPIPE ISEL BIGEND MBW REW RCNT

CURPIPE : CFIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

DCP (Default control pipe)

#0001 : 0001

Pipe 1

#0010 : 0010

Pipe 2

#0011 : 0011

Pipe 3

#0100 : 0100

Pipe 4

#0101 : 0101

Pipe 5

#0110 : 0110

Pipe 6

#0111 : 0111

Pipe 7

#1000 : 1000

Pipe 8

#1001 : 1001

Pipe 9

End of enumeration elements list.

ISEL : CFIFO Port Access Direction When DCP is Selected
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reading from the buffer memory is selected

#1 : 1

Writing to the buffer memory is selected

End of enumeration elements list.

BIGEND : CFIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

MBW : CFIFO Port Access Bit Width
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : 0

8-bit width

1 : 1

16-bit width

2 : 2

32-bit width

End of enumeration elements list.

REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

The buffer pointer is not rewound.

#1 : 1

The buffer pointer is rewound.

End of enumeration elements list.

RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.)

#1 : 1

The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.

End of enumeration elements list.


CFIFOCTR

CFIFO Port Control Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFIFOCTR CFIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTLN FRDY BCLR BVAL

DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 10 (11 bit)
access : read-only

FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

FIFO port access is disabled.

#1 : 1

FIFO port access is enabled.

End of enumeration elements list.

BCLR : CPU Buffer ClearNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not operate

#1 : 1

FIFO buffer cleared on the CPU side.

End of enumeration elements list.

BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Writing ended

End of enumeration elements list.


PIPE_CTR[3]

Pipe %s Control Register
address_offset : 0x23C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[3] PIPE_CTR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E

Pipe Transaction Counter Enable Register
address_offset : 0x258 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

The current counter value is cleared.

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transaction counter is disabled.

#1 : 1

Transaction counter is enabled.

End of enumeration elements list.


PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N

Pipe Transaction Counter Register
address_offset : 0x25A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNCNT

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write


DEVADD[1]

Device Address Configuration Register
address_offset : 0x272 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[1] DEVADD[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


D0FIFOSEL

D0FIFO Port Select Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D0FIFOSEL D0FIFOSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURPIPE BIGEND MBW DREQE DCLRM REW RCNT

CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

DCP (Default control pipe)

#0001 : 0001

Pipe 1

#0010 : 0010

Pipe 2

#0011 : 0011

Pipe 3

#0100 : 0100

Pipe 4

#0101 : 0101

Pipe 5

#0110 : 0110

Pipe 6

#0111 : 0111

Pipe 7

#1000 : 1000

Pipe 8

#1001 : 1001

Pipe 9

End of enumeration elements list.

BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

MBW : FIFO Port Access Bit Width
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : 0

8-bit width

1 : 1

16-bit width

2 : 2

32-bit width

End of enumeration elements list.

DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMA/DTC transfer request is disabled.

#1 : 1

DMA/DTC transfer request is enabled.

End of enumeration elements list.

DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto buffer clear mode is disabled.

#1 : 1

Auto buffer clear mode is enabled.

End of enumeration elements list.

REW : Buffer Pointer RewindNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

The buffer pointer is not rewound.

#1 : 1

The buffer pointer is rewound.

End of enumeration elements list.

RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)

#1 : 1

The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)

End of enumeration elements list.


D0FIFOCTR

D0FIFO Port Control Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D0FIFOCTR D0FIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTLN FRDY BCLR BVAL

DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 10 (11 bit)
access : read-only

FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

FIFO port access is disabled.

#1 : 1

FIFO port access is enabled.

End of enumeration elements list.

BCLR : CPU Buffer ClearNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not operate

#1 : 1

FIFO buffer cleared on the CPU side.

End of enumeration elements list.

BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Writing ended

End of enumeration elements list.


PIPE_CTR[4]

Pipe %s Control Register
address_offset : 0x2B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[4] PIPE_CTR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


D1FIFOSEL

D1FIFO Port Select Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1FIFOSEL D1FIFOSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURPIPE BIGEND MBW DREQE DCLRM REW RCNT

CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

DCP (Default control pipe)

#0001 : 0001

Pipe 1

#0010 : 0010

Pipe 2

#0011 : 0011

Pipe 3

#0100 : 0100

Pipe 4

#0101 : 0101

Pipe 5

#0110 : 0110

Pipe 6

#0111 : 0111

Pipe 7

#1000 : 1000

Pipe 8

#1001 : 1001

Pipe 9

End of enumeration elements list.

BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

MBW : FIFO Port Access Bit Width
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : 0

8-bit width

1 : 1

16-bit width

2 : 2

32-bit width

End of enumeration elements list.

DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMA/DTC transfer request is disabled.

#1 : 1

DMA/DTC transfer request is enabled.

End of enumeration elements list.

DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto buffer clear mode is disabled.

#1 : 1

Auto buffer clear mode is enabled.

End of enumeration elements list.

REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

The buffer pointer is not rewound.

#1 : 1

The buffer pointer is rewound.

End of enumeration elements list.

RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)

#1 : 1

The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)

End of enumeration elements list.


D1FIFOCTR

D1FIFO Port Control Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1FIFOCTR D1FIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTLN FRDY BCLR BVAL

DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 10 (11 bit)
access : read-only

FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

FIFO port access is disabled.

#1 : 1

FIFO port access is enabled.

End of enumeration elements list.

BCLR : CPU Buffer ClearNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not operate

#1 : 1

FIFO buffer cleared on the CPU side.

End of enumeration elements list.

BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Writing ended

End of enumeration elements list.


PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E

Pipe Transaction Counter Enable Register
address_offset : 0x2F8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-E read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

The current counter value is cleared.

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transaction counter is disabled.

#1 : 1

Transaction counter is enabled.

End of enumeration elements list.


PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N

Pipe Transaction Counter Register
address_offset : 0x2FA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N PIPE_TR[4]-PIPE_TR[3]-PIPE_TR[2]-PIPE_TR[1]-PIPE_TR[0]-N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNCNT

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write


INTENB0

Interrupt Enable Register 0
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENB0 INTENB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRDYE NRDYE BEMPE CTRE DVSE SOFE RSME VBSE

BRDYE : Buffer Ready Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

NRDYE : Buffer Not Ready Response Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

BEMPE : Buffer Empty Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

CTRE : Control Transfer Stage Transition Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

DVSE : Device State Transition Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

SOFE : Frame Number Update Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

RSME : Resume Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

VBSE : VBUS Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.


INTENB1

Interrupt Enable Register 1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENB1 INTENB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDDETINTE0 SACKE SIGNE EOFERRE ATTCHE DTCHE BCHGE OVRCRE

PDDETINTE0 : PDDETINT0 Detection Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

SACKE : Setup Transaction Normal Response Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

SIGNE : Setup Transaction Error Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

EOFERRE : EOF Error Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

ATTCHE : Connection Detection Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

DTCHE : Disconnection Detection Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

BCHGE : USB Bus Change Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

OVRCRE : Overcurrent Input Change Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.


PIPE_CTR[5]

Pipe %s Control Register
address_offset : 0x32E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[5] PIPE_CTR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


DEVADD[2]

Device Address Configuration Register
address_offset : 0x346 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[2] DEVADD[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


BRDYENB

BRDY Interrupt Enable Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRDYENB BRDYENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BRDYE PIPE1BRDYE PIPE2BRDYE PIPE3BRDYE PIPE4BRDYE PIPE5BRDYE PIPE6BRDYE PIPE7BRDYE PIPE8BRDYE PIPE9BRDYE

PIPE0BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE1BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE2BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE3BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE4BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE5BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE6BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE7BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE8BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE9BRDYE : BRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.


NRDYENB

NRDY Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NRDYENB NRDYENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0NRDYE PIPE1NRDYE PIPE2NRDYE PIPE3NRDYE PIPE4NRDYE PIPE5NRDYE PIPE6NRDYE PIPE7NRDYE PIPE8NRDYE PIPE9NRDYE

PIPE0NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE1NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE2NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE3NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE4NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE5NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE6NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE7NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE8NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE9NRDYE : NRDY Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.


BEMPENB

BEMP Interrupt Enable Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BEMPENB BEMPENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BEMPE PIPE1BEMPE PIPE2BEMPE PIPE3BEMPE PIPE4BEMPE PIPE5BEMPE PIPE6BEMPE PIPE7BEMPE PIPE8BEMPE PIPE9BEMPE

PIPE0BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE1BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE2BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE3BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE4BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE5BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE6BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE7BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE8BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.

PIPE9BEMPE : BEMP Interrupt Enable for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt output disabled

#1 : 1

Interrupt output enabled

End of enumeration elements list.


PIPE_CTR[6]

Pipe %s Control Register
address_offset : 0x3AA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[6] PIPE_CTR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


SOFCFG

SOF Output Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOFCFG SOFCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDGESTS INTL BRDYM TRNENSEL

EDGESTS : Edge Interrupt Output Status Monitor
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

before stopping the clock supply to the USB module

#1 : 1

the edge interrupt output signal is in the middle of the edge processing

End of enumeration elements list.

INTL : Interrupt Output Sense Select
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Edge sense

#1 : 1

Level sense

End of enumeration elements list.

BRDYM : BRDY Interrupt Status Clear Timing
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

BRDY flag cleared by software

#1 : 1

BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer.

End of enumeration elements list.

TRNENSEL : Transaction-Enabled Time Select
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not low-speed communication

#1 : 1

Low-speed communication.

End of enumeration elements list.


PHYSET

PHY Setting Register
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYSET PHYSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIRPD PLLRESET CDPEN CLKSEL REPSEL REPSTART HSEB

DIRPD : Power-Down Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Does not enter low-power consumption mode

#1 : 1

Enter low-power consumption mode

End of enumeration elements list.

PLLRESET : PLL Reset Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable PLL reset control for UTMI_PHY

#1 : 1

Enable PLL reset control for UTMI_PHY

End of enumeration elements list.

CDPEN : Charging Downstream Port Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable charging downstream port

#1 : 1

Enable charging downstream port

End of enumeration elements list.

CLKSEL : Input System Clock Frequency
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

Setting Prohibited

#01 : 01

12 MHz

#10 : 10

20 MHz

#11 : 11

24 MHz

End of enumeration elements list.

REPSEL : Terminating Resistance Adjustment Cycle
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : 00

No cycle is set.

#01 : 01

Adjust terminating resistance at 16-second intervals.

#10 : 10

Adjust terminating resistance at 64-second intervals.

#11 : 11

Adjust terminating resistance at 128-second intervals.

End of enumeration elements list.

REPSTART : Forcibly Start Terminating Resistance Adjustment
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Terminating resistance adjustment is forcibly started

#1 : 1

Terminating resistance adjustment is not forcibly started

End of enumeration elements list.

HSEB : CL-Only Mode
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

CL-only mode is not activated.

#1 : 1

CL-only mode is activated.

End of enumeration elements list.


SYSSTS0

System Configuration Status Register 0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSSTS0 SYSSTS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNST IDMON SOFEA HTACT OVCMON

LNST : USB Data Line Status Monitor
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#00 : 00

SE0

#01 : 01

K-State (FS) / J-State(LS)

#10 : 10

J-State(FS) / K-State(LS)

#11 : 11

SE1

End of enumeration elements list.

IDMON : External ID0 Input Pin Monitor
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

USB0_ID pin is low

#1 : 1

USB0_ID pin is high

End of enumeration elements list.

SOFEA : SOF Active Monitor While Host Controller Function is Selected.
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

SOF output is stopped.

#1 : 1

SOF output is operating.

End of enumeration elements list.

HTACT : USB Host Sequencer Status Monitor
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Host sequencer completely stopped

#1 : 1

Host sequencer not completely stopped.

End of enumeration elements list.

OVCMON : External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin.
bits : 14 - 14 (1 bit)
access : read-only


INTSTS0

Interrupt Status Register 0
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTS0 INTSTS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSQ VALID DVSQ VBSTS BRDY NRDY BEMP CTRT DVST SOFR RESM VBINT

CTSQ : Control Transfer Stage
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#000 : 000

Idle or setup stage

#001 : 001

Control read data stage

#010 : 010

Control read status stage

#011 : 011

Control write data stage

#100 : 100

Control write status stage

#101 : 101

Control write (no data) status stage

#110 : 110

Control transfer sequence error

End of enumeration elements list.

VALID : USB Request Reception
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Setup packet is not received

#1 : 1

Setup packet is received

End of enumeration elements list.

DVSQ : Device State
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

#000 : 000

Powered state

#001 : 001

Default state

#010 : 010

Address state

#011 : 011

Configured state

End of enumeration elements list.

VBSTS : VBUS Input Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

USB_VBUS pin is low.

#1 : 1

USB_VBUS pin is high.

End of enumeration elements list.

BRDY : Buffer Ready Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

BRDY interrupts are not generated.

#1 : 1

BRDY interrupts are generated.

End of enumeration elements list.

NRDY : Buffer Not Ready Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

NRDY interrupts are not generated.

#1 : 1

NRDY interrupts are generated.

End of enumeration elements list.

BEMP : Buffer Empty Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : 0

BEMP interrupts are not generated.

#1 : 1

BEMP interrupts are generated.

End of enumeration elements list.

CTRT : Control Transfer Stage Transition Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Control transfer stage transition interrupts are not generated.

#1 : 1

Control transfer stage transition interrupts are generated.

End of enumeration elements list.

DVST : Device State Transition Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Device state transition interrupts are not generated.

#1 : 1

Device state transition interrupts are generated.

End of enumeration elements list.

SOFR : Frame Number Refresh Interrupt Status
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

SOF interrupts are not generated.

#1 : 1

SOF interrupts are generated.

End of enumeration elements list.

RESM : Resume Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Resume interrupts are not generated.

#1 : 1

Resume interrupts are generated.

End of enumeration elements list.

VBINT : VBUS Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

VBUS interrupts are not generated.

#1 : 1

VBUS interrupts are generated.

End of enumeration elements list.


DPUSR0R_FS

Deep Software Standby USB Transceiver Control/Pin Monitor Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPUSR0R_FS DPUSR0R_FS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRPC0 RPUE0 DRPD0 FIXPHY0 DP0 DM0 DOVCA0 DOVCB0 DVBSTS0

SRPC0 : USB Single End Receiver Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Input through the DP and DM inputs is disabled.

#1 : 1

Input through the DP and DM inputs is enabled.

End of enumeration elements list.

RPUE0 : DP Pull-Up Resistor Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables DP pull-up resistor.

#1 : 1

Enables DP pull-up resistor.

End of enumeration elements list.

DRPD0 : D+/D- Pull-Down Resistor Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables DP/DM pull-down resistor.

#1 : 1

Enables DP/DM pull-down resistor.

End of enumeration elements list.

FIXPHY0 : USB Transceiver Output Fix
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The outputs are fixed in normal mode and on return from deep software standby mode.

#1 : 1

The outputs are fixed on transitions to deep software standby mode.

End of enumeration elements list.

DP0 : USB0 D+ InputIndicates the D+ input signal of the USB.
bits : 16 - 15 (0 bit)
access : read-only

DM0 : USB D-InputIndicates the D- input signal of the USB.
bits : 17 - 16 (0 bit)
access : read-only

DOVCA0 : USB OVRCURA InputIndicates the OVRCURA input signal of the USB.
bits : 20 - 19 (0 bit)
access : read-only

DOVCB0 : USB OVRCURB InputIndicates the OVRCURB input signal of the USB.
bits : 21 - 20 (0 bit)
access : read-only

DVBSTS0 : USB VBUS InputIndicates the VBUS input signal of the USB.
bits : 23 - 22 (0 bit)
access : read-only


DPUSR1R_FS

Deep Software Standby USB Suspend/Resume Interrupt Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPUSR1R_FS DPUSR1R_FS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPINTE0 DMINTE0 DOVRCRAE0 DOVRCRBE0 DVBSE0 DPINT0 DMINT0 DOVRCRA0 DOVRCRB0 DVBINT0

DPINTE0 : USB DP Interrupt Enable/Clear
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery from deep software standby mode is disabled.

#1 : 1

Recovery from deep software standby mode is enabled.

End of enumeration elements list.

DMINTE0 : USB DM Interrupt Enable/Clear
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery from deep software standby mode is disabled.

#1 : 1

Recovery from deep software standby mode is enabled.

End of enumeration elements list.

DOVRCRAE0 : USB OVRCURA Interrupt Enable/Clear
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery from deep software standby mode is disabled.

#1 : 1

Recovery from deep software standby mode is enabled.

End of enumeration elements list.

DOVRCRBE0 : USB OVRCURB Interrupt Enable/Clear
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery from deep software standby mode is disabled.

#1 : 1

Recovery from deep software standby mode is enabled.

End of enumeration elements list.

DVBSE0 : USB VBUS Interrupt Enable/Clear
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery from deep software standby mode is disabled.

#1 : 1

Recovery from deep software standby mode is enabled.

End of enumeration elements list.

DPINT0 : USB DP Interrupt Source Recovery
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

#0 : 0

The system has not returned from deep software standby mode.

#1 : 1

The system has returned from deep software standby mode.

End of enumeration elements list.

DMINT0 : USB DM Interrupt Source Recovery
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

#0 : 0

The system has not returned from deep software standby mode.

#1 : 1

The system has returned from deep software standby mode.

End of enumeration elements list.

DOVRCRA0 : USB OVRCURA Interrupt Source Recovery
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : 0

The system has not returned from deep software standby mode.

#1 : 1

The system has returned from deep software standby mode.

End of enumeration elements list.

DOVRCRB0 : USB OVRCURB Interrupt Source Recovery
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

#0 : 0

The system has not returned from deep software standby mode.

#1 : 1

The system has returned from deep software standby mode.

End of enumeration elements list.

DVBINT0 : USB VBUS Interrupt Source Recovery
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

#0 : 0

The system has not returned from deep software standby mode.

#1 : 1

The system has returned from deep software standby mode.

End of enumeration elements list.


DEVADD[3]

Device Address Configuration Register
address_offset : 0x41C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[3] DEVADD[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


INTSTS1

Interrupt Status Register 1
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTS1 INTSTS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDDETINT0 SACK SIGN EOFERR LPMEND L1RSMEND ATTCH DTCH BCHG OVRCR

PDDETINT0 : PDDET0 Detection Interrupt Status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

PDDET0 detection interrupts are not generated.

#1 : 1

PDDET0 detection interrupts are generated.

End of enumeration elements list.

SACK : Setup Transaction Normal Response Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

SACK interrupts are not generated.

#1 : 1

SACK interrupts are generated.

End of enumeration elements list.

SIGN : Setup Transaction Error Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

SIGN interrupts are not generated.

#1 : 1

SIGN interrupts are generated.

End of enumeration elements list.

EOFERR : EOF Error Detection Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

EOFERR interrupts are not generated.

#1 : 1

EOFERR interrupts are generated.

End of enumeration elements list.

LPMEND : LPM Transaction End Interrupt Status
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

LPMEND interrupts are not generated

#1 : 1

LPMEND interrupts are generated

End of enumeration elements list.

L1RSMEND : L1 Resume End Interrupt Status
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

L1RSMEND interrupts are not generated

#1 : 1

L1RSMEND interrupts are generated

End of enumeration elements list.

ATTCH : ATTCH Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

ATTCH interrupts are not generated.

#1 : 1

ATTCH interrupts are generated.

End of enumeration elements list.

DTCH : USB Disconnection Detection Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

DTCH interrupts are not generated.

#1 : 1

DTCH interrupts are generated.

End of enumeration elements list.

BCHG : USB Bus Change Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

BCHG interrupts are not generated.

#1 : 1

BCHG interrupts are generated.

End of enumeration elements list.

OVRCR : Overcurrent Input Change Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

OVRCR interrupts are not generated.

#1 : 1

OVRCR interrupts are generated.

End of enumeration elements list.


PIPE_CTR[7]

Pipe %s Control Register
address_offset : 0x428 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[7] PIPE_CTR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


BRDYSTS

BRDY Interrupt Status Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRDYSTS BRDYSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BRDY PIPE1BRDY PIPE2BRDY PIPE3BRDY PIPE4BRDY PIPE5BRDY PIPE6BRDY PIPE7BRDY PIPE8BRDY PIPE9BRDY

PIPE0BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE1BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE2BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE3BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE4BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE5BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE6BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE7BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE8BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE9BRDY : BRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.


NRDYSTS

NRDY Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NRDYSTS NRDYSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0NRDY PIPE1NRDY PIPE2NRDY PIPE3NRDY PIPE4NRDY PIPE5NRDY PIPE6NRDY PIPE7NRDY PIPE8NRDY PIPE9NRDY

PIPE0NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE1NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE2NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE3NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE4NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE5NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE6NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE7NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE8NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE9NRDY : NRDY Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.


BEMPSTS

BEMP Interrupt Status Register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BEMPSTS BEMPSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BEMP PIPE1BEMP PIPE2BEMP PIPE3BEMP PIPE4BEMP PIPE5BEMP PIPE6BEMP PIPE7BEMP PIPE8BEMP PIPE9BEMP

PIPE0BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE1BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE2BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE3BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE4BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE5BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE6BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE7BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE8BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.

PIPE9BEMP : BEMP Interrupt Status for PIPE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts are not generated.

#1 : 1

Interrupts are generated.

End of enumeration elements list.


PIPE_CTR[8]

Pipe %s Control Register
address_offset : 0x4A8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[8] PIPE_CTR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


FRMNUM

Frame Number Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRMNUM FRMNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNM CRCE OVRN

FRNM : Frame NumberLatest frame number
bits : 0 - 9 (10 bit)
access : read-only

CRCE : Receive Data Error
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

No error

#1 : 1

An error occurred

End of enumeration elements list.

OVRN : Overrun/Underrun Detection Status
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No error

#1 : 1

An error occurred

End of enumeration elements list.


UFRMNUM

uFrame Number Register
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UFRMNUM UFRMNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFRNM DVCHG

UFRNM : MicroframeIndicate the microframe number.
bits : 0 - 1 (2 bit)
access : read-only

DVCHG : Device State Change
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0].

#1 : 1

Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0].

End of enumeration elements list.


DEVADD[4]

Device Address Configuration Register
address_offset : 0x4F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[4] DEVADD[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


USBADDR

USB Address Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBADDR USBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBADDR STSRECOV0

USBADDR : USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully.
bits : 0 - 5 (6 bit)
access : read-only

STSRECOV0 : Status Recovery
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#001 : 001

Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected)

#010 : 010

Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected)

#011 : 011

Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected)

#100 : 100

Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected)

#101 : 101

Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected)

#110 : 110

Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected)

#111 : 111

Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected)

End of enumeration elements list.


USBREQ

USB Request Type Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBREQ USBREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMREQUESTTYPE BREQUEST

BMREQUESTTYPE : Request TypeThese bits store the USB request bmRequestType value.
bits : 0 - 6 (7 bit)
access : read-write

BREQUEST : RequestThese bits store the USB request bRequest value.
bits : 8 - 14 (7 bit)
access : read-write


USBVAL

USB Request Value Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBVAL USBVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WVALUE

WVALUE : ValueThese bits store the USB request Value value.
bits : 0 - 14 (15 bit)
access : read-write


USBINDX

USB Request Index Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBINDX USBINDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINDEX

WINDEX : IndexThese bits store the USB request wIndex value.
bits : 0 - 14 (15 bit)
access : read-write


USBLENG

USB Request Length Register
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBLENG USBLENG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLENGTH

WLENGTH : LengthThese bits store the USB request wLength value.
bits : 0 - 14 (15 bit)
access : read-write


DCPCFG

DCP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCPCFG DCPCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIR SHTNAK CNTMD

DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data receiving direction

#1 : 1

Data transmitting direction

End of enumeration elements list.

SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Pipe continued at the end of transfer

#1 : 1

Pipe disabled at the end of transfer

End of enumeration elements list.

CNTMD : Continuous Transfer Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-continuous transfer mode

#1 : 1

Continuous transfer mode

End of enumeration elements list.


DEVADD[5]

Device Address Configuration Register
address_offset : 0x5CE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[5] DEVADD[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


DCPMAXP

DCP Maximum Packet Size Register
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCPMAXP DCPMAXP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPS DEVSEL

MXPS : Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x08 : 0x08

8 bytes

0x10 : 0x10

16 bytes

0x18 : 0x18

24 bytes

0x20 : 0x20

32 bytes

0x28 : 0x28

40 bytes

0x30 : 0x30

48 bytes

0x38 : 0x38

56 bytes

0x40 : 0x40

64 bytes

0x48 : 0x48

72 bytes

0x50 : 0x50

80 bytes

0x58 : 0x58

88 bytes

0x60 : 0x60

96 bytes

0x68 : 0x68

104 bytes

0x70 : 0x70

112 bytes

0x78 : 0x78

120 bytes

End of enumeration elements list.

DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Address 0000

#0001 : 0001

Address 0001

#0010 : 0010

Address 0010

#0011 : 0011

Address 0011

#0100 : 0100

Address 0100

#0101 : 0101

Address 0101

End of enumeration elements list.


PLLSTA

PLL Status Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLLSTA PLLSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLLOCK

PLLLOCK : PLL Lock Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

PLL is not locked.

#1 : 1

PLL is locked.

End of enumeration elements list.


DCPCTR

DCP Control Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCPCTR DCPCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID CCPL PBUSY SQMON SQSET SQCLR SUREQCLR SUREQ BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

CCPL : Control Transfer End Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Completion of control transfer is enabled.

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

DCP is not used for the transaction.

#1 : 1

DCP is used for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Monitor
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Specifies DATA0.

End of enumeration elements list.

SUREQCLR : SUREQ Bit Clear
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Clears the SUREQ bit to 0.

End of enumeration elements list.

SUREQ : Setup Token Transmission
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Transmits the setup packet.

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access is disabled.

#1 : 1

Buffer access is enabled.

End of enumeration elements list.


PIPESEL

Pipe Window Select Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPESEL PIPESEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPESEL

PIPESEL : Pipe Window Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

No pipe selected

#0001 : 0001

PIPE1

#0010 : 0010

PIPE2

#0011 : 0011

PIPE3

#0100 : 0100

PIPE4

#0101 : 0101

PIPE5

#0110 : 0110

PIPE6

#0111 : 0111

PIPE7

#1000 : 1000

PIPE8

#1001 : 1001

PIPE9

End of enumeration elements list.


PIPECFG

Pipe Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPECFG PIPECFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM DIR SHTNAK DBLB BFRE TYPE

EPNUM : Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe.
bits : 0 - 2 (3 bit)
access : read-write

DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Receiving direction

#1 : 1

Transmitting direction

End of enumeration elements list.

SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Continue pipe operation after transfer ends

#1 : 1

Disable pipe operation after transfer ends.

End of enumeration elements list.

DBLB : Double Buffer Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Single buffer

#1 : 1

Double buffer

End of enumeration elements list.

BFRE : BRDY Interrupt Operation Specification
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

BRDY interrupt upon transmitting or receiving data

#1 : 1

BRDY interrupt upon completion of reading data

End of enumeration elements list.

TYPE : Transfer Type
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : 00

Pipe not used

#01 : 01

Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9)

#10 : 10

Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9)

#11 : 11

Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9)

End of enumeration elements list.


DEVADD[6]

Device Address Configuration Register
address_offset : 0x6AA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[6] DEVADD[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


PIPEMAXP

Pipe Maximum Packet Size Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEMAXP PIPEMAXP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPS DEVSEL

MXPS : Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.)
bits : 0 - 7 (8 bit)
access : read-write

DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Address 0000

#0001 : 0001

Address 0001

#0010 : 0010

Address 0010

#0011 : 0011

Address 0011

#0100 : 0100

Address 0100

#0101 : 0101

Address 0101

End of enumeration elements list.


PIPEPERI

Pipe Cycle Control Register
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEPERI PIPEPERI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IITV IFIS

IITV : Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2.
bits : 0 - 1 (2 bit)
access : read-write

IFIS : Isochronous IN Buffer Flush
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

The buffer is not flushed.

#1 : 1

The buffer is flushed.

End of enumeration elements list.


DEVADD[7]

Device Address Configuration Register
address_offset : 0x788 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[7] DEVADD[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


DVSTCTR0

Device State Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVSTCTR0 DVSTCTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHST UACT RESUME USBRST RWUPE WKUP VBUSEN EXICEN HNPBTOA

RHST : USB Bus Reset Status
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#000 : 000

Communication speed not determined

#001 : 001

Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected)

#010 : 010

Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected)

#011 : 011

Setting prohibited

End of enumeration elements list.

UACT : USB Bus Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Downstream port is disabled (SOF transmission is disabled).

#1 : 1

Downstream port is enabled (SOF transmission is enabled).

End of enumeration elements list.

RESUME : Resume Output
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Resume signal is not output.

#1 : 1

Resume signal is output.

End of enumeration elements list.

USBRST : USB Bus Reset Output
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

USB bus reset signal is not output.

#1 : 1

USB bus reset signal is output.

End of enumeration elements list.

RWUPE : Wakeup Detection Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Downstream port wakeup is disabled.

#1 : 1

Downstream port wakeup is enabled.

End of enumeration elements list.

WKUP : Wakeup Output
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Remote wakeup signal is not output.

#1 : 1

Remote wakeup signal is output.

End of enumeration elements list.

VBUSEN : USB_VBUSEN Output Pin Control
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

External USB_VBUSEN pin outputs low

#1 : 1

External USB_VBUSEN pin outputs high

End of enumeration elements list.

EXICEN : USB_EXICEN Output Pin Control
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

External USB_EXICEN pin outputs low

#1 : 1

External USB_EXICEN pin outputs high

End of enumeration elements list.

HNPBTOA : Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Switching from device B to device A is enabled

End of enumeration elements list.


DEVADD[8]

Device Address Configuration Register
address_offset : 0x868 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[8] DEVADD[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


PIPE_TR[0]-E

Pipe Transaction Counter Enable Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[0]-E PIPE_TR[0]-E read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

The current counter value is cleared.

End of enumeration elements list.

TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transaction counter is disabled.

#1 : 1

Transaction counter is enabled.

End of enumeration elements list.


PIPE_TR[0]-N

Pipe Transaction Counter Register
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_TR[0]-N PIPE_TR[0]-N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNCNT

TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write


DEVADD[9]

Device Address Configuration Register
address_offset : 0x94A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADD[9] DEVADD[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD HUBPORT UPPHUB

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

DEVADDn is not used

#01 : 01

Low speed

#10 : 10

Full speed

#11 : 11

Setting prohibited

End of enumeration elements list.

HUBPORT : Communication Target Connecting Hub Port
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

Directly connected to the port of the USBHS.

End of enumeration elements list.

UPPHUB : Communication Target Connecting Hub Register
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Directly connected to the port of the USBHS.

End of enumeration elements list.


USBBCCTRL0

BC Control Register 0
address_offset : 0xB0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBBCCTRL0 USBBCCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPDME0 IDPSRCE0 IDMSINKE0 VDPSRCE0 IDPSINKE0 VDMSRCE0 BATCHGE0 CHGDETSTS0 PDDETSTS0

RPDME0 : D- Pin Pull-Down Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Pull-down off

#1 : 1

Pull-down on

End of enumeration elements list.

IDPSRCE0 : D+ Pin IDPSRC Output Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stop

#1 : 1

10uA output

End of enumeration elements list.

IDMSINKE0 : D- Pin 0.6 V Input Detection (Comparator and Sink) Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Detection off

#1 : 1

Detection on ( Comparator and sink current on )

End of enumeration elements list.

VDPSRCE0 : D+ Pin VDPSRC (0.6 V) Output Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stop

#1 : 1

0.6V output

End of enumeration elements list.

IDPSINKE0 : D+ Pin 0.6 V Input Detection (Comparator and Sink) Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Detection off

#1 : 1

Detection on ( Comparator and sink current on )

End of enumeration elements list.

VDMSRCE0 : D- Pin VDMSRC (0.6 V) Output Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stop

#1 : 1

0.6V output

End of enumeration elements list.

BATCHGE0 : BC (Battery Charger) Function Ch0 General Enable Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

CHGDETSTS0 : D- Pin 0.6 V Input Detection Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not detected

#1 : 1

Detected

End of enumeration elements list.

PDDETSTS0 : D+ Pin 0.6 V Input Detection Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

Not detected

#1 : 1

Detected

End of enumeration elements list.


TESTMODE

USB Test Mode Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTMODE TESTMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UTST

UTST : Test Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

Normal operation

#0001 : 0001

Test_J TestMode(When the Function Controller Function is Selected)

#0010 : 0010

Test_K TestMode(When the Function Controller Function is Selected)

#0011 : 0011

Test_SE0_NAK TestMode(When the Function Controller Function is Selected)

#0100 : 0100

Test_Packet TestMode(When the Function Controller Function is Selected)

#0101 : 0101

Reserved TestMode(When the Function Controller Function is Selected)

#0110 : 0110

Reserved TestMode(When the Function Controller Function is Selected)

#0111 : 0111

Reserved TestMode(When the Function Controller Function is Selected)

#1001 : 1001

Test_J TestMode(When the Host Controller Function is Selected)

#1010 : 1010

Test_K TestMode(When the Host Controller Function is Selected)

#1011 : 1011

Test_SE0_NAK TestMode(When the Host Controller Function is Selected)

#1100 : 1100

Test_Packet TestMode(When the Host Controller Function is Selected)

#1101 : 1101

Test_Force_EnableTestMode(When the Host Controller Function is Selected)

#1110 : 1110

Reserved TestMode(When the Host Controller Function is Selected)

#1111 : 1111

Reserved TestMode(When the Host Controller Function is Selected)

End of enumeration elements list.


UCKSEL

USB Clock Selection Register
address_offset : 0xC4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCKSEL UCKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCKSELC

UCKSELC : USB Clock Selection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

High-speed on-chip oscillator clock (HOCO) is not selected as USB clock

#1 : 1

High-speed on-chip oscillator clock (HOCO) is selected as USB clock

End of enumeration elements list.


USBMC

USB Module Control Register
address_offset : 0xCC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBMC USBMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDDUSBE VDCEN

VDDUSBE : USB Reference Power Supply Circuit On/Off Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

USB reference power supply circuit off

#1 : 1

USB reference power supply circuit on

End of enumeration elements list.

VDCEN : USB Regulator On/Off Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

USB regulator off

#1 : 1

USB regulator on

End of enumeration elements list.


PIPE_CTR[0]

Pipe %s Control Register
address_offset : 0xE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE_CTR[0] PIPE_CTR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM CSSTS CSCLR INBUFM BSTS

PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

NAK response

#01 : 01

BUF response (depending on the buffer state)

#10 : 10

STALL response

#11 : 11

STALL response

End of enumeration elements list.

PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

Pipe n not in use for the transaction

#1 : 1

Pipe n in use for the transaction.

End of enumeration elements list.

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

DATA0

#1 : 1

DATA1

End of enumeration elements list.

SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA1.

End of enumeration elements list.

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Write disabled

#1 : 1

Specifies DATA0.

End of enumeration elements list.

ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled (all buffers are initialized)

End of enumeration elements list.

ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Auto response disabled.

#1 : 1

Auto response enabled.

End of enumeration elements list.

CSSTS : CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.

#1 : 1

CSplit Transaction processing is in progress.

End of enumeration elements list.

CSCLR : CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing is disabled.

#1 : 1

The CSSTS bit is cleared.

End of enumeration elements list.

INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

No data to be transmitted is in the FIFO buffer

#1 : 1

Data to be transmitted is in the FIFO buffer

End of enumeration elements list.

BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Buffer access by the CPU is disabled.

#1 : 1

Buffer access by the CPU is enabled.

End of enumeration elements list.


PHYSLEW

PHY Cross Point Adjustment Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYSLEW PHYSLEW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEWR00 SLEWR01 SLEWF00 SLEWF01

SLEWR00 : Receiver Cross Point Adjustment 00
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#1 : 1

Host or device controller mode.

End of enumeration elements list.

SLEWR01 : Receiver Cross Point Adjustment 01
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#1 : 1

Host or device controller mode.

End of enumeration elements list.

SLEWF00 : Receiver Cross Point Adjustment 00
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#1 : 1

Host or device controller mode.

End of enumeration elements list.

SLEWF01 : Receiver Cross Point Adjustment 01
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#1 : 1

Host or device controller mode.

End of enumeration elements list.



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