\n

Timer

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TAUJ2CDR0

TAUJ2CNT0

TAUJ2CNT1

TAUJ2CNT2

TAUJ2CNT3

TAUJ2CMUR0

TAUJ2CMUR1

TAUJ2CMUR2

TAUJ2CMUR3

TAUJ2CSR0

TAUJ2CSR1

TAUJ2CSR2

TAUJ2CSR3

TAUJ2CDR1

TAUJ2CSC0

TAUJ2CSC1

TAUJ2CSC2

TAUJ2CSC3

TAUJ2TE

TAUJ2TS

TAUJ2TT

TAUJ2TO

TAUJ2TOE

TAUJ2TOL

TAUJ2RDT

TAUJ2RSF

TAUJ2CDR2

TAUJ2CMOR0

TAUJ2CMOR1

TAUJ2CMOR2

TAUJ2CMOR3

TAUJ2TPS

TAUJ2BRS

TAUJ2TOM

TAUJ2TOC

TAUJ2RDE

TAUJ2RDM

TAUJ2CDR3


TAUJ2CDR0

channel data register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CDR0 TAUJ2CDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CNT0

channel counter register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CNT0 TAUJ2CNT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CNT1

channel counter register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CNT1 TAUJ2CNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CNT2

channel counter register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CNT2 TAUJ2CNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CNT3

channel counter register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CNT3 TAUJ2CNT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CMUR0

channel mode user register 0
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMUR0 TAUJ2CMUR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CMUR1

channel mode user register 1
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMUR1 TAUJ2CMUR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CMUR2

channel mode user register 2
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMUR2 TAUJ2CMUR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CMUR3

channel mode user register 3
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMUR3 TAUJ2CMUR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSR0

channel status register 0
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSR0 TAUJ2CSR0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSR1

channel status register 1
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSR1 TAUJ2CSR1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSR2

channel status register 2
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSR2 TAUJ2CSR2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSR3

channel status register 3
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSR3 TAUJ2CSR3 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CDR1

channel data register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CDR1 TAUJ2CDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CSC0

channel status clear trigger register 0
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSC0 TAUJ2CSC0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSC1

channel status clear trigger register 1
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSC1 TAUJ2CSC1 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSC2

channel status clear trigger register 2
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSC2 TAUJ2CSC2 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CSC3

channel status clear trigger register 3
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CSC3 TAUJ2CSC3 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TE

channel enable status register
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TE TAUJ2TE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TS

channel start trigger register
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TS TAUJ2TS write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TT

channel stop trigger register
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TT TAUJ2TT write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TO

channel output register
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TO TAUJ2TO read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TOE

channel output enable register
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TOE TAUJ2TOE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TOL

channel output active level register
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TOL TAUJ2TOL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2RDT

channel reload data trigger register
address_offset : 0x68 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2RDT TAUJ2RDT write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2RSF

channel reload status register
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUJ2RSF TAUJ2RSF read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CDR2

channel data register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CDR2 TAUJ2CDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CMOR0

channel mode OS register 0
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMOR0 TAUJ2CMOR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CMOR1

channel mode OS register 1
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMOR1 TAUJ2CMOR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CMOR2

channel mode OS register 2
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMOR2 TAUJ2CMOR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2CMOR3

channel mode OS register 3
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CMOR3 TAUJ2CMOR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2TPS

prescaler clock select register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TPS TAUJ2TPS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUJ2BRS

prescaler baud rate setting register
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2BRS TAUJ2BRS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TOM

channel output mode register
address_offset : 0x98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TOM TAUJ2TOM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2TOC

channel output configuration register
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2TOC TAUJ2TOC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2RDE

channel reload data enable register
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2RDE TAUJ2RDE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2RDM

channel reload data mode register
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2RDM TAUJ2RDM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUJ2CDR3

channel data register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUJ2CDR3 TAUJ2CDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.