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IIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IICBnDAT

IICBnSTR0

IICBnSTR1

IICBnSTRC

IICBnCTL1

IICBnWL

IICBnWH

IICBnSVA

IICBnCTL0

IICBnTRG


IICBnDAT

Data register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnDAT IICBnDAT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IICBnSTR0

Status Register 0
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IICBnSTR0 IICBnSTR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IICBnSTR1

Status Register 1
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IICBnSTR1 IICBnSTR1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IICBnSTRC

Status clear register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnSTRC IICBnSTRC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IICBnCTL1

Control Register 1
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnCTL1 IICBnCTL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IICBnWL

Low level width setting register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnWL IICBnWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IICBnWH

High level width setting register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnWH IICBnWH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IICBnSVA

Slave address register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnSVA IICBnSVA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IICBnCTL0

Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnCTL0 IICBnCTL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IICBnTRG

Trigger register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICBnTRG IICBnTRG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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