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CC_Link

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MWRENL

M3RCEX

CCRES

CCSMD

M3MRRWW0_L

M3MRRWW0_H

M3MRRWW1_L

M3MRRWW1_H

M3MRRWW2_L

M3MRRWW2_H

M3STNO

M3MRRWW3_L

M3MRRWW3_H

M3KYOKU_BSW

M3ERR1SW

M3SDOK

M3RDRQ

M3VENDORCODE

M3MODELCODE

M3PROTOCOLVERSION

M3SLED03

M3TIM03

M3RMST1

M3RMST2

M3RMRX00_07

M3RMRX08_0F

M3RMRX10_17

M3RMRX18_1F

M3ERR2TR

M3RMRWR0_L

M3RMRWR0_H

M3RMRWR1_L

M3RMRWR1_H

M3RMRWR2_L

M3RMRWR2_H

M3RMRWR3_L

M3RMRWR3_H

M3HOLDCLR

M3MRST1

M3MRST2

M3MRRY00_07

M3MRRY08_0F

M3MRRY10_17

M3MRRY18_1F


MWRENL

transmission data write enable info
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MWRENL MWRENL read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RCEX

receive data update check info
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3RCEX M3RCEX read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CCRES

CC-Link reset register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCRES CCRES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCSMD

CC-Link remote device mode set register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCSMD CCSMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M3MRRWW0_L

M to R RWw0(L)
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW0_L M3MRRWW0_L read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW0_H

M to R RWw0(H)
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW0_H M3MRRWW0_H read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW1_L

M to R RWw1(L)
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW1_L M3MRRWW1_L read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW1_H

M to R RWw1(H)
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW1_H M3MRRWW1_H read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW2_L

M to R RWw2(L)
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW2_L M3MRRWW2_L read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW2_H

M to R RWw2(H)
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW2_H M3MRRWW2_H read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3STNO

node number setting switch info
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3STNO M3STNO read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW3_L

M to R RWw3(L)
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW3_L M3MRRWW3_L read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRWW3_H

M to R RWw3(H)
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRWW3_H M3MRRWW3_H read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3KYOKU_BSW

numbers of stations occupied info/baud rate switch info
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3KYOKU_BSW M3KYOKU_BSW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3ERR1SW

error info1(switch state)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3ERR1SW M3ERR1SW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3SDOK

transmission data write completion flag
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3SDOK M3SDOK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RDRQ

receive data read request flag
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3RDRQ M3RDRQ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3VENDORCODE

Maker code
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3VENDORCODE M3VENDORCODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M3MODELCODE

Model code
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3MODELCODE M3MODELCODE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3PROTOCOLVERSION

Protocol version
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3PROTOCOLVERSION M3PROTOCOLVERSION read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3SLED03

SDLED blinking period setting
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3SLED03 M3SLED03 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3TIM03

time over setting
address_offset : 0x47 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3TIM03 M3TIM03 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMST1

R to M ST1
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3RMST1 M3RMST1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMST2

R to M ST2
address_offset : 0x49 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3RMST2 M3RMST2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRX00_07

R to M RX00-07
address_offset : 0x4A Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRX00_07 M3RMRX00_07 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRX08_0F

R to M RX08-0F
address_offset : 0x4B Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRX08_0F M3RMRX08_0F write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRX10_17

R to M RX10-17
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRX10_17 M3RMRX10_17 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRX18_1F

R to M RX18-1F
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRX18_1F M3RMRX18_1F write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3ERR2TR

error info2(transmission state)
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3ERR2TR M3ERR2TR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR0_L

M to R RWw0(L)
address_offset : 0x5A Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR0_L M3RMRWR0_L write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR0_H

M to R RWw0(H)
address_offset : 0x5B Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR0_H M3RMRWR0_H write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR1_L

M to R RWw1(L)
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR1_L M3RMRWR1_L write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR1_H

M to R RWw1(H)
address_offset : 0x5D Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR1_H M3RMRWR1_H write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR2_L

M to R RWw2(L)
address_offset : 0x5E Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR2_L M3RMRWR2_L write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR2_H

M to R RWw2(H)
address_offset : 0x5F Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR2_H M3RMRWR2_H write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR3_L

M to R RWw3(L)
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR3_L M3RMRWR3_L write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3RMRWR3_H

M to R RWw3(H)
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

M3RMRWR3_H M3RMRWR3_H write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3HOLDCLR

HOLD/CLR info setting
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3HOLDCLR M3HOLDCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRST1

M to R ST1
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRST1 M3MRST1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRST2

M to R ST2
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRST2 M3MRST2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRY00_07

M to R RY00-07
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRY00_07 M3MRRY00_07 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRY08_0F

M to R RY08-0F
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRY08_0F M3MRRY08_0F read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRY10_17

M to R RY10-17
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRY10_17 M3MRRY10_17 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

M3MRRY18_1F

M to R RY18-1F
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3MRRY18_1F M3MRRY18_1F read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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