\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Software Pulse Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0PULSE : Channel 0 Pulse Generation
bits : 0 - 0 (1 bit)
access : write-only
CH1PULSE : Channel 1 Pulse Generation
bits : 1 - 1 (1 bit)
access : write-only
CH2PULSE : Channel 2 Pulse Generation
bits : 2 - 2 (1 bit)
access : write-only
CH3PULSE : Channel 3 Pulse Generation
bits : 3 - 3 (1 bit)
access : write-only
CH4PULSE : Channel 4 Pulse Generation
bits : 4 - 4 (1 bit)
access : write-only
CH5PULSE : Channel 5 Pulse Generation
bits : 5 - 5 (1 bit)
access : write-only
CH6PULSE : Channel 6 Pulse Generation
bits : 6 - 6 (1 bit)
access : write-only
CH7PULSE : Channel 7 Pulse Generation
bits : 7 - 7 (1 bit)
access : write-only
CH8PULSE : Channel 8 Pulse Generation
bits : 8 - 8 (1 bit)
access : write-only
CH9PULSE : Channel 9 Pulse Generation
bits : 9 - 9 (1 bit)
access : write-only
CH10PULSE : Channel 10 Pulse Generation
bits : 10 - 10 (1 bit)
access : write-only
CH11PULSE : Channel 11 Pulse Generation
bits : 11 - 11 (1 bit)
access : write-only
I/O Routing Location Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
0x00000008 : LOC8
Location 8
0x00000009 : LOC9
Location 9
0x0000000A : LOC10
Location 10
0x0000000B : LOC11
Location 11
0x0000000C : LOC12
Location 12
0x0000000D : LOC13
Location 13
End of enumeration elements list.
CH1LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
CH2LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
CH3LOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
0x00000008 : LOC8
Location 8
0x00000009 : LOC9
Location 9
0x0000000A : LOC10
Location 10
0x0000000B : LOC11
Location 11
0x0000000C : LOC12
Location 12
0x0000000D : LOC13
Location 13
0x0000000E : LOC14
Location 14
End of enumeration elements list.
I/O Routing Location Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
End of enumeration elements list.
CH5LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
End of enumeration elements list.
CH6LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
0x00000008 : LOC8
Location 8
0x00000009 : LOC9
Location 9
0x0000000A : LOC10
Location 10
0x0000000B : LOC11
Location 11
0x0000000C : LOC12
Location 12
0x0000000D : LOC13
Location 13
0x0000000E : LOC14
Location 14
0x0000000F : LOC15
Location 15
0x00000010 : LOC16
Location 16
0x00000011 : LOC17
Location 17
End of enumeration elements list.
CH7LOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
0x00000008 : LOC8
Location 8
0x00000009 : LOC9
Location 9
0x0000000A : LOC10
Location 10
End of enumeration elements list.
I/O Routing Location Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
0x00000008 : LOC8
Location 8
0x00000009 : LOC9
Location 9
0x0000000A : LOC10
Location 10
End of enumeration elements list.
CH9LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
0x00000008 : LOC8
Location 8
0x00000009 : LOC9
Location 9
0x0000000A : LOC10
Location 10
0x0000000B : LOC11
Location 11
0x0000000C : LOC12
Location 12
0x0000000D : LOC13
Location 13
0x0000000E : LOC14
Location 14
0x0000000F : LOC15
Location 15
0x00000010 : LOC16
Location 16
End of enumeration elements list.
CH10LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
CH11LOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEVONPRS : Set Event on PRS
bits : 0 - 0 (1 bit)
access : read-write
SEVONPRSSEL : SEVONPRS PRS Channel Select
bits : 1 - 4 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected
0x00000001 : PRSCH1
PRS Channel 1 selected
0x00000002 : PRSCH2
PRS Channel 2 selected
0x00000003 : PRSCH3
PRS Channel 3 selected
0x00000004 : PRSCH4
PRS Channel 4 selected
0x00000005 : PRSCH5
PRS Channel 5 selected
0x00000006 : PRSCH6
PRS Channel 6 selected
0x00000007 : PRSCH7
PRS Channel 7 selected
0x00000008 : PRSCH8
PRS Channel 8 selected
0x00000009 : PRSCH9
PRS Channel 9 selected
0x0000000A : PRSCH10
PRS Channel 10 selected
0x0000000B : PRSCH11
PRS Channel 11 selected
End of enumeration elements list.
DMA Request 0 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DMA Request 0 PRS Channel Select
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected
0x00000001 : PRSCH1
PRS Channel 1 selected
0x00000002 : PRSCH2
PRS Channel 2 selected
0x00000003 : PRSCH3
PRS Channel 3 selected
0x00000004 : PRSCH4
PRS Channel 4 selected
0x00000005 : PRSCH5
PRS Channel 5 selected
0x00000006 : PRSCH6
PRS Channel 6 selected
0x00000007 : PRSCH7
PRS Channel 7 selected
0x00000008 : PRSCH8
PRS Channel 8 selected
0x00000009 : PRSCH9
PRS Channel 9 selected
0x0000000A : PRSCH10
PRS Channel 10 selected
0x0000000B : PRSCH11
PRS Channel 11 selected
End of enumeration elements list.
DMA Request 1 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DMA Request 1 PRS Channel Select
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected
0x00000001 : PRSCH1
PRS Channel 1 selected
0x00000002 : PRSCH2
PRS Channel 2 selected
0x00000003 : PRSCH3
PRS Channel 3 selected
0x00000004 : PRSCH4
PRS Channel 4 selected
0x00000005 : PRSCH5
PRS Channel 5 selected
0x00000006 : PRSCH6
PRS Channel 6 selected
0x00000007 : PRSCH7
PRS Channel 7 selected
0x00000008 : PRSCH8
PRS Channel 8 selected
0x00000009 : PRSCH9
PRS Channel 9 selected
0x0000000A : PRSCH10
PRS Channel 10 selected
0x0000000B : PRSCH11
PRS Channel 11 selected
End of enumeration elements list.
PRS Channel Values
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Channel 0 Current Value
bits : 0 - 0 (1 bit)
access : read-only
CH1VAL : Channel 1 Current Value
bits : 1 - 1 (1 bit)
access : read-only
CH2VAL : Channel 2 Current Value
bits : 2 - 2 (1 bit)
access : read-only
CH3VAL : Channel 3 Current Value
bits : 3 - 3 (1 bit)
access : read-only
CH4VAL : Channel 4 Current Value
bits : 4 - 4 (1 bit)
access : read-only
CH5VAL : Channel 5 Current Value
bits : 5 - 5 (1 bit)
access : read-only
CH6VAL : Channel 6 Current Value
bits : 6 - 6 (1 bit)
access : read-only
CH7VAL : Channel 7 Current Value
bits : 7 - 7 (1 bit)
access : read-only
CH8VAL : Channel 8 Current Value
bits : 8 - 8 (1 bit)
access : read-only
CH9VAL : Channel 9 Current Value
bits : 9 - 9 (1 bit)
access : read-only
CH10VAL : Channel 10 Current Value
bits : 10 - 10 (1 bit)
access : read-only
CH11VAL : Channel 11 Current Value
bits : 11 - 11 (1 bit)
access : read-only
Software Level Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0LEVEL : Channel 0 Software Level
bits : 0 - 0 (1 bit)
access : read-write
CH1LEVEL : Channel 1 Software Level
bits : 1 - 1 (1 bit)
access : read-write
CH2LEVEL : Channel 2 Software Level
bits : 2 - 2 (1 bit)
access : read-write
CH3LEVEL : Channel 3 Software Level
bits : 3 - 3 (1 bit)
access : read-write
CH4LEVEL : Channel 4 Software Level
bits : 4 - 4 (1 bit)
access : read-write
CH5LEVEL : Channel 5 Software Level
bits : 5 - 5 (1 bit)
access : read-write
CH6LEVEL : Channel 6 Software Level
bits : 6 - 6 (1 bit)
access : read-write
CH7LEVEL : Channel 7 Software Level
bits : 7 - 7 (1 bit)
access : read-write
CH8LEVEL : Channel 8 Software Level
bits : 8 - 8 (1 bit)
access : read-write
CH9LEVEL : Channel 9 Software Level
bits : 9 - 9 (1 bit)
access : read-write
CH10LEVEL : Channel 10 Software Level
bits : 10 - 10 (1 bit)
access : read-write
CH11LEVEL : Channel 11 Software Level
bits : 11 - 11 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRSL
Peripheral Reflex System
0x00000002 : PRSH
Peripheral Reflex System
0x00000006 : ACMP0
Analog Comparator 0
0x00000007 : ACMP1
Analog Comparator 1
0x00000008 : ADC0
Analog to Digital Converter 0
0x00000010 : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x00000011 : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000001C : TIMER0
Timer 0
0x0000001D : TIMER1
Timer 1
0x00000029 : RTCC
Real-Time Counter and Calendar
0x00000030 : GPIOL
General purpose Input/Output
0x00000031 : GPIOH
General purpose Input/Output
0x00000034 : LETIMER0
Low Energy Timer 0
0x00000036 : PCNT0
Pulse Counter 0
0x0000003C : CRYOTIMER
CRYOTIMER
0x0000003D : CMU
Clock Management Unit
0x00000043 : CM4
None
End of enumeration elements list.
EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : OFF
Signal is left as it is
0x00000001 : POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
0x00000002 : NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
0x00000003 : BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
End of enumeration elements list.
STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write
INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write
ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write
ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write
ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write
I/O Routing Pin Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0PEN : CH0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
CH1PEN : CH1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
CH2PEN : CH2 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write
CH3PEN : CH3 Pin Enable
bits : 3 - 3 (1 bit)
access : read-write
CH4PEN : CH4 Pin Enable
bits : 4 - 4 (1 bit)
access : read-write
CH5PEN : CH5 Pin Enable
bits : 5 - 5 (1 bit)
access : read-write
CH6PEN : CH6 Pin Enable
bits : 6 - 6 (1 bit)
access : read-write
CH7PEN : CH7 Pin Enable
bits : 7 - 7 (1 bit)
access : read-write
CH8PEN : CH8 Pin Enable
bits : 8 - 8 (1 bit)
access : read-write
CH9PEN : CH9 Pin Enable
bits : 9 - 9 (1 bit)
access : read-write
CH10PEN : CH10 Pin Enable
bits : 10 - 10 (1 bit)
access : read-write
CH11PEN : CH11 Pin Enable
bits : 11 - 11 (1 bit)
access : read-write
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