\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDIFEN : Peripheral Block Enable
bits : 0 - 1 (2 bit)
RXDMAEN : Receiver DMA ENable for data flow
bits : 2 - 2 (1 bit)
RXSTEO : STerEO Mode
bits : 3 - 3 (1 bit)
DRFMT : RX Data format
bits : 4 - 5 (2 bit)
PMSK : Mask Parity error bit
bits : 6 - 6 (1 bit)
VMSK : Mask of Validity bit
bits : 7 - 7 (1 bit)
CUMSK : Mask of channel status and user bits
bits : 8 - 8 (1 bit)
PTMSK : Mask of Preamble Type bits
bits : 9 - 9 (1 bit)
CBDMAEN : Control Buffer DMA ENable for control flow
bits : 10 - 10 (1 bit)
CHSEL : Channel Selection
bits : 11 - 11 (1 bit)
NBTR : Maximum allowed re-tries during synchronization phase
bits : 12 - 13 (2 bit)
WFA : Wait For Activity
bits : 14 - 14 (1 bit)
INSEL : input selection
bits : 16 - 18 (3 bit)
Data input register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DR : Parity Error bit
bits : 0 - 23 (24 bit)
PE : Parity Error bit
bits : 24 - 24 (1 bit)
V : Validity bit
bits : 25 - 25 (1 bit)
U : User bit
bits : 26 - 26 (1 bit)
C : Channel Status bit
bits : 27 - 27 (1 bit)
PT : Preamble Type
bits : 28 - 29 (2 bit)
Channel Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USR : User data information
bits : 0 - 15 (16 bit)
CS : Channel A status information
bits : 16 - 23 (8 bit)
SOB : Start Of Block
bits : 24 - 24 (1 bit)
Debug Information register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
THI : Threshold HIGH
bits : 0 - 12 (13 bit)
TLO : Threshold LOW
bits : 16 - 28 (13 bit)
Interrupt mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNEIE : RXNE interrupt enable
bits : 0 - 0 (1 bit)
CSRNEIE : Control Buffer Ready Interrupt Enable
bits : 1 - 1 (1 bit)
PERRIE : Parity error interrupt enable
bits : 2 - 2 (1 bit)
OVRIE : Overrun error Interrupt Enable
bits : 3 - 3 (1 bit)
SBLKIE : Synchronization Block Detected Interrupt Enable
bits : 4 - 4 (1 bit)
SYNCDIE : Synchronization Done
bits : 5 - 5 (1 bit)
IFEIE : Serial Interface Error Interrupt Enable
bits : 6 - 6 (1 bit)
Status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXNE : Read data register not empty
bits : 0 - 0 (1 bit)
CSRNE : Control Buffer register is not empty
bits : 1 - 1 (1 bit)
PERR : Parity error
bits : 2 - 2 (1 bit)
OVR : Overrun error
bits : 3 - 3 (1 bit)
SBD : Synchronization Block Detected
bits : 4 - 4 (1 bit)
SYNCD : Synchronization Done
bits : 5 - 5 (1 bit)
FERR : Framing error
bits : 6 - 6 (1 bit)
SERR : Synchronization error
bits : 7 - 7 (1 bit)
TERR : Time-out error
bits : 8 - 8 (1 bit)
WIDTH5 : Duration of 5 symbols counted with SPDIF_CLK
bits : 16 - 30 (15 bit)
Interrupt Flag Clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PERRCF : Clears the Parity error flag
bits : 2 - 2 (1 bit)
OVRCF : Clears the Overrun error flag
bits : 3 - 3 (1 bit)
SBDCF : Clears the Synchronization Block Detected flag
bits : 4 - 4 (1 bit)
SYNCDCF : Clears the Synchronization Done flag
bits : 5 - 5 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.