\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Ethernet MMC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR : CR
bits : 0 - 0 (1 bit)
CSR : CSR
bits : 1 - 1 (1 bit)
ROR : ROR
bits : 2 - 2 (1 bit)
MCF : MCF
bits : 3 - 3 (1 bit)
MCP : MCP
bits : 4 - 4 (1 bit)
MCFHP : MCFHP
bits : 5 - 5 (1 bit)
Ethernet MMC transmit interrupt mask register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TGFSCM : TGFSCM
bits : 14 - 14 (1 bit)
TGFMSCM : TGFMSCM
bits : 15 - 15 (1 bit)
TGFM : TGFM
bits : 16 - 16 (1 bit)
Ethernet MMC receive interrupt register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFCES : RFCES
bits : 5 - 5 (1 bit)
RFAES : RFAES
bits : 6 - 6 (1 bit)
RGUFS : RGUFS
bits : 17 - 17 (1 bit)
Ethernet MMC transmitted good frames after a single collision counter
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TGFSCC : TGFSCC
bits : 0 - 31 (32 bit)
Ethernet MMC transmitted good frames after more than a single collision
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TGFMSCC : TGFMSCC
bits : 0 - 31 (32 bit)
Ethernet MMC transmitted good frames counter register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TGFC : HTL
bits : 0 - 31 (32 bit)
Ethernet MMC transmit interrupt register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TGFSCS : TGFSCS
bits : 14 - 14 (1 bit)
TGFMSCS : TGFMSCS
bits : 15 - 15 (1 bit)
TGFS : TGFS
bits : 21 - 21 (1 bit)
Ethernet MMC received frames with CRC error counter register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFCFC : RFCFC
bits : 0 - 31 (32 bit)
Ethernet MMC received frames with alignment error counter register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFAEC : RFAEC
bits : 0 - 31 (32 bit)
Ethernet MMC receive interrupt mask register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFCEM : RFCEM
bits : 5 - 5 (1 bit)
RFAEM : RFAEM
bits : 6 - 6 (1 bit)
RGUFM : RGUFM
bits : 17 - 17 (1 bit)
MMC received good unicast frames counter register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RGUFC : RGUFC
bits : 0 - 31 (32 bit)
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