\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Ethernet MAC configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE : RE
bits : 2 - 2 (1 bit)
TE : TE
bits : 3 - 3 (1 bit)
DC : DC
bits : 4 - 4 (1 bit)
BL : BL
bits : 5 - 6 (2 bit)
APCS : APCS
bits : 7 - 7 (1 bit)
RD : RD
bits : 9 - 9 (1 bit)
IPCO : IPCO
bits : 10 - 10 (1 bit)
DM : DM
bits : 11 - 11 (1 bit)
LM : LM
bits : 12 - 12 (1 bit)
ROD : ROD
bits : 13 - 13 (1 bit)
FES : FES
bits : 14 - 14 (1 bit)
CSD : CSD
bits : 16 - 16 (1 bit)
IFG : IFG
bits : 17 - 19 (3 bit)
JD : JD
bits : 22 - 22 (1 bit)
WD : WD
bits : 23 - 23 (1 bit)
CSTF : CSTF
bits : 25 - 25 (1 bit)
Ethernet MAC MII address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : MII busy
bits : 0 - 0 (1 bit)
MW : MII write
bits : 1 - 1 (1 bit)
CR : Clock range
bits : 2 - 4 (3 bit)
MR : MII register
bits : 6 - 10 (5 bit)
PA : PHY address
bits : 11 - 15 (5 bit)
Ethernet MAC MII data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : MII data
bits : 0 - 15 (16 bit)
Ethernet MAC flow control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCB : Flow control busy/back pressure activate
bits : 0 - 0 (1 bit)
TFCE : Transmit flow control enable
bits : 1 - 1 (1 bit)
RFCE : Receive flow control enable
bits : 2 - 2 (1 bit)
UPFD : Unicast pause frame detect
bits : 3 - 3 (1 bit)
PLT : Pause low threshold
bits : 4 - 5 (2 bit)
ZQPD : Zero-quanta pause disable
bits : 7 - 7 (1 bit)
PT : Pause time
bits : 16 - 31 (16 bit)
Ethernet MAC VLAN tag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLANTI : VLAN tag identifier
bits : 0 - 15 (16 bit)
VLANTC : 12-bit VLAN tag comparison
bits : 16 - 16 (1 bit)
Ethernet MAC remote wakeup frame filter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Ethernet MAC PMT control and status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : Power down
bits : 0 - 0 (1 bit)
MPE : Magic Packet enable
bits : 1 - 1 (1 bit)
WFE : Wakeup frame enable
bits : 2 - 2 (1 bit)
MPR : Magic packet received
bits : 5 - 5 (1 bit)
WFR : Wakeup frame received
bits : 6 - 6 (1 bit)
GU : Global unicast
bits : 9 - 9 (1 bit)
WFFRPR : Wakeup frame filter register pointer reset
bits : 31 - 31 (1 bit)
Ethernet MAC debug register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MMRPEA : MAC MII receive protocol engine active
bits : 0 - 0 (1 bit)
MSFRWCS : MAC small FIFO read / write controllers status
bits : 1 - 1 (1 bit)
RFWRA : Rx FIFO write controller active
bits : 4 - 4 (1 bit)
RFRCS : Rx FIFO read controller status
bits : 5 - 5 (1 bit)
RFFL : Rx FIFO fill level
bits : 8 - 8 (1 bit)
MMTEA : MAC MII transmit engine active
bits : 16 - 16 (1 bit)
MTFCS : MAC transmit frame controller status
bits : 17 - 18 (2 bit)
MTP : MAC transmitter in pause
bits : 19 - 19 (1 bit)
TFRS : Tx FIFO read status
bits : 20 - 21 (2 bit)
TFWA : Tx FIFO write active
bits : 22 - 22 (1 bit)
TFNE : Tx FIFO not empty
bits : 24 - 24 (1 bit)
TFF : Tx FIFO full
bits : 25 - 25 (1 bit)
Ethernet MAC interrupt status register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMTS : PMT status
bits : 3 - 3 (1 bit)
access : read-only
MMCS : MMC status
bits : 4 - 4 (1 bit)
access : read-only
MMCRS : MMC receive status
bits : 5 - 5 (1 bit)
access : read-only
MMCTS : MMC transmit status
bits : 6 - 6 (1 bit)
access : read-only
TSTS : Time stamp trigger status
bits : 9 - 9 (1 bit)
access : read-write
Ethernet MAC interrupt mask register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMTIM : PMT interrupt mask
bits : 3 - 3 (1 bit)
TSTIM : Time stamp trigger interrupt mask
bits : 9 - 9 (1 bit)
Ethernet MAC frame filter register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM : Promiscuous mode
bits : 0 - 0 (1 bit)
HU : Hash unicast
bits : 1 - 1 (1 bit)
HM : Hash multicast
bits : 2 - 2 (1 bit)
DAIF : Destination address inverse filtering
bits : 3 - 3 (1 bit)
PAM : Pass all multicast
bits : 4 - 4 (1 bit)
BFD : Broadcast frames disable
bits : 5 - 5 (1 bit)
PCF : Pass control frames
bits : 6 - 6 (1 bit)
SAIF : Source address inverse filtering
bits : 8 - 8 (1 bit)
SAF : Source address filter
bits : 9 - 9 (1 bit)
HPF : Hash or perfect filter
bits : 10 - 10 (1 bit)
RA : Receive all
bits : 31 - 31 (1 bit)
Ethernet MAC address 0 high register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACA0H : MAC address0 high
bits : 0 - 15 (16 bit)
access : read-write
MO : MO
bits : 31 - 31 (1 bit)
access : read-only
Ethernet MAC address 0 low register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACA0L : MAC address0 low
bits : 0 - 31 (32 bit)
Ethernet MAC address 1 high register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACA1H : MAC address1 high
bits : 0 - 15 (16 bit)
MBC : Mask byte control
bits : 24 - 29 (6 bit)
SA : Source address
bits : 30 - 30 (1 bit)
AE : Address enable
bits : 31 - 31 (1 bit)
Ethernet MAC address1 low register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACA1LR : MAC address1 low
bits : 0 - 31 (32 bit)
Ethernet MAC address 2 high register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC2AH : MAC address2 high
bits : 0 - 15 (16 bit)
MBC : Mask byte control
bits : 24 - 29 (6 bit)
SA : Source address
bits : 30 - 30 (1 bit)
AE : Address enable
bits : 31 - 31 (1 bit)
Ethernet MAC address 2 low register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACA2L : MAC address2 low
bits : 0 - 30 (31 bit)
Ethernet MAC address 3 high register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACA3H : MAC address3 high
bits : 0 - 15 (16 bit)
MBC : Mask byte control
bits : 24 - 29 (6 bit)
SA : Source address
bits : 30 - 30 (1 bit)
AE : Address enable
bits : 31 - 31 (1 bit)
Ethernet MAC address 3 low register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBCA3L : MAC address3 low
bits : 0 - 31 (32 bit)
Ethernet MAC hash table high register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTH : Hash table high
bits : 0 - 31 (32 bit)
Ethernet MAC hash table low register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTL : Hash table low
bits : 0 - 31 (32 bit)
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