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SAI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SAI_ASLOTR

SAI_AIM

SAI_ASR

SAI_ACLRFR

SAI_ADR

SAI_BCR1

SAI_BCR2

SAI_BFRCR

SAI_BSLOTR

SAI_BIM

SAI_BSR

SAI_BCLRFR

SAI_ACR1

SAI_BDR

SAI_ACR2

SAI_AFRCR


SAI_ASLOTR

SAI ASlot register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ASLOTR SAI_ASLOTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBOFF SLOTSZ NBSLOT SLOTEN

FBOFF : First bit offset
bits : 0 - 4 (5 bit)

SLOTSZ : Slot size
bits : 6 - 7 (2 bit)

NBSLOT : Number of slots in an audio frame
bits : 8 - 11 (4 bit)

SLOTEN : Slot enable
bits : 16 - 31 (16 bit)


SAI_AIM

SAI AInterrupt mask register2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_AIM SAI_AIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDRIE MUTEDETIE WCKCFGIE FREQIE CNRDYIE AFSDETIE LFSDETIE

OVRUDRIE : Overrun/underrun interrupt enable
bits : 0 - 0 (1 bit)

MUTEDETIE : Mute detection interrupt enable
bits : 1 - 1 (1 bit)

WCKCFGIE : Wrong clock configuration interrupt enable
bits : 2 - 2 (1 bit)

FREQIE : FIFO request interrupt enable
bits : 3 - 3 (1 bit)

CNRDYIE : Codec not ready interrupt enable
bits : 4 - 4 (1 bit)

AFSDETIE : Anticipated frame synchronization detection interrupt enable
bits : 5 - 5 (1 bit)

LFSDETIE : Late frame synchronization detection interrupt enable
bits : 6 - 6 (1 bit)


SAI_ASR

SAI AStatus register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_ASR SAI_ASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDR MUTEDET WCKCFG FREQ CNRDY AFSDET LFSDET FLTH

OVRUDR : Overrun / underrun
bits : 0 - 0 (1 bit)

MUTEDET : Mute detection
bits : 1 - 1 (1 bit)

WCKCFG : Wrong clock configuration flag
bits : 2 - 2 (1 bit)

FREQ : FIFO request
bits : 3 - 3 (1 bit)

CNRDY : Codec not ready
bits : 4 - 4 (1 bit)

AFSDET : Anticipated frame synchronization detection
bits : 5 - 5 (1 bit)

LFSDET : Late frame synchronization detection
bits : 6 - 6 (1 bit)

FLTH : FIFO level threshold
bits : 16 - 18 (3 bit)


SAI_ACLRFR

SAI AClear flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ACLRFR SAI_ACLRFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVRUDR CMUTEDET CWCKCFG CCNRDY CAFSDET CLFSDET

COVRUDR : Clear overrun / underrun
bits : 0 - 0 (1 bit)

CMUTEDET : Mute detection flag
bits : 1 - 1 (1 bit)

CWCKCFG : Clear wrong clock configuration flag
bits : 2 - 2 (1 bit)

CCNRDY : Clear codec not ready flag
bits : 4 - 4 (1 bit)

CAFSDET : Clear anticipated frame synchronization detection flag
bits : 5 - 5 (1 bit)

CLFSDET : Clear late frame synchronization detection flag
bits : 6 - 6 (1 bit)


SAI_ADR

SAI AData register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ADR SAI_ADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


SAI_BCR1

SAI BConfiguration register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BCR1 SAI_BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PRTCFG DS LSBFIRST CKSTR SYNCEN MONO OUTDRIV SAIBEN DMAEN NODIV MCKDIV

MODE : Audio block mode
bits : 0 - 1 (2 bit)

PRTCFG : Protocol configuration
bits : 2 - 3 (2 bit)

DS : Data size
bits : 5 - 7 (3 bit)

LSBFIRST : Least significant bit first
bits : 8 - 8 (1 bit)

CKSTR : Clock strobing edge
bits : 9 - 9 (1 bit)

SYNCEN : Synchronization enable
bits : 10 - 11 (2 bit)

MONO : Mono mode
bits : 12 - 12 (1 bit)

OUTDRIV : Output drive
bits : 13 - 13 (1 bit)

SAIBEN : Audio block enable
bits : 16 - 16 (1 bit)

DMAEN : DMA enable
bits : 17 - 17 (1 bit)

NODIV : No divider
bits : 19 - 19 (1 bit)

MCKDIV : Master clock divider
bits : 20 - 23 (4 bit)


SAI_BCR2

SAI BConfiguration register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BCR2 SAI_BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH FFLUSH TRIS MUTE MUTEVAL MUTECNT CPL COMP

FTH : FIFO threshold
bits : 0 - 2 (3 bit)

FFLUSH : FIFO flush
bits : 3 - 3 (1 bit)

TRIS : Tristate management on data line
bits : 4 - 4 (1 bit)

MUTE : Mute
bits : 5 - 5 (1 bit)

MUTEVAL : Mute value
bits : 6 - 6 (1 bit)

MUTECNT : Mute counter
bits : 7 - 12 (6 bit)

CPL : Complement bit
bits : 13 - 13 (1 bit)

COMP : Companding mode
bits : 14 - 15 (2 bit)


SAI_BFRCR

SAI BFrame configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BFRCR SAI_BFRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRL FSALL FSDEF FSPOL FSOFF

FRL : Frame length
bits : 0 - 7 (8 bit)
access : read-write

FSALL : Frame synchronization active level length
bits : 8 - 14 (7 bit)
access : read-write

FSDEF : Frame synchronization definition
bits : 16 - 16 (1 bit)
access : read-only

FSPOL : Frame synchronization polarity
bits : 17 - 17 (1 bit)
access : read-write

FSOFF : Frame synchronization offset
bits : 18 - 18 (1 bit)
access : read-write


SAI_BSLOTR

SAI BSlot register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BSLOTR SAI_BSLOTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBOFF SLOTSZ NBSLOT SLOTEN

FBOFF : First bit offset
bits : 0 - 4 (5 bit)

SLOTSZ : Slot size
bits : 6 - 7 (2 bit)

NBSLOT : Number of slots in an audio frame
bits : 8 - 11 (4 bit)

SLOTEN : Slot enable
bits : 16 - 31 (16 bit)


SAI_BIM

SAI BInterrupt mask register2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BIM SAI_BIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDRIE MUTEDETIE WCKCFGIE FREQIE CNRDYIE AFSDETIE LFSDETIE

OVRUDRIE : Overrun/underrun interrupt enable
bits : 0 - 0 (1 bit)

MUTEDETIE : Mute detection interrupt enable
bits : 1 - 1 (1 bit)

WCKCFGIE : Wrong clock configuration interrupt enable
bits : 2 - 2 (1 bit)

FREQIE : FIFO request interrupt enable
bits : 3 - 3 (1 bit)

CNRDYIE : Codec not ready interrupt enable
bits : 4 - 4 (1 bit)

AFSDETIE : Anticipated frame synchronization detection interrupt enable
bits : 5 - 5 (1 bit)

LFSDETIE : Late frame synchronization detection interrupt enable
bits : 6 - 6 (1 bit)


SAI_BSR

SAI BStatus register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_BSR SAI_BSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDR MUTEDET WCKCFG FREQ CNRDY AFSDET LFSDET FLTH

OVRUDR : Overrun / underrun
bits : 0 - 0 (1 bit)

MUTEDET : Mute detection
bits : 1 - 1 (1 bit)

WCKCFG : Wrong clock configuration flag
bits : 2 - 2 (1 bit)

FREQ : FIFO request
bits : 3 - 3 (1 bit)

CNRDY : Codec not ready
bits : 4 - 4 (1 bit)

AFSDET : Anticipated frame synchronization detection
bits : 5 - 5 (1 bit)

LFSDET : Late frame synchronization detection
bits : 6 - 6 (1 bit)

FLTH : FIFO level threshold
bits : 16 - 18 (3 bit)


SAI_BCLRFR

SAI BClear flag register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BCLRFR SAI_BCLRFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVRUDR CMUTEDET CWCKCFG CCNRDY CAFSDET CLFSDET

COVRUDR : Clear overrun / underrun
bits : 0 - 0 (1 bit)

CMUTEDET : Mute detection flag
bits : 1 - 1 (1 bit)

CWCKCFG : Clear wrong clock configuration flag
bits : 2 - 2 (1 bit)

CCNRDY : Clear codec not ready flag
bits : 4 - 4 (1 bit)

CAFSDET : Clear anticipated frame synchronization detection flag
bits : 5 - 5 (1 bit)

CLFSDET : Clear late frame synchronization detection flag
bits : 6 - 6 (1 bit)


SAI_ACR1

SAI AConfiguration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ACR1 SAI_ACR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PRTCFG DS LSBFIRST CKSTR SYNCEN MONO OUTDRIV SAIAEN DMAEN NODIV MCKDIV

MODE : Audio block mode
bits : 0 - 1 (2 bit)

PRTCFG : Protocol configuration
bits : 2 - 3 (2 bit)

DS : Data size
bits : 5 - 7 (3 bit)

LSBFIRST : Least significant bit first
bits : 8 - 8 (1 bit)

CKSTR : Clock strobing edge
bits : 9 - 9 (1 bit)

SYNCEN : Synchronization enable
bits : 10 - 11 (2 bit)

MONO : Mono mode
bits : 12 - 12 (1 bit)

OUTDRIV : Output drive
bits : 13 - 13 (1 bit)

SAIAEN : Audio block enable
bits : 16 - 16 (1 bit)

DMAEN : DMA enable
bits : 17 - 17 (1 bit)

NODIV : No divider
bits : 19 - 19 (1 bit)

MCKDIV : Master clock divider
bits : 20 - 23 (4 bit)


SAI_BDR

SAI BData register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BDR SAI_BDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


SAI_ACR2

SAI AConfiguration register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ACR2 SAI_ACR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH FFLUSH TRIS MUTE MUTEVAL MUTECNT CPL COMP

FTH : FIFO threshold
bits : 0 - 2 (3 bit)

FFLUSH : FIFO flush
bits : 3 - 3 (1 bit)

TRIS : Tristate management on data line
bits : 4 - 4 (1 bit)

MUTE : Mute
bits : 5 - 5 (1 bit)

MUTEVAL : Mute value
bits : 6 - 6 (1 bit)

MUTECNT : Mute counter
bits : 7 - 12 (6 bit)

CPL : Complement bit
bits : 13 - 13 (1 bit)

COMP : Companding mode
bits : 14 - 15 (2 bit)


SAI_AFRCR

SAI AFrame configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_AFRCR SAI_AFRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRL FSALL FSDEF FSPOL FSOFF

FRL : Frame length
bits : 0 - 7 (8 bit)
access : read-write

FSALL : Frame synchronization active level length
bits : 8 - 14 (7 bit)
access : read-write

FSDEF : Frame synchronization definition
bits : 16 - 16 (1 bit)
access : read-only

FSPOL : Frame synchronization polarity
bits : 17 - 17 (1 bit)
access : read-write

FSOFF : Frame synchronization offset
bits : 18 - 18 (1 bit)
access : read-write



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