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USB_OTG_FS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FS_HCFG

FS_HPTXSTS

FS_HCCHAR0

FS_HCINT0

FS_HCINTMSK0

FS_HCTSIZ0

FS_HCCHAR1

FS_HCINT1

FS_HCINTMSK1

FS_HCTSIZ1

HAINT

FS_HCCHAR2

FS_HCINT2

FS_HCINTMSK2

FS_HCTSIZ2

FS_HCCHAR3

FS_HCINT3

FS_HCINTMSK3

FS_HCTSIZ3

HAINTMSK

FS_HCCHAR4

FS_HCINT4

FS_HCINTMSK4

FS_HCTSIZ4

FS_HCCHAR5

FS_HCINT5

FS_HCINTMSK5

FS_HCTSIZ5

FS_HCCHAR6

FS_HCINT6

FS_HCINTMSK6

FS_HCTSIZ6

FS_HCCHAR7

FS_HCINT7

FS_HCINTMSK7

FS_HCTSIZ7

HFIR

FS_HPRT

FS_HFNUM


FS_HCFG

OTG_FS host configuration register (OTG_FS_HCFG)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCFG FS_HCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSLSPCS FSLSS

FSLSPCS : FS/LS PHY clock select
bits : 0 - 1 (2 bit)
access : read-write

FSLSS : FS- and LS-only support
bits : 2 - 2 (1 bit)
access : read-only


FS_HPTXSTS

OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HPTXSTS FS_HPTXSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFSAVL PTXQSAV PTXQTOP

PTXFSAVL : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-write

PTXQSAV : Periodic transmit request queue space available
bits : 16 - 23 (8 bit)
access : read-only

PTXQTOP : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only


FS_HCCHAR0

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR0 FS_HCCHAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT0

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT0 FS_HCINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK0

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK0 FS_HCINTMSK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ0

OTG_FS host channel-0 transfer size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ0 FS_HCTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


FS_HCCHAR1

OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR1 FS_HCCHAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT1

OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT1 FS_HCINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK1

OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK1 FS_HCINTMSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ1

OTG_FS host channel-1 transfer size register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ1 FS_HCTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HAINT

OTG_FS Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HAINT HAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINT

HAINT : Channel interrupts
bits : 0 - 15 (16 bit)


FS_HCCHAR2

OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR2 FS_HCCHAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT2

OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT2 FS_HCINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK2

OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK2 FS_HCINTMSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ2

OTG_FS host channel-2 transfer size register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ2 FS_HCTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


FS_HCCHAR3

OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR3 FS_HCCHAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT3

OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT3 FS_HCINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK3

OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK3 FS_HCINTMSK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ3

OTG_FS host channel-3 transfer size register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ3 FS_HCTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HAINTMSK

OTG_FS host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HAINTMSK HAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINTM

HAINTM : Channel interrupt mask
bits : 0 - 15 (16 bit)


FS_HCCHAR4

OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR4 FS_HCCHAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT4

OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT4 FS_HCINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK4

OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK4 FS_HCINTMSK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ4

OTG_FS host channel-x transfer size register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ4 FS_HCTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


FS_HCCHAR5

OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR5 FS_HCCHAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT5

OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT5 FS_HCINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK5

OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK5 FS_HCINTMSK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ5

OTG_FS host channel-5 transfer size register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ5 FS_HCTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


FS_HCCHAR6

OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR6 FS_HCCHAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT6

OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT6 FS_HCINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK6

OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK6 FS_HCINTMSK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ6

OTG_FS host channel-6 transfer size register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ6 FS_HCTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


FS_HCCHAR7

OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCCHAR7 FS_HCCHAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MCNT : Multicount
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


FS_HCINT7

OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINT7 FS_HCINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


FS_HCINTMSK7

OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCINTMSK7 FS_HCINTMSK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


FS_HCTSIZ7

OTG_FS host channel-7 transfer size register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HCTSIZ7 FS_HCTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


HFIR

OTG_FS Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFIR HFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRIVL

FRIVL : Frame interval
bits : 0 - 15 (16 bit)


FS_HPRT

OTG_FS host port control and status register (OTG_FS_HPRT)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FS_HPRT FS_HPRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCSTS PCDET PENA PENCHNG POCA POCCHNG PRES PSUSP PRST PLSTS PPWR PTCTL PSPD

PCSTS : Port connect status
bits : 0 - 0 (1 bit)
access : read-only

PCDET : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write

PENA : Port enable
bits : 2 - 2 (1 bit)
access : read-write

PENCHNG : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write

POCA : Port overcurrent active
bits : 4 - 4 (1 bit)
access : read-only

POCCHNG : Port overcurrent change
bits : 5 - 5 (1 bit)
access : read-write

PRES : Port resume
bits : 6 - 6 (1 bit)
access : read-write

PSUSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write

PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write

PLSTS : Port line status
bits : 10 - 11 (2 bit)
access : read-only

PPWR : Port power
bits : 12 - 12 (1 bit)
access : read-write

PTCTL : Port test control
bits : 13 - 16 (4 bit)
access : read-write

PSPD : Port speed
bits : 17 - 18 (2 bit)
access : read-only


FS_HFNUM

OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FS_HFNUM FS_HFNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNUM FTREM

FRNUM : Frame number
bits : 0 - 15 (16 bit)

FTREM : Frame time remaining
bits : 16 - 31 (16 bit)



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