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UART0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STATUS

CLKDIV

RXDATAX

RXDATA

RXDOUBLEX

RXDOUBLE

RXDATAXP

RXDOUBLEXP

TXDATAX

TXDATA

TXDOUBLEX

TXDOUBLE

FRAME

IF

IFS

IFC

IEN

IRCTRL

ROUTE

TRIGCTRL

CMD


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC LOOPBK CCEN MPM MPAB OVS CLKPOL CLKPHA MSBF CSMA TXBIL RXINV TXINV CSINV AUTOCS AUTOTRI SCMODE SCRETRANS SKIPPERRF BIT8DV ERRSDMA ERRSRX ERRSTX TXDELAY BYTESWAP

SYNC : USART Synchronous Mode
bits : 0 - 0 (1 bit)
access : read-write

LOOPBK : Loopback Enable
bits : 1 - 1 (1 bit)
access : read-write

CCEN : Collision Check Enable
bits : 2 - 2 (1 bit)
access : read-write

MPM : Multi-Processor Mode
bits : 3 - 3 (1 bit)
access : read-write

MPAB : Multi-Processor Address-Bit
bits : 4 - 4 (1 bit)
access : read-write

OVS : Oversampling
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x00000000 : X16

Regular UART mode with 16X oversampling in asynchronous mode

0x00000001 : X8

Double speed with 8X oversampling in asynchronous mode

0x00000002 : X6

6X oversampling in asynchronous mode

0x00000003 : X4

Quadruple speed with 4X oversampling in asynchronous mode

End of enumeration elements list.

CLKPOL : Clock Polarity
bits : 8 - 8 (1 bit)
access : read-write

CLKPHA : Clock Edge For Setup/Sample
bits : 9 - 9 (1 bit)
access : read-write

MSBF : Most Significant Bit First
bits : 10 - 10 (1 bit)
access : read-write

CSMA : Action On Slave-Select In Master Mode
bits : 11 - 11 (1 bit)
access : read-write

TXBIL : TX Buffer Interrupt Level
bits : 12 - 12 (1 bit)
access : read-write

RXINV : Receiver Input Invert
bits : 13 - 13 (1 bit)
access : read-write

TXINV : Transmitter output Invert
bits : 14 - 14 (1 bit)
access : read-write

CSINV : Chip Select Invert
bits : 15 - 15 (1 bit)
access : read-write

AUTOCS : Automatic Chip Select
bits : 16 - 16 (1 bit)
access : read-write

AUTOTRI : Automatic TX Tristate
bits : 17 - 17 (1 bit)
access : read-write

SCMODE : SmartCard Mode
bits : 18 - 18 (1 bit)
access : read-write

SCRETRANS : SmartCard Retransmit
bits : 19 - 19 (1 bit)
access : read-write

SKIPPERRF : Skip Parity Error Frames
bits : 20 - 20 (1 bit)
access : read-write

BIT8DV : Bit 8 Default Value
bits : 21 - 21 (1 bit)
access : read-write

ERRSDMA : Halt DMA On Error
bits : 22 - 22 (1 bit)
access : read-write

ERRSRX : Disable RX On Error
bits : 23 - 23 (1 bit)
access : read-write

ERRSTX : Disable TX On Error
bits : 24 - 24 (1 bit)
access : read-write

TXDELAY : TX Delay Transmission
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0x00000000 : NONE

Frames are transmitted immediately

0x00000001 : SINGLE

Transmission of new frames are delayed by a single baud period

0x00000002 : DOUBLE

Transmission of new frames are delayed by two baud periods

0x00000003 : TRIPLE

Transmission of new frames are delayed by three baud periods

End of enumeration elements list.

BYTESWAP : Byteswap In Double Accesses
bits : 28 - 28 (1 bit)
access : read-write


STATUS

USART Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXENS TXENS MASTER RXBLOCK TXTRI TXC TXBL RXDATAV RXFULL

RXENS : Receiver Enable Status
bits : 0 - 0 (1 bit)
access : read-only

TXENS : Transmitter Enable Status
bits : 1 - 1 (1 bit)
access : read-only

MASTER : SPI Master Mode
bits : 2 - 2 (1 bit)
access : read-only

RXBLOCK : Block Incoming Data
bits : 3 - 3 (1 bit)
access : read-only

TXTRI : Transmitter Tristated
bits : 4 - 4 (1 bit)
access : read-only

TXC : TX Complete
bits : 5 - 5 (1 bit)
access : read-only

TXBL : TX Buffer Level
bits : 6 - 6 (1 bit)
access : read-only

RXDATAV : RX Data Valid
bits : 7 - 7 (1 bit)
access : read-only

RXFULL : RX FIFO Full
bits : 8 - 8 (1 bit)
access : read-only


CLKDIV

Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Fractional Clock Divider
bits : 6 - 20 (15 bit)
access : read-write


RXDATAX

RX Buffer Data Extended Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAX RXDATAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA PERR FERR

RXDATA : RX Data
bits : 0 - 8 (9 bit)
access : read-only

PERR : Data Parity Error
bits : 14 - 14 (1 bit)
access : read-only

FERR : Data Framing Error
bits : 15 - 15 (1 bit)
access : read-only


RXDATA

RX Buffer Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATA RXDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLEX

RX Buffer Double Data Extended Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEX RXDOUBLEX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 PERR0 FERR0 RXDATA1 PERR1 FERR1

RXDATA0 : RX Data 0
bits : 0 - 8 (9 bit)
access : read-only

PERR0 : Data Parity Error 0
bits : 14 - 14 (1 bit)
access : read-only

FERR0 : Data Framing Error 0
bits : 15 - 15 (1 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 16 - 24 (9 bit)
access : read-only

PERR1 : Data Parity Error 1
bits : 30 - 30 (1 bit)
access : read-only

FERR1 : Data Framing Error 1
bits : 31 - 31 (1 bit)
access : read-only


RXDOUBLE

RX FIFO Double Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLE RXDOUBLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 RXDATA1

RXDATA0 : RX Data 0
bits : 0 - 7 (8 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 8 - 15 (8 bit)
access : read-only


RXDATAXP

RX Buffer Data Extended Peek Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAXP RXDATAXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP PERRP FERRP

RXDATAP : RX Data Peek
bits : 0 - 8 (9 bit)
access : read-only

PERRP : Data Parity Error Peek
bits : 14 - 14 (1 bit)
access : read-only

FERRP : Data Framing Error Peek
bits : 15 - 15 (1 bit)
access : read-only


RXDOUBLEXP

RX Buffer Double Data Extended Peek Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEXP RXDOUBLEXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP0 PERRP0 FERRP0 RXDATAP1 PERRP1 FERRP1

RXDATAP0 : RX Data 0 Peek
bits : 0 - 8 (9 bit)
access : read-only

PERRP0 : Data Parity Error 0 Peek
bits : 14 - 14 (1 bit)
access : read-only

FERRP0 : Data Framing Error 0 Peek
bits : 15 - 15 (1 bit)
access : read-only

RXDATAP1 : RX Data 1 Peek
bits : 16 - 24 (9 bit)
access : read-only

PERRP1 : Data Parity Error 1 Peek
bits : 30 - 30 (1 bit)
access : read-only

FERRP1 : Data Framing Error 1 Peek
bits : 31 - 31 (1 bit)
access : read-only


TXDATAX

TX Buffer Data Extended Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDATAX TXDATAX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATAX UBRXAT TXTRIAT TXBREAK TXDISAT RXENAT

TXDATAX : TX Data
bits : 0 - 8 (9 bit)
access : write-only

UBRXAT : Unblock RX After Transmission
bits : 11 - 11 (1 bit)
access : write-only

TXTRIAT : Set TXTRI After Transmission
bits : 12 - 12 (1 bit)
access : write-only

TXBREAK : Transmit Data As Break
bits : 13 - 13 (1 bit)
access : write-only

TXDISAT : Clear TXEN After Transmission
bits : 14 - 14 (1 bit)
access : write-only

RXENAT : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : write-only


TXDATA

TX Buffer Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDATA TXDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7 (8 bit)
access : write-only


TXDOUBLEX

TX Buffer Double Data Extended Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLEX TXDOUBLEX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 UBRXAT0 TXTRIAT0 TXBREAK0 TXDISAT0 RXENAT0 TXDATA1 UBRXAT1 TXTRIAT1 TXBREAK1 TXDISAT1 RXENAT1

TXDATA0 : TX Data
bits : 0 - 8 (9 bit)
access : write-only

UBRXAT0 : Unblock RX After Transmission
bits : 11 - 11 (1 bit)
access : write-only

TXTRIAT0 : Set TXTRI After Transmission
bits : 12 - 12 (1 bit)
access : write-only

TXBREAK0 : Transmit Data As Break
bits : 13 - 13 (1 bit)
access : write-only

TXDISAT0 : Clear TXEN After Transmission
bits : 14 - 14 (1 bit)
access : write-only

RXENAT0 : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : write-only

TXDATA1 : TX Data
bits : 16 - 24 (9 bit)
access : write-only

UBRXAT1 : Unblock RX After Transmission
bits : 27 - 27 (1 bit)
access : write-only

TXTRIAT1 : Set TXTRI After Transmission
bits : 28 - 28 (1 bit)
access : write-only

TXBREAK1 : Transmit Data As Break
bits : 29 - 29 (1 bit)
access : write-only

TXDISAT1 : Clear TXEN After Transmission
bits : 30 - 30 (1 bit)
access : write-only

RXENAT1 : Enable RX After Transmission
bits : 31 - 31 (1 bit)
access : write-only


TXDOUBLE

TX Buffer Double Data Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLE TXDOUBLE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 TXDATA1

TXDATA0 : TX Data
bits : 0 - 7 (8 bit)
access : write-only

TXDATA1 : TX Data
bits : 8 - 15 (8 bit)
access : write-only


FRAME

USART Frame Format Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAME FRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABITS PARITY STOPBITS

DATABITS : Data-Bit Mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000001 : FOUR

Each frame contains 4 data bits

0x00000002 : FIVE

Each frame contains 5 data bits

0x00000003 : SIX

Each frame contains 6 data bits

0x00000004 : SEVEN

Each frame contains 7 data bits

0x00000005 : EIGHT

Each frame contains 8 data bits

0x00000006 : NINE

Each frame contains 9 data bits

0x00000007 : TEN

Each frame contains 10 data bits

0x00000008 : ELEVEN

Each frame contains 11 data bits

0x00000009 : TWELVE

Each frame contains 12 data bits

0x0000000A : THIRTEEN

Each frame contains 13 data bits

0x0000000B : FOURTEEN

Each frame contains 14 data bits

0x0000000C : FIFTEEN

Each frame contains 15 data bits

0x0000000D : SIXTEEN

Each frame contains 16 data bits

End of enumeration elements list.

PARITY : Parity-Bit Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : NONE

Parity bits are not used

0x00000002 : EVEN

Even parity are used. Parity bits are automatically generated and checked by hardware.

0x00000003 : ODD

Odd parity is used. Parity bits are automatically generated and checked by hardware.

End of enumeration elements list.

STOPBITS : Stop-Bit Mode
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x00000000 : HALF

The transmitter generates a half stop bit. Stop-bits are not verified by receiver

0x00000001 : ONE

One stop bit is generated and verified

0x00000002 : ONEANDAHALF

The transmitter generates one and a half stop bit. The receiver verifies the first stop bit

0x00000003 : TWO

The transmitter generates two stop bits. The receiver checks the first stop-bit only

End of enumeration elements list.


IF

Interrupt Flag Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF

TXC : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

TXBL : TX Buffer Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

RXDATAV : RX Data Valid Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

RXFULL : RX Buffer Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

RXOF : RX Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

RXUF : RX Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only

TXOF : TX Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only

TXUF : TX Underflow Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

PERR : Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only

FERR : Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only

MPAF : Multi-Processor Address Frame Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-only

SSM : Slave-Select In Master Mode Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only

CCF : Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF

TXC : Set TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

RXFULL : Set RX Buffer Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

RXOF : Set RX Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

RXUF : Set RX Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

TXOF : Set TX Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

TXUF : Set TX Underflow Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

PERR : Set Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

FERR : Set Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

MPAF : Set Multi-Processor Address Frame Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

SSM : Set Slave-Select in Master mode Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

CCF : Set Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF

TXC : Clear TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

RXFULL : Clear RX Buffer Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

RXOF : Clear RX Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

RXUF : Clear RX Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

TXOF : Clear TX Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

TXUF : Clear TX Underflow Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

PERR : Clear Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

FERR : Clear Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

MPAF : Clear Multi-Processor Address Frame Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

SSM : Clear Slave-Select In Master Mode Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

CCF : Clear Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF

TXC : TX Complete Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

TXBL : TX Buffer Level Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

RXDATAV : RX Data Valid Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

RXFULL : RX Buffer Full Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

RXOF : RX Overflow Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

RXUF : RX Underflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

TXOF : TX Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

TXUF : TX Underflow Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

PERR : Parity Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

FERR : Framing Error Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

MPAF : Multi-Processor Address Frame Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

SSM : Slave-Select In Master Mode Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

CCF : Collision Check Fail Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write


IRCTRL

IrDA Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRCTRL IRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IREN IRPW IRFILT IRPRSSEL IRPRSEN

IREN : Enable IrDA Module
bits : 0 - 0 (1 bit)
access : read-write

IRPW : IrDA TX Pulse Width
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x00000000 : ONE

IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1

0x00000001 : TWO

IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1

0x00000002 : THREE

IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1

0x00000003 : FOUR

IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1

End of enumeration elements list.

IRFILT : IrDA RX Filter
bits : 3 - 3 (1 bit)
access : read-write

IRPRSSEL : IrDA PRS Channel Select
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

End of enumeration elements list.

IRPRSEN : IrDA PRS Channel Enable
bits : 7 - 7 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPEN TXPEN CSPEN CLKPEN LOCATION

RXPEN : RX Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

TXPEN : TX Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CSPEN : CS Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CLKPEN : CLK Pin Enable
bits : 3 - 3 (1 bit)
access : read-write

LOCATION : I/O Location
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.


TRIGCTRL

USART Trigger Control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIGCTRL TRIGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEL RXTEN TXTEN

TSEL : Trigger PRS Channel Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

End of enumeration elements list.

RXTEN : Receive Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write

TXTEN : Transmit Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write


CMD

Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN RXDIS TXEN TXDIS MASTEREN MASTERDIS RXBLOCKEN RXBLOCKDIS TXTRIEN TXTRIDIS CLEARTX CLEARRX

RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 3 - 3 (1 bit)
access : write-only

MASTEREN : Master Enable
bits : 4 - 4 (1 bit)
access : write-only

MASTERDIS : Master Disable
bits : 5 - 5 (1 bit)
access : write-only

RXBLOCKEN : Receiver Block Enable
bits : 6 - 6 (1 bit)
access : write-only

RXBLOCKDIS : Receiver Block Disable
bits : 7 - 7 (1 bit)
access : write-only

TXTRIEN : Transmitter Tristate Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTRIDIS : Transmitter Tristate Disable
bits : 9 - 9 (1 bit)
access : write-only

CLEARTX : Clear TX
bits : 10 - 10 (1 bit)
access : write-only

CLEARRX : Clear RX
bits : 11 - 11 (1 bit)
access : write-only



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