\n

PCNT1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TOP

TOPB

IF

IFS

IFC

IEN

ROUTE

FREEZE

SYNCBUSY

CMD

STATUS

CNT


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CNTDIR EDGE FILT RSTEN

MODE : Mode Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

The module is disabled.

0x00000001 : OVSSINGLE

Single input LFACLK oversampling mode (available in EM0-EM2).

0x00000002 : EXTCLKSINGLE

Externally clocked single input counter mode (available in EM0-EM3).

0x00000003 : EXTCLKQUAD

Externally clocked quadrature decoder mode (available in EM0-EM3).

End of enumeration elements list.

CNTDIR : Non-Quadrature Mode Counter Direction Control
bits : 2 - 2 (1 bit)
access : read-write

EDGE : Edge Select
bits : 3 - 3 (1 bit)
access : read-write

FILT : Enable Digital Pulse Width Filter
bits : 4 - 4 (1 bit)
access : read-write

RSTEN : Enable PCNT Clock Domain Reset
bits : 5 - 5 (1 bit)
access : read-write


TOP

Top Value Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TOP TOP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP

TOP : Counter Top Value
bits : 0 - 15 (16 bit)
access : read-only


TOPB

Top Value Buffer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOPB TOPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOPB

TOPB : Counter Top Buffer
bits : 0 - 15 (16 bit)
access : read-write


IF

Interrupt Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG

UF : Underflow Interrupt Read Flag
bits : 0 - 0 (1 bit)
access : read-only

OF : Overflow Interrupt Read Flag
bits : 1 - 1 (1 bit)
access : read-only

DIRCNG : Direction Change Detect Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG

UF : Underflow interrupt set
bits : 0 - 0 (1 bit)
access : write-only

OF : Overflow Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

DIRCNG : Direction Change Detect Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG

UF : Underflow Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

OF : Overflow Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

DIRCNG : Direction Change Detect Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG

UF : Underflow Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

OF : Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

DIRCNG : Direction Change Detect Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCATION

LOCATION : I/O Location
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.


FREEZE

Freeze Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREEZE FREEZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE

REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write


SYNCBUSY

Synchronization Busy Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL CMD TOPB

CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only

CMD : CMD Register Busy
bits : 1 - 1 (1 bit)
access : read-only

TOPB : TOPB Register Busy
bits : 2 - 2 (1 bit)
access : read-only


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCNTIM LTOPBIM

LCNTIM : Load CNT Immediately
bits : 0 - 0 (1 bit)
access : write-only

LTOPBIM : Load TOPB Immediately
bits : 1 - 1 (1 bit)
access : write-only


STATUS

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIR

DIR : Current Counter Direction
bits : 0 - 0 (1 bit)
access : read-only


CNT

Counter Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-only



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