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LCD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STATUS

AREGA

AREGB

IF

IFS

IFC

IEN

DISPCTRL

SEGD0L

SEGD1L

SEGD2L

SEGD3L

SEGD0H

SEGD1H

SEGD2H

SEGD3H

FREEZE

SYNCBUSY

SEGEN

BACTRL


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UDCTRL

EN : LCD Enable
bits : 0 - 0 (1 bit)
access : read-write

UDCTRL : Update Data Control
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x00000000 : REGULAR

The data transfer is controlled by SW. Transfer is performed as soon as possible

0x00000001 : FCEVENT

The data transfer is done at the next event triggered by the Frame Counter

0x00000002 : FRAMESTART

The data transfer is done continuously at every LCD frame start

End of enumeration elements list.


STATUS

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTATE BLINK

ASTATE : Current Animation State
bits : 0 - 3 (4 bit)
access : read-only

BLINK : Blink State
bits : 8 - 8 (1 bit)
access : read-only


AREGA

Animation Register A
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREGA AREGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREGA

AREGA : Animation Register A Data
bits : 0 - 7 (8 bit)
access : read-write


AREGB

Animation Register B
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREGB AREGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREGB

AREGB : Animation Register B Data
bits : 0 - 7 (8 bit)
access : read-write


IF

Interrupt Flag Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write


DISPCTRL

Display Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISPCTRL DISPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX BIAS WAVE CONLEV CONCONF VLCDSEL VBLEV

MUX : Mux Configuration
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : STATIC

Static

0x00000001 : DUPLEX

Duplex

0x00000002 : TRIPLEX

Triplex

0x00000003 : QUADRUPLEX

Quadruplex

End of enumeration elements list.

BIAS : Bias Configuration
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x00000000 : STATIC

Static

0x00000001 : ONEHALF

1/2 Bias

0x00000002 : ONETHIRD

1/3 Bias

End of enumeration elements list.

WAVE : Waveform Selection
bits : 4 - 4 (1 bit)
access : read-write

CONLEV : Contrast Level
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x00000000 : MIN

Minimum contrast

0x0000001F : MAX

Maximum contrast

End of enumeration elements list.

CONCONF : Contrast Configuration
bits : 15 - 15 (1 bit)
access : read-write

VLCDSEL : VLCD Selection
bits : 16 - 16 (1 bit)
access : read-write

VBLEV : Voltage Boost Level
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

0x00000000 : LEVEL0

Minimum boost level

0x00000001 : LEVEL1


0x00000002 : LEVEL2


0x00000003 : LEVEL3


0x00000004 : LEVEL4


0x00000005 : LEVEL5


0x00000006 : LEVEL6


0x00000007 : LEVEL7

Maximum boost level

End of enumeration elements list.


SEGD0L

Segment Data Low Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD0L SEGD0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD0L

SEGD0L : COM0 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD1L

Segment Data Low Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD1L SEGD1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD1L

SEGD1L : COM1 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD2L

Segment Data Low Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD2L SEGD2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD2L

SEGD2L : COM2 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD3L

Segment Data Low Register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD3L SEGD3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD3L

SEGD3L : COM3 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD0H

Segment Data High Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD0H SEGD0H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD0H

SEGD0H : COM0 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD1H

Segment Data High Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD1H SEGD1H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD1H

SEGD1H : COM1 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD2H

Segment Data High Register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD2H SEGD2H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD2H

SEGD2H : COM2 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD3H

Segment Data High Register 3
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD3H SEGD3H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD3H

SEGD3H : COM3 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


FREEZE

Freeze Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREEZE FREEZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE

REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write


SYNCBUSY

Synchronization Busy Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL BACTRL AREGA AREGB SEGD0L SEGD1L SEGD2L SEGD3L SEGD0H SEGD1H SEGD2H SEGD3H

CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only

BACTRL : BACTRL Register Busy
bits : 1 - 1 (1 bit)
access : read-only

AREGA : AREGA Register Busy
bits : 2 - 2 (1 bit)
access : read-only

AREGB : AREGB Register Busy
bits : 3 - 3 (1 bit)
access : read-only

SEGD0L : SEGD0L Register Busy
bits : 4 - 4 (1 bit)
access : read-only

SEGD1L : SEGD1L Register Busy
bits : 5 - 5 (1 bit)
access : read-only

SEGD2L : SEGD2L Register Busy
bits : 6 - 6 (1 bit)
access : read-only

SEGD3L : SEGD3L Register Busy
bits : 7 - 7 (1 bit)
access : read-only

SEGD0H : SEGD0H Register Busy
bits : 8 - 8 (1 bit)
access : read-only

SEGD1H : SEGD1H Register Busy
bits : 9 - 9 (1 bit)
access : read-only

SEGD2H : SEGD2H Register Busy
bits : 10 - 10 (1 bit)
access : read-only

SEGD3H : SEGD3H Register Busy
bits : 11 - 11 (1 bit)
access : read-only


SEGEN

Segment Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGEN SEGEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGEN

SEGEN : Segment Enable
bits : 0 - 9 (10 bit)
access : read-write


BACTRL

Blink and Animation Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BACTRL BACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLINKEN BLANK AEN AREGASC AREGBSC ALOGSEL FCEN FCPRESC FCTOP

BLINKEN : Blink Enable
bits : 0 - 0 (1 bit)
access : read-write

BLANK : Blank Display
bits : 1 - 1 (1 bit)
access : read-write

AEN : Animation Enable
bits : 2 - 2 (1 bit)
access : read-write

AREGASC : Animate Register A Shift Control
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x00000000 : NOSHIFT

No Shift operation on Animation Register A

0x00000001 : SHIFTLEFT

Animation Register A is shifted left

0x00000002 : SHIFTRIGHT

Animation Register A is shifted right

End of enumeration elements list.

AREGBSC : Animate Register B Shift Control
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x00000000 : NOSHIFT

No Shift operation on Animation Register B

0x00000001 : SHIFTLEFT

Animation Register B is shifted left

0x00000002 : SHIFTRIGHT

Animation Register B is shifted right

End of enumeration elements list.

ALOGSEL : Animate Logic Function Select
bits : 7 - 7 (1 bit)
access : read-write

FCEN : Frame Counter Enable
bits : 8 - 8 (1 bit)
access : read-write

FCPRESC : Frame Counter Prescaler
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

CLKFC = CLKFRAME / 1

0x00000001 : DIV2

CLKFC = CLKFRAME / 2

0x00000002 : DIV4

CLKFC = CLKFRAME / 4

0x00000003 : DIV8

CLKFC = CLKFRAME / 8

End of enumeration elements list.

FCTOP : Frame Counter Top Value
bits : 18 - 23 (6 bit)
access : read-write



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