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EBI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

POLARITY

ADDRTIMING1

RDTIMING1

WRTIMING1

POLARITY1

ADDRTIMING2

RDTIMING2

WRTIMING2

POLARITY2

ADDRTIMING3

RDTIMING3

ADDRTIMING

WRTIMING3

POLARITY3

PAGECTRL

NANDCTRL

CMD

STATUS

ECCPARITY

TFTCTRL

TFTSTATUS

TFTCOLORFORMAT

TFTFRAMEBASE

TFTSTRIDE

TFTSIZE

TFTHPORCH

TFTVPORCH

RDTIMING

TFTTIMING

TFTPOLARITY

TFTDD

TFTALPHA

TFTPIXEL0

TFTPIXEL1

TFTPIXEL

TFTMASK

IF

IFS

IFC

IEN

ROUTEPEN

ROUTELOC0

ROUTELOC1

WRTIMING


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE MODE1 MODE2 MODE3 BANK0EN BANK1EN BANK2EN BANK3EN NOIDLE NOIDLE1 NOIDLE2 NOIDLE3 ARDYEN ARDYTODIS ARDY1EN ARDYTO1DIS ARDY2EN ARDYTO2DIS ARDY3EN ARDYTO3DIS BL BL1 BL2 BL3 ITS ALTMAP

MODE : Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : D8A8

EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled.

0x00000001 : D16A16ALE

EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000002 : D8A24ALE

EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000003 : D16

EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled.

End of enumeration elements list.

MODE1 : Mode 1
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x00000000 : D8A8

EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled.

0x00000001 : D16A16ALE

EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000002 : D8A24ALE

EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000003 : D16

EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled.

End of enumeration elements list.

MODE2 : Mode 2
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : D8A8

EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled.

0x00000001 : D16A16ALE

EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000002 : D8A24ALE

EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000003 : D16

EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled.

End of enumeration elements list.

MODE3 : Mode 3
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x00000000 : D8A8

EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled.

0x00000001 : D16A16ALE

EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000002 : D8A24ALE

EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled.

0x00000003 : D16

EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled.

End of enumeration elements list.

BANK0EN : Bank 0 Enable
bits : 8 - 8 (1 bit)
access : read-write

BANK1EN : Bank 1 Enable
bits : 9 - 9 (1 bit)
access : read-write

BANK2EN : Bank 2 Enable
bits : 10 - 10 (1 bit)
access : read-write

BANK3EN : Bank 3 Enable
bits : 11 - 11 (1 bit)
access : read-write

NOIDLE : No Idle Cycle Insertion on Bank 0
bits : 12 - 12 (1 bit)
access : read-write

NOIDLE1 : No Idle Cycle Insertion on Bank 1
bits : 13 - 13 (1 bit)
access : read-write

NOIDLE2 : No Idle Cycle Insertion on Bank 2
bits : 14 - 14 (1 bit)
access : read-write

NOIDLE3 : No Idle Cycle Insertion on Bank 3
bits : 15 - 15 (1 bit)
access : read-write

ARDYEN : ARDY Enable
bits : 16 - 16 (1 bit)
access : read-write

ARDYTODIS : ARDY Timeout Disable
bits : 17 - 17 (1 bit)
access : read-write

ARDY1EN : ARDY Enable for Bank 1
bits : 18 - 18 (1 bit)
access : read-write

ARDYTO1DIS : ARDY Timeout Disable for Bank 1
bits : 19 - 19 (1 bit)
access : read-write

ARDY2EN : ARDY Enable for Bank 2
bits : 20 - 20 (1 bit)
access : read-write

ARDYTO2DIS : ARDY Timeout Disable for Bank 2
bits : 21 - 21 (1 bit)
access : read-write

ARDY3EN : ARDY Enable for Bank 3
bits : 22 - 22 (1 bit)
access : read-write

ARDYTO3DIS : ARDY Timeout Disable for Bank 3
bits : 23 - 23 (1 bit)
access : read-write

BL : Byte Lane Enable for Bank 0
bits : 24 - 24 (1 bit)
access : read-write

BL1 : Byte Lane Enable for Bank 1
bits : 25 - 25 (1 bit)
access : read-write

BL2 : Byte Lane Enable for Bank 2
bits : 26 - 26 (1 bit)
access : read-write

BL3 : Byte Lane Enable for Bank 3
bits : 27 - 27 (1 bit)
access : read-write

ITS : Individual Timing Set, Line Polarity and Mode Definition Enable
bits : 30 - 30 (1 bit)
access : read-write

ALTMAP : Alternative Address Map Enable
bits : 31 - 31 (1 bit)
access : read-write


POLARITY

Polarity Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POLARITY POLARITY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPOL REPOL WEPOL ALEPOL ARDYPOL BLPOL

CSPOL : Chip Select Polarity
bits : 0 - 0 (1 bit)
access : read-write

REPOL : Read Enable Polarity
bits : 1 - 1 (1 bit)
access : read-write

WEPOL : Write Enable Polarity
bits : 2 - 2 (1 bit)
access : read-write

ALEPOL : Address Latch Polarity
bits : 3 - 3 (1 bit)
access : read-write

ARDYPOL : ARDY Polarity
bits : 4 - 4 (1 bit)
access : read-write

BLPOL : BL Polarity
bits : 5 - 5 (1 bit)
access : read-write


ADDRTIMING1

Address Timing Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRTIMING1 ADDRTIMING1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRSETUP ADDRHOLD HALFALE

ADDRSETUP : Address Setup Time
bits : 0 - 2 (3 bit)
access : read-write

ADDRHOLD : Address Hold Time
bits : 8 - 10 (3 bit)
access : read-write

HALFALE : Half Cycle ALE Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write


RDTIMING1

Read Timing Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDTIMING1 RDTIMING1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDSETUP RDSTRB RDHOLD HALFRE PREFETCH PAGEMODE

RDSETUP : Read Setup Time
bits : 0 - 2 (3 bit)
access : read-write

RDSTRB : Read Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

RDHOLD : Read Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFRE : Half Cycle REn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

PREFETCH : Prefetch Enable
bits : 29 - 29 (1 bit)
access : read-write

PAGEMODE : Page Mode Access Enable
bits : 30 - 30 (1 bit)
access : read-write


WRTIMING1

Write Timing Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRTIMING1 WRTIMING1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRSETUP WRSTRB WRHOLD HALFWE WBUFDIS

WRSETUP : Write Setup Time
bits : 0 - 2 (3 bit)
access : read-write

WRSTRB : Write Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

WRHOLD : Write Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFWE : Half Cycle WEn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

WBUFDIS : Write Buffer Disable
bits : 29 - 29 (1 bit)
access : read-write


POLARITY1

Polarity Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POLARITY1 POLARITY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPOL REPOL WEPOL ALEPOL ARDYPOL BLPOL

CSPOL : Chip Select Polarity
bits : 0 - 0 (1 bit)
access : read-write

REPOL : Read Enable Polarity
bits : 1 - 1 (1 bit)
access : read-write

WEPOL : Write Enable Polarity
bits : 2 - 2 (1 bit)
access : read-write

ALEPOL : Address Latch Polarity
bits : 3 - 3 (1 bit)
access : read-write

ARDYPOL : ARDY Polarity
bits : 4 - 4 (1 bit)
access : read-write

BLPOL : BL Polarity
bits : 5 - 5 (1 bit)
access : read-write


ADDRTIMING2

Address Timing Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRTIMING2 ADDRTIMING2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRSETUP ADDRHOLD HALFALE

ADDRSETUP : Address Setup Time
bits : 0 - 2 (3 bit)
access : read-write

ADDRHOLD : Address Hold Time
bits : 8 - 10 (3 bit)
access : read-write

HALFALE : Half Cycle ALE Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write


RDTIMING2

Read Timing Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDTIMING2 RDTIMING2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDSETUP RDSTRB RDHOLD HALFRE PREFETCH PAGEMODE

RDSETUP : Read Setup Time
bits : 0 - 2 (3 bit)
access : read-write

RDSTRB : Read Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

RDHOLD : Read Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFRE : Half Cycle REn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

PREFETCH : Prefetch Enable
bits : 29 - 29 (1 bit)
access : read-write

PAGEMODE : Page Mode Access Enable
bits : 30 - 30 (1 bit)
access : read-write


WRTIMING2

Write Timing Register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRTIMING2 WRTIMING2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRSETUP WRSTRB WRHOLD HALFWE WBUFDIS

WRSETUP : Write Setup Time
bits : 0 - 2 (3 bit)
access : read-write

WRSTRB : Write Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

WRHOLD : Write Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFWE : Half Cycle WEn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

WBUFDIS : Write Buffer Disable
bits : 29 - 29 (1 bit)
access : read-write


POLARITY2

Polarity Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POLARITY2 POLARITY2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPOL REPOL WEPOL ALEPOL ARDYPOL BLPOL

CSPOL : Chip Select Polarity
bits : 0 - 0 (1 bit)
access : read-write

REPOL : Read Enable Polarity
bits : 1 - 1 (1 bit)
access : read-write

WEPOL : Write Enable Polarity
bits : 2 - 2 (1 bit)
access : read-write

ALEPOL : Address Latch Polarity
bits : 3 - 3 (1 bit)
access : read-write

ARDYPOL : ARDY Polarity
bits : 4 - 4 (1 bit)
access : read-write

BLPOL : BL Polarity
bits : 5 - 5 (1 bit)
access : read-write


ADDRTIMING3

Address Timing Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRTIMING3 ADDRTIMING3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRSETUP ADDRHOLD HALFALE

ADDRSETUP : Address Setup Time
bits : 0 - 2 (3 bit)
access : read-write

ADDRHOLD : Address Hold Time
bits : 8 - 10 (3 bit)
access : read-write

HALFALE : Half Cycle ALE Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write


RDTIMING3

Read Timing Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDTIMING3 RDTIMING3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDSETUP RDSTRB RDHOLD HALFRE PREFETCH PAGEMODE

RDSETUP : Read Setup Time
bits : 0 - 2 (3 bit)
access : read-write

RDSTRB : Read Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

RDHOLD : Read Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFRE : Half Cycle REn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

PREFETCH : Prefetch Enable
bits : 29 - 29 (1 bit)
access : read-write

PAGEMODE : Page Mode Access Enable
bits : 30 - 30 (1 bit)
access : read-write


ADDRTIMING

Address Timing Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRTIMING ADDRTIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRSETUP ADDRHOLD HALFALE

ADDRSETUP : Address Setup Time
bits : 0 - 2 (3 bit)
access : read-write

ADDRHOLD : Address Hold Time
bits : 8 - 10 (3 bit)
access : read-write

HALFALE : Half Cycle ALE Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write


WRTIMING3

Write Timing Register 3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRTIMING3 WRTIMING3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRSETUP WRSTRB WRHOLD HALFWE WBUFDIS

WRSETUP : Write Setup Time
bits : 0 - 2 (3 bit)
access : read-write

WRSTRB : Write Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

WRHOLD : Write Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFWE : Half Cycle WEn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

WBUFDIS : Write Buffer Disable
bits : 29 - 29 (1 bit)
access : read-write


POLARITY3

Polarity Register 3
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POLARITY3 POLARITY3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPOL REPOL WEPOL ALEPOL ARDYPOL BLPOL

CSPOL : Chip Select Polarity
bits : 0 - 0 (1 bit)
access : read-write

REPOL : Read Enable Polarity
bits : 1 - 1 (1 bit)
access : read-write

WEPOL : Write Enable Polarity
bits : 2 - 2 (1 bit)
access : read-write

ALEPOL : Address Latch Polarity
bits : 3 - 3 (1 bit)
access : read-write

ARDYPOL : ARDY Polarity
bits : 4 - 4 (1 bit)
access : read-write

BLPOL : BL Polarity
bits : 5 - 5 (1 bit)
access : read-write


PAGECTRL

Page Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAGECTRL PAGECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGELEN INCHIT RDPA KEEPOPEN

PAGELEN : Page Length
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : MEMBER4

4 members in a page.

0x00000001 : MEMBER8

8 members in a page.

0x00000002 : MEMBER16

16 members in a page.

0x00000003 : MEMBER32

32 members in a page.

End of enumeration elements list.

INCHIT : Intrapage Hit Only on Incremental Addresses
bits : 4 - 4 (1 bit)
access : read-write

RDPA : Page Read Access Time
bits : 8 - 11 (4 bit)
access : read-write

KEEPOPEN : Maximum Page Open Time
bits : 20 - 26 (7 bit)
access : read-write


NANDCTRL

NAND Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NANDCTRL NANDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN BANKSEL

EN : NAND Flash Control Enable
bits : 0 - 0 (1 bit)
access : read-write

BANKSEL : NAND Flash Bank
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : BANK0

Memory bank 0 is connected to a NAND Flash device.

0x00000001 : BANK1

Memory bank 1 is connected to a NAND Flash device.

0x00000002 : BANK2

Memory bank 2 is connected to a NAND Flash device.

0x00000003 : BANK3

Memory bank 3 is connected to a NAND Flash device.

End of enumeration elements list.


CMD

Command Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCSTART ECCSTOP ECCCLEAR

ECCSTART : Error Correction Code Generation Start
bits : 0 - 0 (1 bit)
access : write-only

ECCSTOP : Error Correction Code Generation Stop
bits : 1 - 1 (1 bit)
access : write-only

ECCCLEAR : Error Correction Code Clear
bits : 2 - 2 (1 bit)
access : write-only


STATUS

Status Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBACT ECCACT TFTPIXEL0EMPTY TFTPIXEL1EMPTY TFTPIXELFULL DDACT TFTDDEMPTY

AHBACT : EBI Busy With AHB Transaction
bits : 0 - 0 (1 bit)
access : read-only

ECCACT : EBI ECC Generation Active
bits : 4 - 4 (1 bit)
access : read-only

TFTPIXEL0EMPTY : EBI_TFTPIXEL0 is Empty
bits : 8 - 8 (1 bit)
access : read-only

TFTPIXEL1EMPTY : EBI_TFTPIXEL1 is Empty
bits : 9 - 9 (1 bit)
access : read-only

TFTPIXELFULL : EBI_TFTPIXEL0 is Full
bits : 10 - 10 (1 bit)
access : read-only

DDACT : EBI Busy With Direct Drive Transactions
bits : 12 - 12 (1 bit)
access : read-only

TFTDDEMPTY : EBI_TFTDD Register is Empty
bits : 13 - 13 (1 bit)
access : read-only


ECCPARITY

ECC Parity Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCPARITY ECCPARITY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCPARITY

ECCPARITY : ECC Parity Data
bits : 0 - 31 (32 bit)
access : read-only


TFTCTRL

TFT Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTCTRL TFTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DD MASKBLEND SHIFTDCLKEN FBCTRIG INTERLEAVE COLOR1SRC WIDTH ALIASBANKEN BANKSEL ALIASBANK

DD : TFT Direct Drive Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Direct Drive is disabled.

0x00000001 : INTERNAL

Direct Drive from internal memory enabled and started.

0x00000002 : EXTERNAL

Direct Drive from external memory enabled and started.

End of enumeration elements list.

MASKBLEND : TFT Mask and Blend Mode
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Masking and Blending are disabled.

0x00000001 : IMASK

Internal Masking is enabled.

0x00000002 : IALPHA

Internal Alpha Blending is enabled.

0x00000003 : IMASKALPHA

Internal Masking and Alpha Blending are enabled.

0x00000004 : EFBMASK

External Frame Buffer Masking is enabled.

0x00000005 : EFBALPHA

External Frame Buffer Alpha Blending is enabled.

0x00000006 : EFBMASKALPHA

External Frame Buffer Masking and Alpha Blending are enabled.

0x00000007 : IFBMASK

Internal Frame Buffer Masking is enabled.

0x00000008 : IFBALPHA

Internal Frame Buffer Alpha Blending is enabled.

0x00000009 : IFBMASKALPHA

Internal Frame Buffer Masking and Alpha Blending are enabled.

End of enumeration elements list.

SHIFTDCLKEN : TFT EBI_DCLK Shift Enable
bits : 8 - 8 (1 bit)
access : read-write

FBCTRIG : TFT Frame Base Copy Trigger
bits : 9 - 9 (1 bit)
access : read-write

INTERLEAVE : Interleave Mode
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0x00000000 : UNLIMITED

Allow unlimited interleaved EBI accesses per EBI_DCLK period. This can cause jitter on the EBI_DCLK

0x00000001 : ONEPERDCLK

Allow 1 interleaved EBI access per EBI_DCLK period.

0x00000002 : PORCH

Only allow EBI accesses during TFT porches.

End of enumeration elements list.

COLOR1SRC : Masking/Alpha Blending Color1 Source
bits : 12 - 12 (1 bit)
access : read-write

WIDTH : TFT Transaction Width
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x00000000 : BYTE

TFT Data is 8 bit wide.

0x00000001 : HALFWORD

TFT Data is 16 bit wide.

End of enumeration elements list.

ALIASBANKEN : Alias to Graphics Bank Enable
bits : 19 - 19 (1 bit)
access : read-write

BANKSEL : Graphics Bank
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : BANK0

Memory bank 0 is used for Direct Drive, Masking, and Alpha Blending.

0x00000001 : BANK1

Memory bank 1 is used for Direct Drive, Masking, and Alpha Blending.

0x00000002 : BANK2

Memory bank 2 is used for Direct Drive, Masking, and Alpha Blending.

0x00000003 : BANK3

Memory bank 3 is used for Direct Drive, Masking, and Alpha Blending.

End of enumeration elements list.

ALIASBANK : Graphic Bank Select Aliasing
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x00000000 : ALIASBANK0

Graphic Bank Select is alias to Bank Select 0

0x00000001 : ALIASBANK1

Graphic Bank Select is alias to Bank Select 1

0x00000002 : ALIASBANK2

Graphic Bank Select is alias to Bank Select 2

0x00000003 : ALIASBANK3

Graphic Bank Select is alias to Bank Select 3

End of enumeration elements list.


TFTSTATUS

TFT Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TFTSTATUS TFTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCNT VCNT

HCNT : Horizontal Count
bits : 0 - 10 (11 bit)
access : read-only

VCNT : Vertical Count
bits : 16 - 30 (15 bit)
access : read-only


TFTCOLORFORMAT

Color Format Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTCOLORFORMAT TFTCOLORFORMAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIXEL0FORMAT PIXEL1FORMAT

PIXEL0FORMAT : Sprite Pixel Color Format
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : ARGB0555

ARGB data is 0555

0x00000001 : ARGB0565

ARGB data is 0565

0x00000002 : ARGB0666

ARGB data is 0666

0x00000003 : ARGB0888

ARGB data is 0888

0x00000004 : ARGB5555

ARGB data is 5555

0x00000005 : ARGB6565

ARGB data is 6565

0x00000006 : ARGB6666

ARGB data is 6666

0x00000007 : ARGB8888

ARGB data is 8888

End of enumeration elements list.

PIXEL1FORMAT : Source and Destination Pixel Color Format
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : RGB555

RGB data is 555

0x00000001 : RGB565

RGB data is 565

0x00000002 : RGB666

RGB data is 666

0x00000003 : RGB888

RGB data is 888

End of enumeration elements list.


TFTFRAMEBASE

TFT Frame Base Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTFRAMEBASE TFTFRAMEBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAMEBASE

FRAMEBASE : Frame Base Address
bits : 0 - 27 (28 bit)
access : read-write


TFTSTRIDE

TFT Stride Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTSTRIDE TFTSTRIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTRIDE

HSTRIDE : Horizontal Stride
bits : 0 - 11 (12 bit)
access : read-write


TFTSIZE

TFT Size Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTSIZE TFTSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSZ VSZ

HSZ : Horizontal Size (excluding Porches)
bits : 0 - 9 (10 bit)
access : read-write

VSZ : Vertical Size (excluding Porches)
bits : 16 - 25 (10 bit)
access : read-write


TFTHPORCH

TFT Horizontal Porch Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTHPORCH TFTHPORCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSYNC HFPORCH HBPORCH HSYNCSTART

HSYNC : Horizontal Synchronization Pulse Width
bits : 0 - 6 (7 bit)
access : read-write

HFPORCH : Horizontal Front Porch Size
bits : 8 - 15 (8 bit)
access : read-write

HBPORCH : Horizontal Back Porch Size
bits : 18 - 25 (8 bit)
access : read-write

HSYNCSTART : HSYNC Start Delay
bits : 28 - 29 (2 bit)
access : read-write


TFTVPORCH

TFT Vertical Porch Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTVPORCH TFTVPORCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC VFPORCH VBPORCH

VSYNC : Vertical Synchronization Pulse Width
bits : 0 - 6 (7 bit)
access : read-write

VFPORCH : Vertical Front Porch Size
bits : 8 - 19 (12 bit)
access : read-write

VBPORCH : Vertical Back Porch Size
bits : 20 - 31 (12 bit)
access : read-write


RDTIMING

Read Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDTIMING RDTIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDSETUP RDSTRB RDHOLD HALFRE PREFETCH PAGEMODE

RDSETUP : Read Setup Time
bits : 0 - 2 (3 bit)
access : read-write

RDSTRB : Read Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

RDHOLD : Read Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFRE : Half Cycle REn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

PREFETCH : Prefetch Enable
bits : 29 - 29 (1 bit)
access : read-write

PAGEMODE : Page Mode Access Enable
bits : 30 - 30 (1 bit)
access : read-write


TFTTIMING

TFT Timing Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTTIMING TFTTIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCLKPERIOD TFTSTART TFTSETUP TFTHOLD

DCLKPERIOD : TFT Direct Drive Transaction (EBI_DCLK) Period
bits : 0 - 11 (12 bit)
access : read-write

TFTSTART : TFT Direct Drive Transaction Start
bits : 12 - 23 (12 bit)
access : read-write

TFTSETUP : TFT Setup Time
bits : 24 - 26 (3 bit)
access : read-write

TFTHOLD : TFT Hold Time
bits : 28 - 30 (3 bit)
access : read-write


TFTPOLARITY

TFT Polarity Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTPOLARITY TFTPOLARITY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPOL DCLKPOL DATAENPOL HSYNCPOL VSYNCPOL

CSPOL : TFT Chip Select Polarity
bits : 0 - 0 (1 bit)
access : read-write

DCLKPOL : TFT DCLK Polarity
bits : 1 - 1 (1 bit)
access : read-write

DATAENPOL : TFT DATAEN Polarity
bits : 2 - 2 (1 bit)
access : read-write

HSYNCPOL : Address Latch Polarity
bits : 3 - 3 (1 bit)
access : read-write

VSYNCPOL : VSYNC Polarity
bits : 4 - 4 (1 bit)
access : read-write


TFTDD

TFT Direct Drive Data Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTDD TFTDD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : TFT Direct Drive Data From Internal Memory
bits : 0 - 23 (24 bit)
access : read-write


TFTALPHA

TFT Alpha Blending Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTALPHA TFTALPHA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALPHA

ALPHA : TFT Alpha Blending Factor
bits : 0 - 8 (9 bit)
access : read-write


TFTPIXEL0

TFT Pixel 0 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTPIXEL0 TFTPIXEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : RGB Data
bits : 0 - 23 (24 bit)
access : read-write


TFTPIXEL1

TFT Pixel 1 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTPIXEL1 TFTPIXEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : RGB Data
bits : 0 - 23 (24 bit)
access : read-write


TFTPIXEL

TFT Alpha Blending Result Pixel Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TFTPIXEL TFTPIXEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Alpha Blending Result
bits : 0 - 23 (24 bit)
access : read-only


TFTMASK

TFT Masking Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFTMASK TFTMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFTMASK

TFTMASK : TFT Mask Value
bits : 0 - 23 (24 bit)
access : read-write


IF

Interrupt Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC HSYNC VBPORCH VFPORCH DDEMPTY DDJIT TFTPIXEL0EMPTY TFTPIXEL1EMPTY TFTPIXELFULL TFTPIXELOF

VSYNC : Vertical Sync Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

HSYNC : Horizontal Sync Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

VBPORCH : Vertical Back Porch Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

VFPORCH : Vertical Front Porch Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

DDEMPTY : Direct Drive Data Empty Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

DDJIT : Direct Drive Jitter Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only

TFTPIXEL0EMPTY : EBI_TFTPIXEL0 is Empty Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only

TFTPIXEL1EMPTY : EBI_TFTPIXEL1 is Empty Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

TFTPIXELFULL : EBI_TFTPIXEL is Full Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only

TFTPIXELOF : EBI_TFTPIXEL Register Overflow Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC HSYNC VBPORCH VFPORCH DDEMPTY DDJIT TFTPIXEL0EMPTY TFTPIXEL1EMPTY TFTPIXELFULL TFTPIXELOF

VSYNC : Vertical Sync Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only

HSYNC : Horizontal Sync Interrupt Flag Set
bits : 1 - 1 (1 bit)
access : write-only

VBPORCH : Vertical Back Porch Interrupt Flag Set
bits : 2 - 2 (1 bit)
access : write-only

VFPORCH : Vertical Front Porch Interrupt Flag Set
bits : 3 - 3 (1 bit)
access : write-only

DDEMPTY : Direct Drive Data Empty Interrupt Flag Set
bits : 4 - 4 (1 bit)
access : write-only

DDJIT : Direct Drive Jitter Interrupt Flag Set
bits : 5 - 5 (1 bit)
access : write-only

TFTPIXEL0EMPTY : EBI_TFTPIXEL0 Empty Interrupt Flag Set
bits : 6 - 6 (1 bit)
access : write-only

TFTPIXEL1EMPTY : EBI_TFTPIXEL1 Empty Interrupt Flag Set
bits : 7 - 7 (1 bit)
access : write-only

TFTPIXELFULL : EBI_TFTPIXEL Full Interrupt Flag Set
bits : 8 - 8 (1 bit)
access : write-only

TFTPIXELOF : EBI_TFTPIXEL Overflow Interrupt Flag Set
bits : 9 - 9 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC HSYNC VBPORCH VFPORCH DDEMPTY DDJIT TFTPIXEL0EMPTY TFTPIXEL1EMPTY TFTPIXELFULL TFTPIXELOF

VSYNC : Vertical Sync Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only

HSYNC : Horizontal Sync Interrupt Flag Clear
bits : 1 - 1 (1 bit)
access : write-only

VBPORCH : Vertical Back Porch Interrupt Flag Clear
bits : 2 - 2 (1 bit)
access : write-only

VFPORCH : Vertical Front Porch Interrupt Flag Clear
bits : 3 - 3 (1 bit)
access : write-only

DDEMPTY : Direct Drive Data Empty Interrupt Flag Clear
bits : 4 - 4 (1 bit)
access : write-only

DDJIT : Direct Drive Jitter Interrupt Flag Clear
bits : 5 - 5 (1 bit)
access : write-only

TFTPIXEL0EMPTY : EBI_TFTPIXEL0 Empty Interrupt Flag Clear
bits : 6 - 6 (1 bit)
access : write-only

TFTPIXEL1EMPTY : EBI_TFTPIXEL1 Empty Interrupt Flag Clear
bits : 7 - 7 (1 bit)
access : write-only

TFTPIXELFULL : EBI_TFTPIXEL Full Interrupt Flag Clear
bits : 8 - 8 (1 bit)
access : write-only

TFTPIXELOF : EBI_TFTPIXEL Overflow Interrupt Flag Clear
bits : 9 - 9 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC HSYNC VBPORCH VFPORCH DDEMPTY DDJIT TFTPIXEL0EMPTY TFTPIXEL1EMPTY TFTPIXELFULL TFTPIXELOF

VSYNC : Vertical Sync Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

HSYNC : Horizontal Sync Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

VBPORCH : Vertical Back Porch Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

VFPORCH : Vertical Front Porch Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

DDEMPTY : Direct Drive Data Empty Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

DDJIT : Direct Drive Jitter Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

TFTPIXEL0EMPTY : EBI_TFTPIXEL0 Empty Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

TFTPIXEL1EMPTY : EBI_TFTPIXEL1 Empty Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

TFTPIXELFULL : EBI_TFTPIXEL Full Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

TFTPIXELOF : EBI_TFTPIXEL Overflow Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write


ROUTEPEN

I/O Routing Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTEPEN ROUTEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBIPEN CS0PEN CS1PEN CS2PEN CS3PEN ALEPEN ARDYPEN BLPEN NANDPEN ALB APEN TFTPEN DATAENPEN CSTFTPEN

EBIPEN : EBI Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

CS0PEN : EBI_CS0 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CS1PEN : EBI_CS1 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CS2PEN : EBI_CS2 Pin Enable
bits : 3 - 3 (1 bit)
access : read-write

CS3PEN : EBI_CS3 Pin Enable
bits : 4 - 4 (1 bit)
access : read-write

ALEPEN : EBI_ALE Pin Enable
bits : 5 - 5 (1 bit)
access : read-write

ARDYPEN : EBI_ARDY Pin Enable
bits : 6 - 6 (1 bit)
access : read-write

BLPEN : EBI_BL[1:0] Pin Enable
bits : 7 - 7 (1 bit)
access : read-write

NANDPEN : NANDRE and NANDWE Pin Enable
bits : 12 - 12 (1 bit)
access : read-write

ALB : Sets the Lower Bound for EBI_A Enabling
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x00000000 : A0

Address lines from EBI_A[0] and upwards can be enabled via APEN.

0x00000001 : A8

Address lines from EBI_A[8] and upwards can be enabled via APEN.

0x00000002 : A16

Address lines from EBI_A[16] and upwards can be enabled via APEN.

0x00000003 : A24

Address lines from EBI_A[24] and upwards can be enabled via APEN.

End of enumeration elements list.

APEN : EBI_A Pin Enable
bits : 18 - 22 (5 bit)
access : read-write

Enumeration:

0x00000000 : A0

All EBI_A pins are disabled.

0x00000005 : A5

EBI_A[4:L] pins enabled.

0x00000006 : A6

EBI_A[5:L] pins enabled.

0x00000007 : A7

EBI_A[6:L] pins enabled.

0x00000008 : A8

EBI_A[7:L] pins enabled.

0x00000009 : A9

EBI_A[8:L] pins enabled.

0x0000000A : A10

EBI_A[9:L] pins enabled.

0x0000000B : A11

EBI_A[10:L] pins enabled.

0x0000000C : A12

EBI_A[11:L] pins enabled.

0x0000000D : A13

EBI_A[12:L] pins enabled.

0x0000000E : A14

EBI_A[13:L] pins enabled.

0x0000000F : A15

EBI_A[14:L] pins enabled.

0x00000010 : A16

EBI_A[15:L] pins enabled.

0x00000011 : A17

EBI_A[16:L] pins enabled.

0x00000012 : A18

EBI_A[17:L] pins enabled.

0x00000013 : A19

EBI_A[18:L] pins enabled.

0x00000014 : A20

EBI_A[19:L] pins enabled.

0x00000015 : A21

EBI_A[20:L] pins enabled.

0x00000016 : A22

EBI_A[21:L] pins enabled.

0x00000017 : A23

EBI_A[22:L] pins enabled.

0x00000018 : A24

EBI_A[23:L] pins enabled.

0x00000019 : A25

EBI_A[24:L] pins enabled.

0x0000001A : A26

EBI_A[25:L] pins enabled.

0x0000001B : A27

EBI_A[26:L] pins enabled.

0x0000001C : A28

EBI_A[27:L] pins enabled.

End of enumeration elements list.

TFTPEN : EBI_TFT Pin Enable
bits : 24 - 24 (1 bit)
access : read-write

DATAENPEN : EBI_DATA Pin Enable
bits : 25 - 25 (1 bit)
access : read-write

CSTFTPEN : EBI_CSTFT Pin Enable
bits : 26 - 26 (1 bit)
access : read-write


ROUTELOC0

I/O Routing Location Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC0 ROUTELOC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBILOC CSLOC NANDLOC TFTLOC

EBILOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.

CSLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

End of enumeration elements list.

NANDLOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.

TFTLOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.


ROUTELOC1

I/O Routing Location Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC1 ROUTELOC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLOC ALOC RDYLOC

ADLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.

ALOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.

RDYLOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.


WRTIMING

Write Timing Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRTIMING WRTIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRSETUP WRSTRB WRHOLD HALFWE WBUFDIS

WRSETUP : Write Setup Time
bits : 0 - 2 (3 bit)
access : read-write

WRSTRB : Write Strobe Time
bits : 8 - 14 (7 bit)
access : read-write

WRHOLD : Write Hold Time
bits : 16 - 18 (3 bit)
access : read-write

HALFWE : Half Cycle WEn Strobe Duration Enable
bits : 28 - 28 (1 bit)
access : read-write

WBUFDIS : Write Buffer Disable
bits : 29 - 29 (1 bit)
access : read-write



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