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USART4

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STATUS

CLKDIV

RXDATAX

RXDATA

RXDOUBLEX

RXDOUBLE

RXDATAXP

RXDOUBLEXP

TXDATAX

TXDATA

TXDOUBLEX

TXDOUBLE

FRAME

IF

IFS

IFC

IEN

IRCTRL

INPUT

I2SCTRL

TIMING

CTRLX

TIMECMP0

TIMECMP1

TIMECMP2

ROUTEPEN

ROUTELOC0

ROUTELOC1

TRIGCTRL

CMD


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC LOOPBK CCEN MPM MPAB OVS CLKPOL CLKPHA MSBF CSMA TXBIL RXINV TXINV CSINV AUTOCS AUTOTRI SCMODE SCRETRANS SKIPPERRF BIT8DV ERRSDMA ERRSRX ERRSTX SSSEARLY BYTESWAP AUTOTX MVDIS SMSDELAY

SYNC : USART Synchronous Mode
bits : 0 - 0 (1 bit)
access : read-write

LOOPBK : Loopback Enable
bits : 1 - 1 (1 bit)
access : read-write

CCEN : Collision Check Enable
bits : 2 - 2 (1 bit)
access : read-write

MPM : Multi-Processor Mode
bits : 3 - 3 (1 bit)
access : read-write

MPAB : Multi-Processor Address-Bit
bits : 4 - 4 (1 bit)
access : read-write

OVS : Oversampling
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x00000000 : X16

Regular UART mode with 16X oversampling in asynchronous mode

0x00000001 : X8

Double speed with 8X oversampling in asynchronous mode

0x00000002 : X6

6X oversampling in asynchronous mode

0x00000003 : X4

Quadruple speed with 4X oversampling in asynchronous mode

End of enumeration elements list.

CLKPOL : Clock Polarity
bits : 8 - 8 (1 bit)
access : read-write

CLKPHA : Clock Edge for Setup/Sample
bits : 9 - 9 (1 bit)
access : read-write

MSBF : Most Significant Bit First
bits : 10 - 10 (1 bit)
access : read-write

CSMA : Action on Slave-Select in Master Mode
bits : 11 - 11 (1 bit)
access : read-write

TXBIL : TX Buffer Interrupt Level
bits : 12 - 12 (1 bit)
access : read-write

RXINV : Receiver Input Invert
bits : 13 - 13 (1 bit)
access : read-write

TXINV : Transmitter Output Invert
bits : 14 - 14 (1 bit)
access : read-write

CSINV : Chip Select Invert
bits : 15 - 15 (1 bit)
access : read-write

AUTOCS : Automatic Chip Select
bits : 16 - 16 (1 bit)
access : read-write

AUTOTRI : Automatic TX Tristate
bits : 17 - 17 (1 bit)
access : read-write

SCMODE : SmartCard Mode
bits : 18 - 18 (1 bit)
access : read-write

SCRETRANS : SmartCard Retransmit
bits : 19 - 19 (1 bit)
access : read-write

SKIPPERRF : Skip Parity Error Frames
bits : 20 - 20 (1 bit)
access : read-write

BIT8DV : Bit 8 Default Value
bits : 21 - 21 (1 bit)
access : read-write

ERRSDMA : Halt DMA on Error
bits : 22 - 22 (1 bit)
access : read-write

ERRSRX : Disable RX on Error
bits : 23 - 23 (1 bit)
access : read-write

ERRSTX : Disable TX on Error
bits : 24 - 24 (1 bit)
access : read-write

SSSEARLY : Synchronous Slave Setup Early
bits : 25 - 25 (1 bit)
access : read-write

BYTESWAP : Byteswap in Double Accesses
bits : 28 - 28 (1 bit)
access : read-write

AUTOTX : Always Transmit When RX Not Full
bits : 29 - 29 (1 bit)
access : read-write

MVDIS : Majority Vote Disable
bits : 30 - 30 (1 bit)
access : read-write

SMSDELAY : Synchronous Master Sample Delay
bits : 31 - 31 (1 bit)
access : read-write


STATUS

USART Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXENS TXENS MASTER RXBLOCK TXTRI TXC TXBL RXDATAV RXFULL TXBDRIGHT TXBSRIGHT RXDATAVRIGHT RXFULLRIGHT TXIDLE TIMERRESTARTED TXBUFCNT

RXENS : Receiver Enable Status
bits : 0 - 0 (1 bit)
access : read-only

TXENS : Transmitter Enable Status
bits : 1 - 1 (1 bit)
access : read-only

MASTER : SPI Master Mode
bits : 2 - 2 (1 bit)
access : read-only

RXBLOCK : Block Incoming Data
bits : 3 - 3 (1 bit)
access : read-only

TXTRI : Transmitter Tristated
bits : 4 - 4 (1 bit)
access : read-only

TXC : TX Complete
bits : 5 - 5 (1 bit)
access : read-only

TXBL : TX Buffer Level
bits : 6 - 6 (1 bit)
access : read-only

RXDATAV : RX Data Valid
bits : 7 - 7 (1 bit)
access : read-only

RXFULL : RX FIFO Full
bits : 8 - 8 (1 bit)
access : read-only

TXBDRIGHT : TX Buffer Expects Double Right Data
bits : 9 - 9 (1 bit)
access : read-only

TXBSRIGHT : TX Buffer Expects Single Right Data
bits : 10 - 10 (1 bit)
access : read-only

RXDATAVRIGHT : RX Data Right
bits : 11 - 11 (1 bit)
access : read-only

RXFULLRIGHT : RX Full of Right Data
bits : 12 - 12 (1 bit)
access : read-only

TXIDLE : TX Idle
bits : 13 - 13 (1 bit)
access : read-only

TIMERRESTARTED : The USART Timer Restarted Itself
bits : 14 - 14 (1 bit)
access : read-only

TXBUFCNT : TX Buffer Count
bits : 16 - 17 (2 bit)
access : read-only


CLKDIV

Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV AUTOBAUDEN

DIV : Fractional Clock Divider
bits : 3 - 22 (20 bit)
access : read-write

AUTOBAUDEN : AUTOBAUD Detection Enable
bits : 31 - 31 (1 bit)
access : read-write


RXDATAX

RX Buffer Data Extended Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAX RXDATAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA PERR FERR

RXDATA : RX Data
bits : 0 - 8 (9 bit)
access : read-only

PERR : Data Parity Error
bits : 14 - 14 (1 bit)
access : read-only

FERR : Data Framing Error
bits : 15 - 15 (1 bit)
access : read-only


RXDATA

RX Buffer Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATA RXDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLEX

RX Buffer Double Data Extended Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEX RXDOUBLEX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 PERR0 FERR0 RXDATA1 PERR1 FERR1

RXDATA0 : RX Data 0
bits : 0 - 8 (9 bit)
access : read-only

PERR0 : Data Parity Error 0
bits : 14 - 14 (1 bit)
access : read-only

FERR0 : Data Framing Error 0
bits : 15 - 15 (1 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 16 - 24 (9 bit)
access : read-only

PERR1 : Data Parity Error 1
bits : 30 - 30 (1 bit)
access : read-only

FERR1 : Data Framing Error 1
bits : 31 - 31 (1 bit)
access : read-only


RXDOUBLE

RX FIFO Double Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLE RXDOUBLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 RXDATA1

RXDATA0 : RX Data 0
bits : 0 - 7 (8 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 8 - 15 (8 bit)
access : read-only


RXDATAXP

RX Buffer Data Extended Peek Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAXP RXDATAXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP PERRP FERRP

RXDATAP : RX Data Peek
bits : 0 - 8 (9 bit)
access : read-only

PERRP : Data Parity Error Peek
bits : 14 - 14 (1 bit)
access : read-only

FERRP : Data Framing Error Peek
bits : 15 - 15 (1 bit)
access : read-only


RXDOUBLEXP

RX Buffer Double Data Extended Peek Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEXP RXDOUBLEXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP0 PERRP0 FERRP0 RXDATAP1 PERRP1 FERRP1

RXDATAP0 : RX Data 0 Peek
bits : 0 - 8 (9 bit)
access : read-only

PERRP0 : Data Parity Error 0 Peek
bits : 14 - 14 (1 bit)
access : read-only

FERRP0 : Data Framing Error 0 Peek
bits : 15 - 15 (1 bit)
access : read-only

RXDATAP1 : RX Data 1 Peek
bits : 16 - 24 (9 bit)
access : read-only

PERRP1 : Data Parity Error 1 Peek
bits : 30 - 30 (1 bit)
access : read-only

FERRP1 : Data Framing Error 1 Peek
bits : 31 - 31 (1 bit)
access : read-only


TXDATAX

TX Buffer Data Extended Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDATAX TXDATAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATAX UBRXAT TXTRIAT TXBREAK TXDISAT RXENAT

TXDATAX : TX Data
bits : 0 - 8 (9 bit)
access : read-write

UBRXAT : Unblock RX After Transmission
bits : 11 - 11 (1 bit)
access : read-write

TXTRIAT : Set TXTRI After Transmission
bits : 12 - 12 (1 bit)
access : read-write

TXBREAK : Transmit Data as Break
bits : 13 - 13 (1 bit)
access : read-write

TXDISAT : Clear TXEN After Transmission
bits : 14 - 14 (1 bit)
access : read-write

RXENAT : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : read-write


TXDATA

TX Buffer Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDATA TXDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7 (8 bit)
access : read-write


TXDOUBLEX

TX Buffer Double Data Extended Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLEX TXDOUBLEX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 UBRXAT0 TXTRIAT0 TXBREAK0 TXDISAT0 RXENAT0 TXDATA1 UBRXAT1 TXTRIAT1 TXBREAK1 TXDISAT1 RXENAT1

TXDATA0 : TX Data
bits : 0 - 8 (9 bit)
access : read-write

UBRXAT0 : Unblock RX After Transmission
bits : 11 - 11 (1 bit)
access : read-write

TXTRIAT0 : Set TXTRI After Transmission
bits : 12 - 12 (1 bit)
access : read-write

TXBREAK0 : Transmit Data as Break
bits : 13 - 13 (1 bit)
access : read-write

TXDISAT0 : Clear TXEN After Transmission
bits : 14 - 14 (1 bit)
access : read-write

RXENAT0 : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : read-write

TXDATA1 : TX Data
bits : 16 - 24 (9 bit)
access : read-write

UBRXAT1 : Unblock RX After Transmission
bits : 27 - 27 (1 bit)
access : read-write

TXTRIAT1 : Set TXTRI After Transmission
bits : 28 - 28 (1 bit)
access : read-write

TXBREAK1 : Transmit Data as Break
bits : 29 - 29 (1 bit)
access : read-write

TXDISAT1 : Clear TXEN After Transmission
bits : 30 - 30 (1 bit)
access : read-write

RXENAT1 : Enable RX After Transmission
bits : 31 - 31 (1 bit)
access : read-write


TXDOUBLE

TX Buffer Double Data Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLE TXDOUBLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 TXDATA1

TXDATA0 : TX Data
bits : 0 - 7 (8 bit)
access : read-write

TXDATA1 : TX Data
bits : 8 - 15 (8 bit)
access : read-write


FRAME

USART Frame Format Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAME FRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABITS PARITY STOPBITS

DATABITS : Data-Bit Mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000001 : FOUR

Each frame contains 4 data bits

0x00000002 : FIVE

Each frame contains 5 data bits

0x00000003 : SIX

Each frame contains 6 data bits

0x00000004 : SEVEN

Each frame contains 7 data bits

0x00000005 : EIGHT

Each frame contains 8 data bits

0x00000006 : NINE

Each frame contains 9 data bits

0x00000007 : TEN

Each frame contains 10 data bits

0x00000008 : ELEVEN

Each frame contains 11 data bits

0x00000009 : TWELVE

Each frame contains 12 data bits

0x0000000A : THIRTEEN

Each frame contains 13 data bits

0x0000000B : FOURTEEN

Each frame contains 14 data bits

0x0000000C : FIFTEEN

Each frame contains 15 data bits

0x0000000D : SIXTEEN

Each frame contains 16 data bits

End of enumeration elements list.

PARITY : Parity-Bit Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : NONE

Parity bits are not used

0x00000002 : EVEN

Even parity are used. Parity bits are automatically generated and checked by hardware.

0x00000003 : ODD

Odd parity is used. Parity bits are automatically generated and checked by hardware.

End of enumeration elements list.

STOPBITS : Stop-Bit Mode
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x00000000 : HALF

The transmitter generates a half stop bit. Stop-bits are not verified by receiver

0x00000001 : ONE

One stop bit is generated and verified

0x00000002 : ONEANDAHALF

The transmitter generates one and a half stop bit. The receiver verifies the first stop bit

0x00000003 : TWO

The transmitter generates two stop bits. The receiver checks the first stop-bit only

End of enumeration elements list.


IF

Interrupt Flag Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF TXIDLE TCMP0 TCMP1 TCMP2

TXC : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

TXBL : TX Buffer Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

RXDATAV : RX Data Valid Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

RXFULL : RX Buffer Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

RXOF : RX Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

RXUF : RX Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only

TXOF : TX Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only

TXUF : TX Underflow Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

PERR : Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only

FERR : Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only

MPAF : Multi-Processor Address Frame Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-only

SSM : Slave-Select in Master Mode Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only

CCF : Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-only

TXIDLE : TX Idle Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-only

TCMP0 : Timer Comparator 0 Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-only

TCMP1 : Timer Comparator 1 Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-only

TCMP2 : Timer Comparator 2 Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF TXIDLE TCMP0 TCMP1 TCMP2

TXC : Set TXC Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

RXFULL : Set RXFULL Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

RXOF : Set RXOF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

RXUF : Set RXUF Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

TXOF : Set TXOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

TXUF : Set TXUF Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

PERR : Set PERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

FERR : Set FERR Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

MPAF : Set MPAF Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

SSM : Set SSM Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

CCF : Set CCF Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only

TXIDLE : Set TXIDLE Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only

TCMP0 : Set TCMP0 Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

TCMP1 : Set TCMP1 Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

TCMP2 : Set TCMP2 Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF TXIDLE TCMP0 TCMP1 TCMP2

TXC : Clear TXC Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

RXFULL : Clear RXFULL Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

RXOF : Clear RXOF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

RXUF : Clear RXUF Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

TXOF : Clear TXOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

TXUF : Clear TXUF Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

PERR : Clear PERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

FERR : Clear FERR Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

MPAF : Clear MPAF Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

SSM : Clear SSM Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

CCF : Clear CCF Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only

TXIDLE : Clear TXIDLE Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only

TCMP0 : Clear TCMP0 Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

TCMP1 : Clear TCMP1 Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

TCMP2 : Clear TCMP2 Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF TXIDLE TCMP0 TCMP1 TCMP2

TXC : TXC Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

TXBL : TXBL Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

RXDATAV : RXDATAV Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

RXFULL : RXFULL Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

RXOF : RXOF Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

RXUF : RXUF Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

TXOF : TXOF Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

TXUF : TXUF Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

PERR : PERR Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

FERR : FERR Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

MPAF : MPAF Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

SSM : SSM Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

CCF : CCF Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

TXIDLE : TXIDLE Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

TCMP0 : TCMP0 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

TCMP1 : TCMP1 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write

TCMP2 : TCMP2 Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write


IRCTRL

IrDA Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRCTRL IRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IREN IRPW IRFILT IRPRSEN IRPRSSEL

IREN : Enable IrDA Module
bits : 0 - 0 (1 bit)
access : read-write

IRPW : IrDA TX Pulse Width
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x00000000 : ONE

IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1

0x00000001 : TWO

IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1

0x00000002 : THREE

IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1

0x00000003 : FOUR

IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1

End of enumeration elements list.

IRFILT : IrDA RX Filter
bits : 3 - 3 (1 bit)
access : read-write

IRPRSEN : IrDA PRS Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

IRPRSSEL : IrDA PRS Channel Select
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

0x00000008 : PRSCH8

PRS Channel 8 selected

0x00000009 : PRSCH9

PRS Channel 9 selected

0x0000000A : PRSCH10

PRS Channel 10 selected

0x0000000B : PRSCH11

PRS Channel 11 selected

0x0000000C : PRSCH12

PRS Channel 12 selected

0x0000000D : PRSCH13

PRS Channel 13 selected

0x0000000E : PRSCH14

PRS Channel 14 selected

0x0000000F : PRSCH15

PRS Channel 15 selected

0x00000010 : PRSCH16

PRS Channel 16 selected

0x00000011 : PRSCH17

PRS Channel 17 selected

0x00000012 : PRSCH18

PRS Channel 18 selected

0x00000013 : PRSCH19

PRS Channel 19 selected

0x00000014 : PRSCH20

PRS Channel 20 selected

0x00000015 : PRSCH21

PRS Channel 21 selected

0x00000016 : PRSCH22

PRS Channel 22 selected

0x00000017 : PRSCH23

PRS Channel 23 selected

End of enumeration elements list.


INPUT

USART Input Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INPUT INPUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPRSSEL RXPRS CLKPRSSEL CLKPRS

RXPRSSEL : RX PRS Channel Select
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

0x00000008 : PRSCH8

PRS Channel 8 selected

0x00000009 : PRSCH9

PRS Channel 9 selected

0x0000000A : PRSCH10

PRS Channel 10 selected

0x0000000B : PRSCH11

PRS Channel 11 selected

0x0000000C : PRSCH12

PRS Channel 12 selected

0x0000000D : PRSCH13

PRS Channel 13 selected

0x0000000E : PRSCH14

PRS Channel 14 selected

0x0000000F : PRSCH15

PRS Channel 15 selected

0x00000010 : PRSCH16

PRS Channel 16 selected

0x00000011 : PRSCH17

PRS Channel 17 selected

0x00000012 : PRSCH18

PRS Channel 18 selected

0x00000013 : PRSCH19

PRS Channel 19 selected

0x00000014 : PRSCH20

PRS Channel 20 selected

0x00000015 : PRSCH21

PRS Channel 21 selected

0x00000016 : PRSCH22

PRS Channel 22 selected

0x00000017 : PRSCH23

PRS Channel 23 selected

End of enumeration elements list.

RXPRS : PRS RX Enable
bits : 7 - 7 (1 bit)
access : read-write

CLKPRSSEL : CLK PRS Channel Select
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

0x00000008 : PRSCH8

PRS Channel 8 selected

0x00000009 : PRSCH9

PRS Channel 9 selected

0x0000000A : PRSCH10

PRS Channel 10 selected

0x0000000B : PRSCH11

PRS Channel 11 selected

0x0000000C : PRSCH12

PRS Channel 12 selected

0x0000000D : PRSCH13

PRS Channel 13 selected

0x0000000E : PRSCH14

PRS Channel 14 selected

0x0000000F : PRSCH15

PRS Channel 15 selected

0x00000010 : PRSCH16

PRS Channel 16 selected

0x00000011 : PRSCH17

PRS Channel 17 selected

0x00000012 : PRSCH18

PRS Channel 18 selected

0x00000013 : PRSCH19

PRS Channel 19 selected

0x00000014 : PRSCH20

PRS Channel 20 selected

0x00000015 : PRSCH21

PRS Channel 21 selected

0x00000016 : PRSCH22

PRS Channel 22 selected

0x00000017 : PRSCH23

PRS Channel 23 selected

End of enumeration elements list.

CLKPRS : PRS CLK Enable
bits : 15 - 15 (1 bit)
access : read-write


I2SCTRL

I2S Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCTRL I2SCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MONO JUSTIFY DMASPLIT DELAY FORMAT

EN : Enable I2S Mode
bits : 0 - 0 (1 bit)
access : read-write

MONO : Stero or Mono
bits : 1 - 1 (1 bit)
access : read-write

JUSTIFY : Justification of I2S Data
bits : 2 - 2 (1 bit)
access : read-write

DMASPLIT : Separate DMA Request for Left/Right Data
bits : 3 - 3 (1 bit)
access : read-write

DELAY : Delay on I2S Data
bits : 4 - 4 (1 bit)
access : read-write

FORMAT : I2S Word Format
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x00000000 : W32D32

32-bit word, 32-bit data

0x00000001 : W32D24M

32-bit word, 32-bit data with 8 lsb masked

0x00000002 : W32D24

32-bit word, 24-bit data

0x00000003 : W32D16

32-bit word, 16-bit data

0x00000004 : W32D8

32-bit word, 8-bit data

0x00000005 : W16D16

16-bit word, 16-bit data

0x00000006 : W16D8

16-bit word, 8-bit data

0x00000007 : W8D8

8-bit word, 8-bit data

End of enumeration elements list.


TIMING

Timing Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDELAY CSSETUP ICS CSHOLD

TXDELAY : TX Frame Start Delay
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Disable - TXDELAY in USARTn_CTRL can be used for legacy

0x00000001 : ONE

Start of transmission is delayed for 1 baud-times

0x00000002 : TWO

Start of transmission is delayed for 2 baud-times

0x00000003 : THREE

Start of transmission is delayed for 3 baud-times

0x00000004 : SEVEN

Start of transmission is delayed for 7 baud-times

0x00000005 : TCMP0

Start of transmission is delayed for TCMPVAL0 baud-times

0x00000006 : TCMP1

Start of transmission is delayed for TCMPVAL1 baud-times

0x00000007 : TCMP2

Start of transmission is delayed for TCMPVAL2 baud-times

End of enumeration elements list.

CSSETUP : Chip Select Setup
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x00000000 : ZERO

CS is not asserted before start of transmission

0x00000001 : ONE

CS is asserted for 1 baud-times before start of transmission

0x00000002 : TWO

CS is asserted for 2 baud-times before start of transmission

0x00000003 : THREE

CS is asserted for 3 baud-times before start of transmission

0x00000004 : SEVEN

CS is asserted for 7 baud-times before start of transmission

0x00000005 : TCMP0

CS is asserted before the start of transmission for TCMPVAL0 baud-times

0x00000006 : TCMP1

CS is asserted before the start of transmission for TCMPVAL1 baud-times

0x00000007 : TCMP2

CS is asserted before the start of transmission for TCMPVAL2 baud-times

End of enumeration elements list.

ICS : Inter-character Spacing
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : ZERO

There is no space between charcters

0x00000001 : ONE

Create a space of 1 baud-times before start of transmission

0x00000002 : TWO

Create a space of 2 baud-times before start of transmission

0x00000003 : THREE

Create a space of 3 baud-times before start of transmission

0x00000004 : SEVEN

Create a space of 7 baud-times before start of transmission

0x00000005 : TCMP0

Create a space of before the start of transmission for TCMPVAL0 baud-times

0x00000006 : TCMP1

Create a space of before the start of transmission for TCMPVAL1 baud-times

0x00000007 : TCMP2

Create a space of before the start of transmission for TCMPVAL2 baud-times

End of enumeration elements list.

CSHOLD : Chip Select Hold
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

0x00000000 : ZERO

Disable CS being asserted after the end of transmission

0x00000001 : ONE

CS is asserted for 1 baud-times after the end of transmission

0x00000002 : TWO

CS is asserted for 2 baud-times after the end of transmission

0x00000003 : THREE

CS is asserted for 3 baud-times after the end of transmission

0x00000004 : SEVEN

CS is asserted for 7 baud-times after the end of transmission

0x00000005 : TCMP0

CS is asserted after the end of transmission for TCMPVAL0 baud-times

0x00000006 : TCMP1

CS is asserted after the end of transmission for TCMPVAL1 baud-times

0x00000007 : TCMP2

CS is asserted after the end of transmission for TCMPVAL2 baud-times

End of enumeration elements list.


CTRLX

Control Register Extended
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLX CTRLX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGHALT CTSINV CTSEN RTSINV

DBGHALT : Debug Halt
bits : 0 - 0 (1 bit)
access : read-write

CTSINV : CTS Pin Inversion
bits : 1 - 1 (1 bit)
access : read-write

CTSEN : CTS Function Enabled
bits : 2 - 2 (1 bit)
access : read-write

RTSINV : RTS Pin Inversion
bits : 3 - 3 (1 bit)
access : read-write


TIMECMP0

Used to Generate Interrupts and Various Delays
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMECMP0 TIMECMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMPVAL TSTART TSTOP RESTARTEN

TCMPVAL : Timer Comparator 0
bits : 0 - 7 (8 bit)
access : read-write

TSTART : Timer Start Source
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Comparator 0 is disabled

0x00000001 : TXEOF

Comparator 0 and timer are started at TX end of frame

0x00000002 : TXC

Comparator 0 and timer are started at TX Complete

0x00000003 : RXACT

Comparator 0 and timer are started at RX going Active (default: low)

0x00000004 : RXEOF

Comparator 0 and timer are started at RX end of frame

End of enumeration elements list.

TSTOP : Source Used to Disable Comparator 0
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x00000000 : TCMP0

Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event

0x00000001 : TXST

Comparator 0 is disabled at the start of transmission

0x00000002 : RXACT

Comparator 0 is disabled on RX going going Active (default: low)

0x00000003 : RXACTN

Comparator 0 is disabled on RX going Inactive

End of enumeration elements list.

RESTARTEN : Restart Timer on TCMP0
bits : 24 - 24 (1 bit)
access : read-write


TIMECMP1

Used to Generate Interrupts and Various Delays
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMECMP1 TIMECMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMPVAL TSTART TSTOP RESTARTEN

TCMPVAL : Timer Comparator 1
bits : 0 - 7 (8 bit)
access : read-write

TSTART : Timer Start Source
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Comparator 1 is disabled

0x00000001 : TXEOF

Comparator 1 and timer are started at TX end of frame

0x00000002 : TXC

Comparator 1 and timer are started at TX Complete

0x00000003 : RXACT

Comparator 1 and timer are started at RX going going Active (default: low)

0x00000004 : RXEOF

Comparator 1 and timer are started at RX end of frame

End of enumeration elements list.

TSTOP : Source Used to Disable Comparator 1
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x00000000 : TCMP1

Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event

0x00000001 : TXST

Comparator 1 is disabled at TX start TX Engine

0x00000002 : RXACT

Comparator 1 is disabled on RX going going Active (default: low)

0x00000003 : RXACTN

Comparator 1 is disabled on RX going Inactive

End of enumeration elements list.

RESTARTEN : Restart Timer on TCMP1
bits : 24 - 24 (1 bit)
access : read-write


TIMECMP2

Used to Generate Interrupts and Various Delays
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMECMP2 TIMECMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMPVAL TSTART TSTOP RESTARTEN

TCMPVAL : Timer Comparator 2
bits : 0 - 7 (8 bit)
access : read-write

TSTART : Timer Start Source
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Comparator 2 is disabled

0x00000001 : TXEOF

Comparator 2 and timer are started at TX end of frame

0x00000002 : TXC

Comparator 2 and timer are started at TX Complete

0x00000003 : RXACT

Comparator 2 and timer are started at RX going going Active (default: low)

0x00000004 : RXEOF

Comparator 2 and timer are started at RX end of frame

End of enumeration elements list.

TSTOP : Source Used to Disable Comparator 2
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x00000000 : TCMP2

Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event

0x00000001 : TXST

Comparator 2 is disabled at TX start TX Engine

0x00000002 : RXACT

Comparator 2 is disabled on RX going going Active (default: low)

0x00000003 : RXACTN

Comparator 2 is disabled on RX going Inactive

End of enumeration elements list.

RESTARTEN : Restart Timer on TCMP2
bits : 24 - 24 (1 bit)
access : read-write


ROUTEPEN

I/O Routing Pin Enable Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTEPEN ROUTEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPEN TXPEN CSPEN CLKPEN CTSPEN RTSPEN

RXPEN : RX Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

TXPEN : TX Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CSPEN : CS Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CLKPEN : CLK Pin Enable
bits : 3 - 3 (1 bit)
access : read-write

CTSPEN : CTS Pin Enable
bits : 4 - 4 (1 bit)
access : read-write

RTSPEN : RTS Pin Enable
bits : 5 - 5 (1 bit)
access : read-write


ROUTELOC0

I/O Routing Location Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC0 ROUTELOC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXLOC TXLOC CSLOC CLKLOC

RXLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.

TXLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.

CSLOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.

CLKLOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.


ROUTELOC1

I/O Routing Location Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC1 ROUTELOC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSLOC RTSLOC

CTSLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.

RTSLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.


TRIGCTRL

USART Trigger Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIGCTRL TRIGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN AUTOTXTEN TXARX0EN TXARX1EN TXARX2EN RXATX0EN RXATX1EN RXATX2EN TSEL

RXTEN : Receive Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write

TXTEN : Transmit Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write

AUTOTXTEN : AUTOTX Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

TXARX0EN : Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL
bits : 7 - 7 (1 bit)
access : read-write

TXARX1EN : Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL
bits : 8 - 8 (1 bit)
access : read-write

TXARX2EN : Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL
bits : 9 - 9 (1 bit)
access : read-write

RXATX0EN : Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times
bits : 10 - 10 (1 bit)
access : read-write

RXATX1EN : Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times
bits : 11 - 11 (1 bit)
access : read-write

RXATX2EN : Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times
bits : 12 - 12 (1 bit)
access : read-write

TSEL : Trigger PRS Channel Select
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

0x00000008 : PRSCH8

PRS Channel 8 selected

0x00000009 : PRSCH9

PRS Channel 9 selected

0x0000000A : PRSCH10

PRS Channel 10 selected

0x0000000B : PRSCH11

PRS Channel 11 selected

0x0000000C : PRSCH12

PRS Channel 12 selected

0x0000000D : PRSCH13

PRS Channel 13 selected

0x0000000E : PRSCH14

PRS Channel 14 selected

0x0000000F : PRSCH15

PRS Channel 15 selected

0x00000010 : PRSCH16

PRS Channel 16 selected

0x00000011 : PRSCH17

PRS Channel 17 selected

0x00000012 : PRSCH18

PRS Channel 18 selected

0x00000013 : PRSCH19

PRS Channel 19 selected

0x00000014 : PRSCH20

PRS Channel 20 selected

0x00000015 : PRSCH21

PRS Channel 21 selected

0x00000016 : PRSCH22

PRS Channel 22 selected

0x00000017 : PRSCH23

PRS Channel 23 selected

End of enumeration elements list.


CMD

Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN RXDIS TXEN TXDIS MASTEREN MASTERDIS RXBLOCKEN RXBLOCKDIS TXTRIEN TXTRIDIS CLEARTX CLEARRX

RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 3 - 3 (1 bit)
access : write-only

MASTEREN : Master Enable
bits : 4 - 4 (1 bit)
access : write-only

MASTERDIS : Master Disable
bits : 5 - 5 (1 bit)
access : write-only

RXBLOCKEN : Receiver Block Enable
bits : 6 - 6 (1 bit)
access : write-only

RXBLOCKDIS : Receiver Block Disable
bits : 7 - 7 (1 bit)
access : write-only

TXTRIEN : Transmitter Tristate Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTRIDIS : Transmitter Tristate Disable
bits : 9 - 9 (1 bit)
access : write-only

CLEARTX : Clear TX
bits : 10 - 10 (1 bit)
access : write-only

CLEARRX : Clear RX
bits : 11 - 11 (1 bit)
access : write-only



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