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ETM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ETMCR

ETMSR

ETMSCR

ETMCNTRLDVR1

ETMSYNCFR

ETMIDR

ETMCCER

ETMTESSEICR

ETMTSEVR

ETMTEEVR

ETMTRACEIDR

ETMIDR2

ETMTECR1

ETMFFLR

ETMPDSR

ETMCCR

ETMTRIGGER

ETMISCIN

ITTRIGOUT

ETMITATBCTR2

ETMITATBCTR0

ETMITCTRL

ETMCLAIMSET

ETMCLAIMCLR

ETMLAR

ETMLSR

ETMAUTHSTATUS

ETMDEVTYPE

ETMPIDR4

ETMPIDR5

ETMPIDR6

ETMPIDR7

ETMPIDR0

ETMPIDR1

ETMPIDR2

ETMPIDR3

ETMCIDR0

ETMCIDR1

ETMCIDR2

ETMCIDR3


ETMCR

Main Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMCR ETMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWERDWN PORTSIZE STALL BRANCHOUTPUT DBGREQCTRL ETMPROG ETMPORTSEL PORTMODE2 PORTMODE EPORTSIZE TSTAMPEN

POWERDWN : ETM Control in low power mode
bits : 0 - 0 (1 bit)
access : read-write

PORTSIZE : ETM Port Size
bits : 4 - 6 (3 bit)
access : read-write

STALL : Stall Processor
bits : 7 - 7 (1 bit)
access : read-write

BRANCHOUTPUT : Branch Output
bits : 8 - 8 (1 bit)
access : read-write

DBGREQCTRL : Debug Request Control
bits : 9 - 9 (1 bit)
access : read-write

ETMPROG : ETM Programming
bits : 10 - 10 (1 bit)
access : read-write

ETMPORTSEL : ETM Port Selection
bits : 11 - 11 (1 bit)
access : read-write

PORTMODE2 : Port Mode[2]
bits : 13 - 13 (1 bit)
access : read-write

PORTMODE : Port Mode Control
bits : 16 - 17 (2 bit)
access : read-write

EPORTSIZE : Port Size[3]
bits : 21 - 22 (2 bit)
access : read-write

TSTAMPEN : Time Stamp Enable
bits : 28 - 28 (1 bit)
access : read-write


ETMSR

ETM Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMSR ETMSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHOF ETMPROGBIT TRACESTAT TRIGBIT

ETHOF : ETM Overflow
bits : 0 - 0 (1 bit)
access : read-only

ETMPROGBIT : ETM Programming Bit Status
bits : 1 - 1 (1 bit)
access : read-only

TRACESTAT : Trace Start/Stop Status
bits : 2 - 2 (1 bit)
access : read-write

TRIGBIT : Trigger Bit
bits : 3 - 3 (1 bit)
access : read-write


ETMSCR

ETM System Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMSCR ETMSCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXPORTSIZE FIFOFULL MAXPORTSIZE3 PORTSIZE PORTMODE PROCNUM NOFETCHCOMP

MAXPORTSIZE : Maximum Port Size
bits : 0 - 2 (3 bit)
access : read-only

FIFOFULL : FIFO FULL Supported
bits : 8 - 8 (1 bit)
access : read-only

MAXPORTSIZE3 : Max Port Size[3]
bits : 9 - 9 (1 bit)
access : read-only

PORTSIZE : Port Size Supported
bits : 10 - 10 (1 bit)
access : read-only

PORTMODE : Port Mode Supported
bits : 11 - 11 (1 bit)
access : read-only

PROCNUM : Number of Supported Processros
bits : 12 - 14 (3 bit)
access : read-only

NOFETCHCOMP : No Fetch Comparison
bits : 17 - 17 (1 bit)
access : read-only


ETMCNTRLDVR1

Counter Reload Value
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMCNTRLDVR1 ETMCNTRLDVR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Free running counter reload value
bits : 0 - 15 (16 bit)
access : read-write


ETMSYNCFR

Synchronisation Frequency Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMSYNCFR ETMSYNCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ

FREQ : Synchronisation Frequency Value
bits : 0 - 11 (12 bit)
access : read-write


ETMIDR

ID Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMIDR ETMIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMPVER ETMMINVER ETMMAJVER PROCFAM LPCF THUMBT SECEXT BPE IMPCODE

IMPVER : Implementation Revision
bits : 0 - 3 (4 bit)
access : read-only

ETMMINVER : Minor ETM Architecture Version
bits : 4 - 7 (4 bit)
access : read-only

ETMMAJVER : Major ETM Architecture Version
bits : 8 - 11 (4 bit)
access : read-only

PROCFAM : Implementer Code
bits : 12 - 15 (4 bit)
access : read-only

LPCF : Load PC First
bits : 16 - 16 (1 bit)
access : read-only

THUMBT : 32-bit Thumb Instruction Tracing
bits : 18 - 18 (1 bit)
access : read-only

SECEXT : Security Extension Support
bits : 19 - 19 (1 bit)
access : read-only

BPE : Branch Packet Encoding
bits : 20 - 20 (1 bit)
access : read-only

IMPCODE : Implementer Code
bits : 24 - 31 (8 bit)
access : read-only


ETMCCER

Configuration Code Extension Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMCCER ETMCCER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINPSEL EXTINPBUS READREGS DADDRCMP INSTRES EICEWPNT TEICEWPNT EICEIMP TIMP RFCNT TENC TSIZE

EXTINPSEL : Extended External Input Selectors
bits : 0 - 1 (2 bit)
access : read-only

EXTINPBUS : Extended External Input Bus
bits : 3 - 10 (8 bit)
access : read-only

READREGS : Readable Registers
bits : 11 - 11 (1 bit)
access : read-only

DADDRCMP : Data Address comparisons
bits : 12 - 12 (1 bit)
access : read-only

INSTRES : Instrumentation Resources
bits : 13 - 15 (3 bit)
access : read-only

EICEWPNT : EmbeddedICE watchpoint inputs
bits : 16 - 19 (4 bit)
access : read-only

TEICEWPNT : Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs
bits : 20 - 20 (1 bit)
access : read-only

EICEIMP : EmbeddedICE Behavior control Implemented
bits : 21 - 21 (1 bit)
access : read-only

TIMP : Timestamping Implemented
bits : 22 - 22 (1 bit)
access : read-only

RFCNT : Reduced Function Counter
bits : 27 - 27 (1 bit)
access : read-only

TENC : Timestamp Encoding
bits : 28 - 28 (1 bit)
access : read-only

TSIZE : Timestamp Size
bits : 29 - 29 (1 bit)
access : read-only


ETMTESSEICR

TraceEnable Start/Stop EmbeddedICE Control Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMTESSEICR ETMTESSEICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTRSEL STOPRSEL

STARTRSEL : Stop Resource Selection
bits : 0 - 3 (4 bit)
access : read-write

STOPRSEL : Stop Resource Selection
bits : 16 - 19 (4 bit)
access : read-write


ETMTSEVR

Timestamp Event Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMTSEVR ETMTSEVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESAEVT RESBEVT ETMFCNEVT

RESAEVT : ETM Resource A Event
bits : 0 - 6 (7 bit)
access : read-write

RESBEVT : ETM Resource B Event
bits : 7 - 13 (7 bit)
access : read-write

ETMFCNEVT : ETM Function Event
bits : 14 - 16 (3 bit)
access : read-write


ETMTEEVR

ETM TraceEnable Event Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMTEEVR ETMTEEVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESA RESB ETMFCNEN

RESA : ETM Resource A Trace Enable
bits : 0 - 6 (7 bit)
access : read-write

RESB : ETM Resource B Trace Enable
bits : 7 - 13 (7 bit)
access : read-write

ETMFCNEN : ETM Function Trace Enable
bits : 14 - 16 (3 bit)
access : read-write


ETMTRACEIDR

CoreSight Trace ID Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMTRACEIDR ETMTRACEIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACEID

TRACEID : Trace ID
bits : 0 - 6 (7 bit)
access : read-write


ETMIDR2

ETM ID Register 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMIDR2 ETMIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFE SWP

RFE : RFE Transfer Order
bits : 0 - 0 (1 bit)
access : read-only

SWP : SWP Transfer Order
bits : 1 - 1 (1 bit)
access : read-only


ETMTECR1

ETM Trace control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMTECR1 ETMTECR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRCMP MEMMAP INCEXCTL TCE

ADRCMP : Address Comparator
bits : 0 - 7 (8 bit)
access : read-write

MEMMAP : Memmap
bits : 8 - 23 (16 bit)
access : read-write

INCEXCTL : Trace Include/Exclude Flag
bits : 24 - 24 (1 bit)
access : read-write

TCE : Trace Control Enable
bits : 25 - 25 (1 bit)
access : read-write


ETMFFLR

ETM Fifo Full Level Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMFFLR ETMFFLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYTENUM

BYTENUM : Bytes left in FIFO
bits : 0 - 7 (8 bit)
access : read-write


ETMPDSR

Device Power-down Status Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMPDSR ETMPDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETMUP

ETMUP : ETM Powered Up
bits : 0 - 0 (1 bit)
access : read-only


ETMCCR

Configuration Code Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMCCR ETMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRCMPPAIR DATACMPNUM MMDECCNT COUNTNUM SEQPRES EXTINPNUM EXTOUTNUM FIFOFULLPRES IDCOMPNUM TRACESS MMACCESS ETMID

ADRCMPPAIR : Number of Address Comparator Pairs
bits : 0 - 3 (4 bit)
access : read-only

DATACMPNUM : Number of Data Value Comparators
bits : 4 - 7 (4 bit)
access : read-only

MMDECCNT : Number of Memeory Map Decoders
bits : 8 - 12 (5 bit)
access : read-only

COUNTNUM : Number of Counters
bits : 13 - 15 (3 bit)
access : read-only

SEQPRES : Sequencer Present
bits : 16 - 16 (1 bit)
access : read-only

EXTINPNUM : Number of External Inputs
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

0x00000000 : ZERO

Zero inputs presents

0x00000001 : ONE

One inputs presents

0x00000002 : TWO

Two inputs presents

End of enumeration elements list.

EXTOUTNUM : Number of External Output
bits : 20 - 22 (3 bit)
access : read-only

FIFOFULLPRES : FIFIO FULL present
bits : 23 - 23 (1 bit)
access : read-only

IDCOMPNUM : Number of context ID Comparators
bits : 24 - 25 (2 bit)
access : read-only

TRACESS : Trace Start/Stop Block Present
bits : 26 - 26 (1 bit)
access : read-only

MMACCESS : Coprocessor and Memeory Access
bits : 27 - 27 (1 bit)
access : read-only

ETMID : ETM ID Register Present
bits : 31 - 31 (1 bit)
access : read-only


ETMTRIGGER

ETM Trigger Event Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMTRIGGER ETMTRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESA RESB ETMFCN

RESA : ETM Resource A
bits : 0 - 6 (7 bit)
access : read-write

RESB : ETM Resource B
bits : 7 - 13 (7 bit)
access : read-write

ETMFCN : ETM Function
bits : 14 - 16 (3 bit)
access : read-write


ETMISCIN

Integration Test Miscellaneous Inputs Register
address_offset : 0xEE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMISCIN ETMISCIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTIN COREHALT

EXTIN : EXTIN Value
bits : 0 - 1 (2 bit)
access : read-write

COREHALT : Core Halt
bits : 4 - 4 (1 bit)
access : read-write


ITTRIGOUT

Integration Test Trigger Out Register
address_offset : 0xEE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITTRIGOUT ITTRIGOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIGGEROUT

TRIGGEROUT : Trigger output value
bits : 0 - 0 (1 bit)
access : read-write


ETMITATBCTR2

ETM Integration Test ATB Control 2 Register
address_offset : 0xEF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMITATBCTR2 ETMITATBCTR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATREADY

ATREADY : ATREADY Input Value
bits : 0 - 0 (1 bit)
access : read-only


ETMITATBCTR0

ETM Integration Test ATB Control 0 Register
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMITATBCTR0 ETMITATBCTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATVALID

ATVALID : ATVALID Output Value
bits : 0 - 0 (1 bit)
access : read-write


ETMITCTRL

ETM Integration Control Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMITCTRL ETMITCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITEN

ITEN : Integration Mode Enable
bits : 0 - 0 (1 bit)
access : read-write


ETMCLAIMSET

ETM Claim Tag Set Register
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMCLAIMSET ETMCLAIMSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETTAG

SETTAG : Tag Bits
bits : 0 - 7 (8 bit)
access : read-write


ETMCLAIMCLR

ETM Claim Tag Clear Register
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMCLAIMCLR ETMCLAIMCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRTAG

CLRTAG : Tag Bits
bits : 0 - 0 (1 bit)
access : read-write


ETMLAR

ETM Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETMLAR ETMLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Key Value
bits : 0 - 0 (1 bit)
access : read-write


ETMLSR

Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMLSR ETMLSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKIMP LOCKED

LOCKIMP : ETM Locking Implemented
bits : 0 - 0 (1 bit)
access : read-only

LOCKED : ETM locked
bits : 1 - 1 (1 bit)
access : read-only


ETMAUTHSTATUS

ETM Authentication Status Register
address_offset : 0xFB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMAUTHSTATUS ETMAUTHSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONSECINVDBG NONSECNONINVDBG SECINVDBG SECNONINVDBG

NONSECINVDBG : Non-secure invasive Debug Status
bits : 0 - 1 (2 bit)
access : read-only

NONSECNONINVDBG : Non-secure non-invasive Debug Status
bits : 2 - 3 (2 bit)
access : read-only

Enumeration:

0x00000002 : DISABLE

Non-secure non-invasive debug disable

0x00000003 : ENABLE

Non-secure non-invasive debug enable

End of enumeration elements list.

SECINVDBG : Secure invasive Debug Status
bits : 4 - 5 (2 bit)
access : read-only

SECNONINVDBG : Secure non-invasive Debug Status
bits : 6 - 7 (2 bit)
access : read-only


ETMDEVTYPE

CoreSight Device Type Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMDEVTYPE ETMDEVTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACESRC PROCTRACE

TRACESRC : Trace Source
bits : 0 - 3 (4 bit)
access : read-only

PROCTRACE : Processor Trace
bits : 4 - 7 (4 bit)
access : read-only


ETMPIDR4

Peripheral ID4 Register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR4 ETMPIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONTCODE COUNT

CONTCODE : JEP106 Continuation Code
bits : 0 - 3 (4 bit)
access : read-only

COUNT : 4KB Count
bits : 4 - 7 (4 bit)
access : read-only


ETMPIDR5

Peripheral ID5 Register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR5 ETMPIDR5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETMPIDR6

Peripheral ID6 Register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR6 ETMPIDR6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETMPIDR7

Peripheral ID7 Register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR7 ETMPIDR7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETMPIDR0

Peripheral ID0 Register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR0 ETMPIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM

PARTNUM : Part Number
bits : 0 - 7 (8 bit)
access : read-only


ETMPIDR1

Peripheral ID1 Register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR1 ETMPIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM IDCODE

PARTNUM : Part Number
bits : 0 - 3 (4 bit)
access : read-only

IDCODE : JEP106 Identity Code
bits : 4 - 7 (4 bit)
access : read-only


ETMPIDR2

Peripheral ID2 Register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR2 ETMPIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDCODE ALWAYS1 REV

IDCODE : JEP106 Identity Code
bits : 0 - 2 (3 bit)
access : read-only

ALWAYS1 : Always 1
bits : 3 - 3 (1 bit)
access : read-only

REV : Revision
bits : 4 - 7 (4 bit)
access : read-only


ETMPIDR3

Peripheral ID3 Register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMPIDR3 ETMPIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUSTMOD REVAND

CUSTMOD : Customer Modified
bits : 0 - 3 (4 bit)
access : read-only

REVAND : RevAnd
bits : 4 - 7 (4 bit)
access : read-only


ETMCIDR0

Component ID0 Register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMCIDR0 ETMCIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMB

PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only


ETMCIDR1

Component ID1 Register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMCIDR1 ETMCIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMB

PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only


ETMCIDR2

Component ID2 Register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMCIDR2 ETMCIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMB

PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only


ETMCIDR3

Component ID3 Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETMCIDR3 ETMCIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMB

PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only



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