\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
EXTI rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
TR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
TR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
TR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
TR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
TR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
TR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
TR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
TR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
TR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
TR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
TR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
TR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
TR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
TR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
TR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
TR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
TR17 : Rising trigger event configuration bit of Configurable Event input
bits : 17 - 17 (1 bit)
TR18 : Rising trigger event configuration bit of Configurable Event input
bits : 18 - 18 (1 bit)
TR19 : Rising trigger event configuration bit of Configurable Event input
bits : 19 - 19 (1 bit)
TR20 : Rising trigger event configuration bit of Configurable Event input
bits : 20 - 20 (1 bit)
TR21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 21 (1 bit)
EXTI D3 pending clear selection register low
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS0 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 0 - 1 (2 bit)
PCS1 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 2 - 3 (2 bit)
PCS2 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 4 - 5 (2 bit)
PCS3 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 6 - 7 (2 bit)
PCS4 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 8 - 9 (2 bit)
PCS5 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 10 - 11 (2 bit)
PCS6 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 12 - 13 (2 bit)
PCS7 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 14 - 15 (2 bit)
PCS8 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 16 - 17 (2 bit)
PCS9 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 18 - 19 (2 bit)
PCS10 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 20 - 21 (2 bit)
PCS11 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 22 - 23 (2 bit)
PCS12 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 24 - 25 (2 bit)
PCS13 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 26 - 27 (2 bit)
PCS14 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 28 - 29 (2 bit)
PCS15 : D3 Pending request clear input signal selection on Event input x = truncate (n/2)
bits : 30 - 31 (2 bit)
EXTI D3 pending clear selection register high
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS19 : D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)
bits : 6 - 7 (2 bit)
PCS20 : D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)
bits : 8 - 9 (2 bit)
PCS21 : D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)
bits : 10 - 11 (2 bit)
PCS25 : D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)
bits : 18 - 19 (2 bit)
EXTI rising trigger selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR49 : Rising trigger event configuration bit of Configurable Event input x+32
bits : 17 - 17 (1 bit)
TR51 : Rising trigger event configuration bit of Configurable Event input x+32
bits : 19 - 19 (1 bit)
EXTI falling trigger selection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR49 : Falling trigger event configuration bit of Configurable Event input x+32
bits : 17 - 17 (1 bit)
TR51 : Falling trigger event configuration bit of Configurable Event input x+32
bits : 19 - 19 (1 bit)
EXTI software interrupt event register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIER49 : Software interrupt on line x+32
bits : 17 - 17 (1 bit)
SWIER51 : Software interrupt on line x+32
bits : 19 - 19 (1 bit)
EXTI D3 pending mask register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR34 : D3 Pending Mask on Event input x+32
bits : 2 - 2 (1 bit)
MR35 : D3 Pending Mask on Event input x+32
bits : 3 - 3 (1 bit)
MR41 : D3 Pending Mask on Event input x+32
bits : 9 - 9 (1 bit)
MR48 : D3 Pending Mask on Event input x+32
bits : 16 - 16 (1 bit)
MR49 : D3 Pending Mask on Event input x+32
bits : 17 - 17 (1 bit)
MR50 : D3 Pending Mask on Event input x+32
bits : 18 - 18 (1 bit)
MR51 : D3 Pending Mask on Event input x+32
bits : 19 - 19 (1 bit)
MR52 : D3 Pending Mask on Event input x+32
bits : 20 - 20 (1 bit)
MR53 : D3 Pending Mask on Event input x+32
bits : 21 - 21 (1 bit)
EXTI D3 pending clear selection register low
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS34 : D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)
bits : 4 - 5 (2 bit)
PCS35 : D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)
bits : 6 - 7 (2 bit)
PCS41 : D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)
bits : 18 - 19 (2 bit)
EXTI D3 pending clear selection register high
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS48 : Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
bits : 0 - 1 (2 bit)
PCS49 : Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
bits : 2 - 3 (2 bit)
PCS50 : Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
bits : 4 - 5 (2 bit)
PCS51 : Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
bits : 6 - 7 (2 bit)
PCS52 : Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
bits : 8 - 9 (2 bit)
PCS53 : Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
bits : 10 - 11 (2 bit)
EXTI falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
TR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
TR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
TR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
TR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
TR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
TR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
TR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
TR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
TR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
TR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
TR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
TR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
TR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
TR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
TR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
TR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
TR17 : Rising trigger event configuration bit of Configurable Event input
bits : 17 - 17 (1 bit)
TR18 : Rising trigger event configuration bit of Configurable Event input
bits : 18 - 18 (1 bit)
TR19 : Rising trigger event configuration bit of Configurable Event input
bits : 19 - 19 (1 bit)
TR20 : Rising trigger event configuration bit of Configurable Event input
bits : 20 - 20 (1 bit)
TR21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 21 (1 bit)
EXTI rising trigger selection register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR82 : Rising trigger event configuration bit of Configurable Event input x+64
bits : 18 - 18 (1 bit)
TR84 : Rising trigger event configuration bit of Configurable Event input x+64
bits : 20 - 20 (1 bit)
TR85 : Rising trigger event configuration bit of Configurable Event input x+64
bits : 21 - 21 (1 bit)
TR86 : Rising trigger event configuration bit of Configurable Event input x+64
bits : 22 - 22 (1 bit)
EXTI falling trigger selection register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR82 : Falling trigger event configuration bit of Configurable Event input x+64
bits : 18 - 18 (1 bit)
TR84 : Falling trigger event configuration bit of Configurable Event input x+64
bits : 20 - 20 (1 bit)
TR85 : Falling trigger event configuration bit of Configurable Event input x+64
bits : 21 - 21 (1 bit)
TR86 : Falling trigger event configuration bit of Configurable Event input x+64
bits : 22 - 22 (1 bit)
EXTI software interrupt event register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIER82 : Software interrupt on line x+64
bits : 18 - 18 (1 bit)
SWIER84 : Software interrupt on line x+64
bits : 20 - 20 (1 bit)
SWIER85 : Software interrupt on line x+64
bits : 21 - 21 (1 bit)
SWIER86 : Software interrupt on line x+64
bits : 22 - 22 (1 bit)
EXTI D3 pending mask register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR88 : D3 Pending Mask on Event input x+64
bits : 24 - 24 (1 bit)
EXTI D3 pending clear selection register high
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS88 : D3 Pending request clear input signal selection on Event input x= truncate N+160/2
bits : 18 - 19 (2 bit)
EXTI software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIER0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
SWIER1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
SWIER2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
SWIER3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
SWIER4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
SWIER5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
SWIER6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
SWIER7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
SWIER8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
SWIER9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
SWIER10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
SWIER11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
SWIER12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
SWIER13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
SWIER14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
SWIER15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
SWIER16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
SWIER17 : Rising trigger event configuration bit of Configurable Event input
bits : 17 - 17 (1 bit)
SWIER18 : Rising trigger event configuration bit of Configurable Event input
bits : 18 - 18 (1 bit)
SWIER19 : Rising trigger event configuration bit of Configurable Event input
bits : 19 - 19 (1 bit)
SWIER20 : Rising trigger event configuration bit of Configurable Event input
bits : 20 - 20 (1 bit)
SWIER21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 21 (1 bit)
EXTI interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
MR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
MR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
MR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
MR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
MR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
MR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
MR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
MR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
MR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
MR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
MR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
MR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
MR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
MR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
MR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
MR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
MR17 : Rising trigger event configuration bit of Configurable Event input
bits : 17 - 17 (1 bit)
MR18 : Rising trigger event configuration bit of Configurable Event input
bits : 18 - 18 (1 bit)
MR19 : Rising trigger event configuration bit of Configurable Event input
bits : 19 - 19 (1 bit)
MR20 : Rising trigger event configuration bit of Configurable Event input
bits : 20 - 20 (1 bit)
MR21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 21 (1 bit)
MR22 : Rising trigger event configuration bit of Configurable Event input
bits : 22 - 22 (1 bit)
MR23 : Rising trigger event configuration bit of Configurable Event input
bits : 23 - 23 (1 bit)
MR24 : Rising trigger event configuration bit of Configurable Event input
bits : 24 - 24 (1 bit)
MR25 : Rising trigger event configuration bit of Configurable Event input
bits : 25 - 25 (1 bit)
MR26 : Rising trigger event configuration bit of Configurable Event input
bits : 26 - 26 (1 bit)
MR27 : Rising trigger event configuration bit of Configurable Event input
bits : 27 - 27 (1 bit)
MR28 : Rising trigger event configuration bit of Configurable Event input
bits : 28 - 28 (1 bit)
MR29 : Rising trigger event configuration bit of Configurable Event input
bits : 29 - 29 (1 bit)
MR30 : Rising trigger event configuration bit of Configurable Event input
bits : 30 - 30 (1 bit)
MR31 : Rising trigger event configuration bit of Configurable Event input
bits : 31 - 31 (1 bit)
EXTI event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : CPU Event mask on Event input x
bits : 0 - 0 (1 bit)
MR1 : CPU Event mask on Event input x
bits : 1 - 1 (1 bit)
MR2 : CPU Event mask on Event input x
bits : 2 - 2 (1 bit)
MR3 : CPU Event mask on Event input x
bits : 3 - 3 (1 bit)
MR4 : CPU Event mask on Event input x
bits : 4 - 4 (1 bit)
MR5 : CPU Event mask on Event input x
bits : 5 - 5 (1 bit)
MR6 : CPU Event mask on Event input x
bits : 6 - 6 (1 bit)
MR7 : CPU Event mask on Event input x
bits : 7 - 7 (1 bit)
MR8 : CPU Event mask on Event input x
bits : 8 - 8 (1 bit)
MR9 : CPU Event mask on Event input x
bits : 9 - 9 (1 bit)
MR10 : CPU Event mask on Event input x
bits : 10 - 10 (1 bit)
MR11 : CPU Event mask on Event input x
bits : 11 - 11 (1 bit)
MR12 : CPU Event mask on Event input x
bits : 12 - 12 (1 bit)
MR13 : CPU Event mask on Event input x
bits : 13 - 13 (1 bit)
MR14 : CPU Event mask on Event input x
bits : 14 - 14 (1 bit)
MR15 : CPU Event mask on Event input x
bits : 15 - 15 (1 bit)
MR16 : CPU Event mask on Event input x
bits : 16 - 16 (1 bit)
MR17 : CPU Event mask on Event input x
bits : 17 - 17 (1 bit)
MR18 : CPU Event mask on Event input x
bits : 18 - 18 (1 bit)
MR19 : CPU Event mask on Event input x
bits : 19 - 19 (1 bit)
MR20 : CPU Event mask on Event input x
bits : 20 - 20 (1 bit)
MR21 : CPU Event mask on Event input x
bits : 21 - 21 (1 bit)
MR22 : CPU Event mask on Event input x
bits : 22 - 22 (1 bit)
MR23 : CPU Event mask on Event input x
bits : 23 - 23 (1 bit)
MR24 : CPU Event mask on Event input x
bits : 24 - 24 (1 bit)
MR25 : CPU Event mask on Event input x
bits : 25 - 25 (1 bit)
MR26 : CPU Event mask on Event input x
bits : 26 - 26 (1 bit)
MR27 : CPU Event mask on Event input x
bits : 27 - 27 (1 bit)
MR28 : CPU Event mask on Event input x
bits : 28 - 28 (1 bit)
MR29 : CPU Event mask on Event input x
bits : 29 - 29 (1 bit)
MR30 : CPU Event mask on Event input x
bits : 30 - 30 (1 bit)
MR31 : CPU Event mask on Event input x
bits : 31 - 31 (1 bit)
EXTI pending register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR0 : CPU Event mask on Event input x
bits : 0 - 0 (1 bit)
PR1 : CPU Event mask on Event input x
bits : 1 - 1 (1 bit)
PR2 : CPU Event mask on Event input x
bits : 2 - 2 (1 bit)
PR3 : CPU Event mask on Event input x
bits : 3 - 3 (1 bit)
PR4 : CPU Event mask on Event input x
bits : 4 - 4 (1 bit)
PR5 : CPU Event mask on Event input x
bits : 5 - 5 (1 bit)
PR6 : CPU Event mask on Event input x
bits : 6 - 6 (1 bit)
PR7 : CPU Event mask on Event input x
bits : 7 - 7 (1 bit)
PR8 : CPU Event mask on Event input x
bits : 8 - 8 (1 bit)
PR9 : CPU Event mask on Event input x
bits : 9 - 9 (1 bit)
PR10 : CPU Event mask on Event input x
bits : 10 - 10 (1 bit)
PR11 : CPU Event mask on Event input x
bits : 11 - 11 (1 bit)
PR12 : CPU Event mask on Event input x
bits : 12 - 12 (1 bit)
PR13 : CPU Event mask on Event input x
bits : 13 - 13 (1 bit)
PR14 : CPU Event mask on Event input x
bits : 14 - 14 (1 bit)
PR15 : CPU Event mask on Event input x
bits : 15 - 15 (1 bit)
PR16 : CPU Event mask on Event input x
bits : 16 - 16 (1 bit)
PR17 : CPU Event mask on Event input x
bits : 17 - 17 (1 bit)
PR18 : CPU Event mask on Event input x
bits : 18 - 18 (1 bit)
PR19 : CPU Event mask on Event input x
bits : 19 - 19 (1 bit)
PR20 : CPU Event mask on Event input x
bits : 20 - 20 (1 bit)
PR21 : CPU Event mask on Event input x
bits : 21 - 21 (1 bit)
EXTI interrupt mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : CPU Interrupt Mask on Direct Event input x+32
bits : 0 - 0 (1 bit)
MR1 : CPU Interrupt Mask on Direct Event input x+32
bits : 1 - 1 (1 bit)
MR2 : CPU Interrupt Mask on Direct Event input x+32
bits : 2 - 2 (1 bit)
MR3 : CPU Interrupt Mask on Direct Event input x+32
bits : 3 - 3 (1 bit)
MR4 : CPU Interrupt Mask on Direct Event input x+32
bits : 4 - 4 (1 bit)
MR5 : CPU Interrupt Mask on Direct Event input x+32
bits : 5 - 5 (1 bit)
MR6 : CPU Interrupt Mask on Direct Event input x+32
bits : 6 - 6 (1 bit)
MR7 : CPU Interrupt Mask on Direct Event input x+32
bits : 7 - 7 (1 bit)
MR8 : CPU Interrupt Mask on Direct Event input x+32
bits : 8 - 8 (1 bit)
MR9 : CPU Interrupt Mask on Direct Event input x+32
bits : 9 - 9 (1 bit)
MR10 : CPU Interrupt Mask on Direct Event input x+32
bits : 10 - 10 (1 bit)
MR11 : CPU Interrupt Mask on Direct Event input x+32
bits : 11 - 11 (1 bit)
MR12 : CPU Interrupt Mask on Direct Event input x+32
bits : 12 - 12 (1 bit)
MR14 : CPU Interrupt Mask on Direct Event input x+32
bits : 14 - 14 (1 bit)
MR15 : CPU Interrupt Mask on Direct Event input x+32
bits : 15 - 15 (1 bit)
MR16 : CPU Interrupt Mask on Direct Event input x+32
bits : 16 - 16 (1 bit)
MR17 : CPU Interrupt Mask on Direct Event input x+32
bits : 17 - 17 (1 bit)
MR18 : CPU Interrupt Mask on Direct Event input x+32
bits : 18 - 18 (1 bit)
MR19 : CPU Interrupt Mask on Direct Event input x+32
bits : 19 - 19 (1 bit)
MR20 : CPU Interrupt Mask on Direct Event input x+32
bits : 20 - 20 (1 bit)
MR21 : CPU Interrupt Mask on Direct Event input x+32
bits : 21 - 21 (1 bit)
MR22 : CPU Interrupt Mask on Direct Event input x+32
bits : 22 - 22 (1 bit)
MR23 : CPU Interrupt Mask on Direct Event input x+32
bits : 23 - 23 (1 bit)
MR24 : CPU Interrupt Mask on Direct Event input x+32
bits : 24 - 24 (1 bit)
MR25 : CPU Interrupt Mask on Direct Event input x+32
bits : 25 - 25 (1 bit)
MR26 : CPU Interrupt Mask on Direct Event input x+32
bits : 26 - 26 (1 bit)
MR27 : CPU Interrupt Mask on Direct Event input x+32
bits : 27 - 27 (1 bit)
MR28 : CPU Interrupt Mask on Direct Event input x+32
bits : 28 - 28 (1 bit)
MR29 : CPU Interrupt Mask on Direct Event input x+32
bits : 29 - 29 (1 bit)
MR30 : CPU Interrupt Mask on Direct Event input x+32
bits : 30 - 30 (1 bit)
MR31 : CPU Interrupt Mask on Direct Event input x+32
bits : 31 - 31 (1 bit)
EXTI event mask register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR32 : CPU Interrupt Mask on Direct Event input x+32
bits : 0 - 0 (1 bit)
MR33 : CPU Interrupt Mask on Direct Event input x+32
bits : 1 - 1 (1 bit)
MR34 : CPU Interrupt Mask on Direct Event input x+32
bits : 2 - 2 (1 bit)
MR35 : CPU Interrupt Mask on Direct Event input x+32
bits : 3 - 3 (1 bit)
MR36 : CPU Interrupt Mask on Direct Event input x+32
bits : 4 - 4 (1 bit)
MR37 : CPU Interrupt Mask on Direct Event input x+32
bits : 5 - 5 (1 bit)
MR38 : CPU Interrupt Mask on Direct Event input x+32
bits : 6 - 6 (1 bit)
MR39 : CPU Interrupt Mask on Direct Event input x+32
bits : 7 - 7 (1 bit)
MR40 : CPU Interrupt Mask on Direct Event input x+32
bits : 8 - 8 (1 bit)
MR41 : CPU Interrupt Mask on Direct Event input x+32
bits : 9 - 9 (1 bit)
MR42 : CPU Interrupt Mask on Direct Event input x+32
bits : 10 - 10 (1 bit)
MR43 : CPU Interrupt Mask on Direct Event input x+32
bits : 11 - 11 (1 bit)
MR44 : CPU Interrupt Mask on Direct Event input x+32
bits : 12 - 12 (1 bit)
MR46 : CPU Interrupt Mask on Direct Event input x+32
bits : 14 - 14 (1 bit)
MR47 : CPU Interrupt Mask on Direct Event input x+32
bits : 15 - 15 (1 bit)
MR48 : CPU Interrupt Mask on Direct Event input x+32
bits : 16 - 16 (1 bit)
MR49 : CPU Interrupt Mask on Direct Event input x+32
bits : 17 - 17 (1 bit)
MR50 : CPU Interrupt Mask on Direct Event input x+32
bits : 18 - 18 (1 bit)
MR51 : CPU Interrupt Mask on Direct Event input x+32
bits : 19 - 19 (1 bit)
MR52 : CPU Interrupt Mask on Direct Event input x+32
bits : 20 - 20 (1 bit)
MR53 : CPU Interrupt Mask on Direct Event input x+32
bits : 21 - 21 (1 bit)
MR54 : CPU Interrupt Mask on Direct Event input x+32
bits : 22 - 22 (1 bit)
MR55 : CPU Interrupt Mask on Direct Event input x+32
bits : 23 - 23 (1 bit)
MR56 : CPU Interrupt Mask on Direct Event input x+32
bits : 24 - 24 (1 bit)
MR57 : CPU Interrupt Mask on Direct Event input x+32
bits : 25 - 25 (1 bit)
MR58 : CPU Interrupt Mask on Direct Event input x+32
bits : 26 - 26 (1 bit)
MR59 : CPU Interrupt Mask on Direct Event input x+32
bits : 27 - 27 (1 bit)
MR60 : CPU Interrupt Mask on Direct Event input x+32
bits : 28 - 28 (1 bit)
MR61 : CPU Interrupt Mask on Direct Event input x+32
bits : 29 - 29 (1 bit)
MR62 : CPU Interrupt Mask on Direct Event input x+32
bits : 30 - 30 (1 bit)
MR63 : CPU Interrupt Mask on Direct Event input x+32
bits : 31 - 31 (1 bit)
EXTI pending register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PR49 : Configurable event inputs x+32 Pending bit
bits : 17 - 17 (1 bit)
PR51 : Configurable event inputs x+32 Pending bit
bits : 19 - 19 (1 bit)
EXTI interrupt mask register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MR64 : CPU Interrupt Mask on Direct Event input x+64
bits : 0 - 0 (1 bit)
MR65 : CPU Interrupt Mask on Direct Event input x+64
bits : 1 - 1 (1 bit)
MR66 : CPU Interrupt Mask on Direct Event input x+64
bits : 2 - 2 (1 bit)
MR67 : CPU Interrupt Mask on Direct Event input x+64
bits : 3 - 3 (1 bit)
MR68 : CPU Interrupt Mask on Direct Event input x+64
bits : 4 - 4 (1 bit)
MR69 : CPU Interrupt Mask on Direct Event input x+64
bits : 5 - 5 (1 bit)
MR70 : CPU Interrupt Mask on Direct Event input x+64
bits : 6 - 6 (1 bit)
MR71 : CPU Interrupt Mask on Direct Event input x+64
bits : 7 - 7 (1 bit)
MR72 : CPU Interrupt Mask on Direct Event input x+64
bits : 8 - 8 (1 bit)
MR73 : CPU Interrupt Mask on Direct Event input x+64
bits : 9 - 9 (1 bit)
MR74 : CPU Interrupt Mask on Direct Event input x+64
bits : 10 - 10 (1 bit)
MR75 : CPU Interrupt Mask on Direct Event input x+64
bits : 11 - 11 (1 bit)
MR76 : CPU Interrupt Mask on Direct Event input x+64
bits : 12 - 12 (1 bit)
MR77 : CPU Interrupt Mask on Direct Event input x+64
bits : 13 - 13 (1 bit)
MR78 : CPU Interrupt Mask on Direct Event input x+64
bits : 14 - 14 (1 bit)
MR79 : CPU Interrupt Mask on Direct Event input x+64
bits : 15 - 15 (1 bit)
MR80 : CPU Interrupt Mask on Direct Event input x+64
bits : 16 - 16 (1 bit)
MR82 : CPU Interrupt Mask on Direct Event input x+64
bits : 18 - 18 (1 bit)
MR84 : CPU Interrupt Mask on Direct Event input x+64
bits : 20 - 20 (1 bit)
MR85 : CPU Interrupt Mask on Direct Event input x+64
bits : 21 - 21 (1 bit)
MR86 : CPU Interrupt Mask on Direct Event input x+64
bits : 22 - 22 (1 bit)
MR87 : CPU Interrupt Mask on Direct Event input x+64
bits : 23 - 23 (1 bit)
MR88 : CPU Interrupt Mask on Direct Event input x+64
bits : 24 - 24 (1 bit)
EXTI event mask register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MR64 : CPU Event mask on Event input x+64
bits : 0 - 0 (1 bit)
MR65 : CPU Event mask on Event input x+64
bits : 1 - 1 (1 bit)
MR66 : CPU Event mask on Event input x+64
bits : 2 - 2 (1 bit)
MR67 : CPU Event mask on Event input x+64
bits : 3 - 3 (1 bit)
MR68 : CPU Event mask on Event input x+64
bits : 4 - 4 (1 bit)
MR69 : CPU Event mask on Event input x+64
bits : 5 - 5 (1 bit)
MR70 : CPU Event mask on Event input x+64
bits : 6 - 6 (1 bit)
MR71 : CPU Event mask on Event input x+64
bits : 7 - 7 (1 bit)
MR72 : CPU Event mask on Event input x+64
bits : 8 - 8 (1 bit)
MR73 : CPU Event mask on Event input x+64
bits : 9 - 9 (1 bit)
MR74 : CPU Event mask on Event input x+64
bits : 10 - 10 (1 bit)
MR75 : CPU Event mask on Event input x+64
bits : 11 - 11 (1 bit)
MR76 : CPU Event mask on Event input x+64
bits : 12 - 12 (1 bit)
MR77 : CPU Event mask on Event input x+64
bits : 13 - 13 (1 bit)
MR78 : CPU Event mask on Event input x+64
bits : 14 - 14 (1 bit)
MR79 : CPU Event mask on Event input x+64
bits : 15 - 15 (1 bit)
MR80 : CPU Event mask on Event input x+64
bits : 16 - 16 (1 bit)
MR82 : CPU Event mask on Event input x+64
bits : 18 - 18 (1 bit)
MR84 : CPU Event mask on Event input x+64
bits : 20 - 20 (1 bit)
MR85 : CPU Event mask on Event input x+64
bits : 21 - 21 (1 bit)
MR86 : CPU Event mask on Event input x+64
bits : 22 - 22 (1 bit)
MR87 : CPU Event mask on Event input x+64
bits : 23 - 23 (1 bit)
MR88 : CPU Event mask on Event input x+64
bits : 24 - 24 (1 bit)
EXTI pending register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PR82 : Configurable event inputs x+64 Pending bit
bits : 18 - 18 (1 bit)
PR84 : Configurable event inputs x+64 Pending bit
bits : 20 - 20 (1 bit)
PR85 : Configurable event inputs x+64 Pending bit
bits : 21 - 21 (1 bit)
PR86 : Configurable event inputs x+64 Pending bit
bits : 22 - 22 (1 bit)
EXTI D3 pending mask register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
MR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
MR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
MR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
MR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
MR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
MR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
MR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
MR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
MR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
MR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
MR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
MR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
MR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
MR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
MR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
MR19 : Rising trigger event configuration bit of Configurable Event input
bits : 19 - 19 (1 bit)
MR20 : Rising trigger event configuration bit of Configurable Event input
bits : 20 - 20 (1 bit)
MR21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 21 (1 bit)
MR25 : Rising trigger event configuration bit of Configurable Event input
bits : 25 - 25 (1 bit)
EXTI interrupt mask register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
MR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
MR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
MR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
MR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
MR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
MR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
MR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
MR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
MR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
MR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
MR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
MR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
MR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
MR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
MR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
MR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
MR17 : Rising trigger event configuration bit of Configurable Event input
bits : 17 - 17 (1 bit)
MR18 : Rising trigger event configuration bit of Configurable Event input
bits : 18 - 18 (1 bit)
MR19 : Rising trigger event configuration bit of Configurable Event input
bits : 19 - 19 (1 bit)
MR20 : Rising trigger event configuration bit of Configurable Event input
bits : 20 - 20 (1 bit)
MR21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 21 (1 bit)
MR22 : Rising trigger event configuration bit of Configurable Event input
bits : 22 - 22 (1 bit)
MR23 : Rising trigger event configuration bit of Configurable Event input
bits : 23 - 23 (1 bit)
MR24 : Rising trigger event configuration bit of Configurable Event input
bits : 24 - 24 (1 bit)
MR25 : Rising trigger event configuration bit of Configurable Event input
bits : 25 - 25 (1 bit)
MR26 : Rising trigger event configuration bit of Configurable Event input
bits : 26 - 26 (1 bit)
MR27 : Rising trigger event configuration bit of Configurable Event input
bits : 27 - 27 (1 bit)
MR28 : Rising trigger event configuration bit of Configurable Event input
bits : 28 - 28 (1 bit)
MR29 : Rising trigger event configuration bit of Configurable Event input
bits : 29 - 29 (1 bit)
MR30 : Rising trigger event configuration bit of Configurable Event input
bits : 30 - 30 (1 bit)
MR31 : Rising trigger event configuration bit of Configurable Event input
bits : 31 - 31 (1 bit)
EXTI event mask register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : CPU Event mask on Event input x
bits : 0 - 0 (1 bit)
MR1 : CPU Event mask on Event input x
bits : 1 - 1 (1 bit)
MR2 : CPU Event mask on Event input x
bits : 2 - 2 (1 bit)
MR3 : CPU Event mask on Event input x
bits : 3 - 3 (1 bit)
MR4 : CPU Event mask on Event input x
bits : 4 - 4 (1 bit)
MR5 : CPU Event mask on Event input x
bits : 5 - 5 (1 bit)
MR6 : CPU Event mask on Event input x
bits : 6 - 6 (1 bit)
MR7 : CPU Event mask on Event input x
bits : 7 - 7 (1 bit)
MR8 : CPU Event mask on Event input x
bits : 8 - 8 (1 bit)
MR9 : CPU Event mask on Event input x
bits : 9 - 9 (1 bit)
MR10 : CPU Event mask on Event input x
bits : 10 - 10 (1 bit)
MR11 : CPU Event mask on Event input x
bits : 11 - 11 (1 bit)
MR12 : CPU Event mask on Event input x
bits : 12 - 12 (1 bit)
MR13 : CPU Event mask on Event input x
bits : 13 - 13 (1 bit)
MR14 : CPU Event mask on Event input x
bits : 14 - 14 (1 bit)
MR15 : CPU Event mask on Event input x
bits : 15 - 15 (1 bit)
MR16 : CPU Event mask on Event input x
bits : 16 - 16 (1 bit)
MR17 : CPU Event mask on Event input x
bits : 17 - 17 (1 bit)
MR18 : CPU Event mask on Event input x
bits : 18 - 18 (1 bit)
MR19 : CPU Event mask on Event input x
bits : 19 - 19 (1 bit)
MR20 : CPU Event mask on Event input x
bits : 20 - 20 (1 bit)
MR21 : CPU Event mask on Event input x
bits : 21 - 21 (1 bit)
MR22 : CPU Event mask on Event input x
bits : 22 - 22 (1 bit)
MR23 : CPU Event mask on Event input x
bits : 23 - 23 (1 bit)
MR24 : CPU Event mask on Event input x
bits : 24 - 24 (1 bit)
MR25 : CPU Event mask on Event input x
bits : 25 - 25 (1 bit)
MR26 : CPU Event mask on Event input x
bits : 26 - 26 (1 bit)
MR27 : CPU Event mask on Event input x
bits : 27 - 27 (1 bit)
MR28 : CPU Event mask on Event input x
bits : 28 - 28 (1 bit)
MR29 : CPU Event mask on Event input x
bits : 29 - 29 (1 bit)
MR30 : CPU Event mask on Event input x
bits : 30 - 30 (1 bit)
MR31 : CPU Event mask on Event input x
bits : 31 - 31 (1 bit)
EXTI pending register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR0 : CPU Event mask on Event input x
bits : 0 - 0 (1 bit)
PR1 : CPU Event mask on Event input x
bits : 1 - 1 (1 bit)
PR2 : CPU Event mask on Event input x
bits : 2 - 2 (1 bit)
PR3 : CPU Event mask on Event input x
bits : 3 - 3 (1 bit)
PR4 : CPU Event mask on Event input x
bits : 4 - 4 (1 bit)
PR5 : CPU Event mask on Event input x
bits : 5 - 5 (1 bit)
PR6 : CPU Event mask on Event input x
bits : 6 - 6 (1 bit)
PR7 : CPU Event mask on Event input x
bits : 7 - 7 (1 bit)
PR8 : CPU Event mask on Event input x
bits : 8 - 8 (1 bit)
PR9 : CPU Event mask on Event input x
bits : 9 - 9 (1 bit)
PR10 : CPU Event mask on Event input x
bits : 10 - 10 (1 bit)
PR11 : CPU Event mask on Event input x
bits : 11 - 11 (1 bit)
PR12 : CPU Event mask on Event input x
bits : 12 - 12 (1 bit)
PR13 : CPU Event mask on Event input x
bits : 13 - 13 (1 bit)
PR14 : CPU Event mask on Event input x
bits : 14 - 14 (1 bit)
PR15 : CPU Event mask on Event input x
bits : 15 - 15 (1 bit)
PR16 : CPU Event mask on Event input x
bits : 16 - 16 (1 bit)
PR17 : CPU Event mask on Event input x
bits : 17 - 17 (1 bit)
PR18 : CPU Event mask on Event input x
bits : 18 - 18 (1 bit)
PR19 : CPU Event mask on Event input x
bits : 19 - 19 (1 bit)
PR20 : CPU Event mask on Event input x
bits : 20 - 20 (1 bit)
PR21 : CPU Event mask on Event input x
bits : 21 - 21 (1 bit)
EXTI interrupt mask register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0 : CPU Interrupt Mask on Direct Event input x+32
bits : 0 - 0 (1 bit)
MR1 : CPU Interrupt Mask on Direct Event input x+32
bits : 1 - 1 (1 bit)
MR2 : CPU Interrupt Mask on Direct Event input x+32
bits : 2 - 2 (1 bit)
MR3 : CPU Interrupt Mask on Direct Event input x+32
bits : 3 - 3 (1 bit)
MR4 : CPU Interrupt Mask on Direct Event input x+32
bits : 4 - 4 (1 bit)
MR5 : CPU Interrupt Mask on Direct Event input x+32
bits : 5 - 5 (1 bit)
MR6 : CPU Interrupt Mask on Direct Event input x+32
bits : 6 - 6 (1 bit)
MR7 : CPU Interrupt Mask on Direct Event input x+32
bits : 7 - 7 (1 bit)
MR8 : CPU Interrupt Mask on Direct Event input x+32
bits : 8 - 8 (1 bit)
MR9 : CPU Interrupt Mask on Direct Event input x+32
bits : 9 - 9 (1 bit)
MR10 : CPU Interrupt Mask on Direct Event input x+32
bits : 10 - 10 (1 bit)
MR11 : CPU Interrupt Mask on Direct Event input x+32
bits : 11 - 11 (1 bit)
MR12 : CPU Interrupt Mask on Direct Event input x+32
bits : 12 - 12 (1 bit)
MR14 : CPU Interrupt Mask on Direct Event input x+32
bits : 14 - 14 (1 bit)
MR15 : CPU Interrupt Mask on Direct Event input x+32
bits : 15 - 15 (1 bit)
MR16 : CPU Interrupt Mask on Direct Event input x+32
bits : 16 - 16 (1 bit)
MR17 : CPU Interrupt Mask on Direct Event input x+32
bits : 17 - 17 (1 bit)
MR18 : CPU Interrupt Mask on Direct Event input x+32
bits : 18 - 18 (1 bit)
MR19 : CPU Interrupt Mask on Direct Event input x+32
bits : 19 - 19 (1 bit)
MR20 : CPU Interrupt Mask on Direct Event input x+32
bits : 20 - 20 (1 bit)
MR21 : CPU Interrupt Mask on Direct Event input x+32
bits : 21 - 21 (1 bit)
MR22 : CPU Interrupt Mask on Direct Event input x+32
bits : 22 - 22 (1 bit)
MR23 : CPU Interrupt Mask on Direct Event input x+32
bits : 23 - 23 (1 bit)
MR24 : CPU Interrupt Mask on Direct Event input x+32
bits : 24 - 24 (1 bit)
MR25 : CPU Interrupt Mask on Direct Event input x+32
bits : 25 - 25 (1 bit)
MR26 : CPU Interrupt Mask on Direct Event input x+32
bits : 26 - 26 (1 bit)
MR27 : CPU Interrupt Mask on Direct Event input x+32
bits : 27 - 27 (1 bit)
MR28 : CPU Interrupt Mask on Direct Event input x+32
bits : 28 - 28 (1 bit)
MR29 : CPU Interrupt Mask on Direct Event input x+32
bits : 29 - 29 (1 bit)
MR30 : CPU Interrupt Mask on Direct Event input x+32
bits : 30 - 30 (1 bit)
MR31 : CPU Interrupt Mask on Direct Event input x+32
bits : 31 - 31 (1 bit)
EXTI event mask register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR32 : CPU Interrupt Mask on Direct Event input x+32
bits : 0 - 0 (1 bit)
MR33 : CPU Interrupt Mask on Direct Event input x+32
bits : 1 - 1 (1 bit)
MR34 : CPU Interrupt Mask on Direct Event input x+32
bits : 2 - 2 (1 bit)
MR35 : CPU Interrupt Mask on Direct Event input x+32
bits : 3 - 3 (1 bit)
MR36 : CPU Interrupt Mask on Direct Event input x+32
bits : 4 - 4 (1 bit)
MR37 : CPU Interrupt Mask on Direct Event input x+32
bits : 5 - 5 (1 bit)
MR38 : CPU Interrupt Mask on Direct Event input x+32
bits : 6 - 6 (1 bit)
MR39 : CPU Interrupt Mask on Direct Event input x+32
bits : 7 - 7 (1 bit)
MR40 : CPU Interrupt Mask on Direct Event input x+32
bits : 8 - 8 (1 bit)
MR41 : CPU Interrupt Mask on Direct Event input x+32
bits : 9 - 9 (1 bit)
MR42 : CPU Interrupt Mask on Direct Event input x+32
bits : 10 - 10 (1 bit)
MR43 : CPU Interrupt Mask on Direct Event input x+32
bits : 11 - 11 (1 bit)
MR44 : CPU Interrupt Mask on Direct Event input x+32
bits : 12 - 12 (1 bit)
MR46 : CPU Interrupt Mask on Direct Event input x+32
bits : 14 - 14 (1 bit)
MR47 : CPU Interrupt Mask on Direct Event input x+32
bits : 15 - 15 (1 bit)
MR48 : CPU Interrupt Mask on Direct Event input x+32
bits : 16 - 16 (1 bit)
MR49 : CPU Interrupt Mask on Direct Event input x+32
bits : 17 - 17 (1 bit)
MR50 : CPU Interrupt Mask on Direct Event input x+32
bits : 18 - 18 (1 bit)
MR51 : CPU Interrupt Mask on Direct Event input x+32
bits : 19 - 19 (1 bit)
MR52 : CPU Interrupt Mask on Direct Event input x+32
bits : 20 - 20 (1 bit)
MR53 : CPU Interrupt Mask on Direct Event input x+32
bits : 21 - 21 (1 bit)
MR54 : CPU Interrupt Mask on Direct Event input x+32
bits : 22 - 22 (1 bit)
MR55 : CPU Interrupt Mask on Direct Event input x+32
bits : 23 - 23 (1 bit)
MR56 : CPU Interrupt Mask on Direct Event input x+32
bits : 24 - 24 (1 bit)
MR57 : CPU Interrupt Mask on Direct Event input x+32
bits : 25 - 25 (1 bit)
MR58 : CPU Interrupt Mask on Direct Event input x+32
bits : 26 - 26 (1 bit)
MR59 : CPU Interrupt Mask on Direct Event input x+32
bits : 27 - 27 (1 bit)
MR60 : CPU Interrupt Mask on Direct Event input x+32
bits : 28 - 28 (1 bit)
MR61 : CPU Interrupt Mask on Direct Event input x+32
bits : 29 - 29 (1 bit)
MR62 : CPU Interrupt Mask on Direct Event input x+32
bits : 30 - 30 (1 bit)
MR63 : CPU Interrupt Mask on Direct Event input x+32
bits : 31 - 31 (1 bit)
EXTI pending register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PR49 : Configurable event inputs x+32 Pending bit
bits : 17 - 17 (1 bit)
PR51 : Configurable event inputs x+32 Pending bit
bits : 19 - 19 (1 bit)
EXTI interrupt mask register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MR64 : CPU Interrupt Mask on Direct Event input x+64
bits : 0 - 0 (1 bit)
MR65 : CPU Interrupt Mask on Direct Event input x+64
bits : 1 - 1 (1 bit)
MR66 : CPU Interrupt Mask on Direct Event input x+64
bits : 2 - 2 (1 bit)
MR67 : CPU Interrupt Mask on Direct Event input x+64
bits : 3 - 3 (1 bit)
MR68 : CPU Interrupt Mask on Direct Event input x+64
bits : 4 - 4 (1 bit)
MR69 : CPU Interrupt Mask on Direct Event input x+64
bits : 5 - 5 (1 bit)
MR70 : CPU Interrupt Mask on Direct Event input x+64
bits : 6 - 6 (1 bit)
MR71 : CPU Interrupt Mask on Direct Event input x+64
bits : 7 - 7 (1 bit)
MR72 : CPU Interrupt Mask on Direct Event input x+64
bits : 8 - 8 (1 bit)
MR73 : CPU Interrupt Mask on Direct Event input x+64
bits : 9 - 9 (1 bit)
MR74 : CPU Interrupt Mask on Direct Event input x+64
bits : 10 - 10 (1 bit)
MR75 : CPU Interrupt Mask on Direct Event input x+64
bits : 11 - 11 (1 bit)
MR76 : CPU Interrupt Mask on Direct Event input x+64
bits : 12 - 12 (1 bit)
MR77 : CPU Interrupt Mask on Direct Event input x+64
bits : 13 - 13 (1 bit)
MR78 : CPU Interrupt Mask on Direct Event input x+64
bits : 14 - 14 (1 bit)
MR79 : CPU Interrupt Mask on Direct Event input x+64
bits : 15 - 15 (1 bit)
MR80 : CPU Interrupt Mask on Direct Event input x+64
bits : 16 - 16 (1 bit)
MR82 : CPU Interrupt Mask on Direct Event input x+64
bits : 18 - 18 (1 bit)
MR84 : CPU Interrupt Mask on Direct Event input x+64
bits : 20 - 20 (1 bit)
MR85 : CPU Interrupt Mask on Direct Event input x+64
bits : 21 - 21 (1 bit)
MR86 : CPU Interrupt Mask on Direct Event input x+64
bits : 22 - 22 (1 bit)
MR87 : CPU Interrupt Mask on Direct Event input x+64
bits : 23 - 23 (1 bit)
MR88 : CPU Interrupt Mask on Direct Event input x+64
bits : 24 - 24 (1 bit)
EXTI event mask register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MR64 : CPU Event mask on Event input x+64
bits : 0 - 0 (1 bit)
MR65 : CPU Event mask on Event input x+64
bits : 1 - 1 (1 bit)
MR66 : CPU Event mask on Event input x+64
bits : 2 - 2 (1 bit)
MR67 : CPU Event mask on Event input x+64
bits : 3 - 3 (1 bit)
MR68 : CPU Event mask on Event input x+64
bits : 4 - 4 (1 bit)
MR69 : CPU Event mask on Event input x+64
bits : 5 - 5 (1 bit)
MR70 : CPU Event mask on Event input x+64
bits : 6 - 6 (1 bit)
MR71 : CPU Event mask on Event input x+64
bits : 7 - 7 (1 bit)
MR72 : CPU Event mask on Event input x+64
bits : 8 - 8 (1 bit)
MR73 : CPU Event mask on Event input x+64
bits : 9 - 9 (1 bit)
MR74 : CPU Event mask on Event input x+64
bits : 10 - 10 (1 bit)
MR75 : CPU Event mask on Event input x+64
bits : 11 - 11 (1 bit)
MR76 : CPU Event mask on Event input x+64
bits : 12 - 12 (1 bit)
MR77 : CPU Event mask on Event input x+64
bits : 13 - 13 (1 bit)
MR78 : CPU Event mask on Event input x+64
bits : 14 - 14 (1 bit)
MR79 : CPU Event mask on Event input x+64
bits : 15 - 15 (1 bit)
MR80 : CPU Event mask on Event input x+64
bits : 16 - 16 (1 bit)
MR82 : CPU Event mask on Event input x+64
bits : 18 - 18 (1 bit)
MR84 : CPU Event mask on Event input x+64
bits : 20 - 20 (1 bit)
MR85 : CPU Event mask on Event input x+64
bits : 21 - 21 (1 bit)
MR86 : CPU Event mask on Event input x+64
bits : 22 - 22 (1 bit)
MR87 : CPU Event mask on Event input x+64
bits : 23 - 23 (1 bit)
MR88 : CPU Event mask on Event input x+64
bits : 24 - 24 (1 bit)
EXTI pending register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PR82 : Configurable event inputs x+64 Pending bit
bits : 18 - 18 (1 bit)
PR84 : Configurable event inputs x+64 Pending bit
bits : 20 - 20 (1 bit)
PR85 : Configurable event inputs x+64 Pending bit
bits : 21 - 21 (1 bit)
PR86 : Configurable event inputs x+64 Pending bit
bits : 22 - 22 (1 bit)
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