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WDOG1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

PCH1_PRSCTRL

IF

IFS

IFC

IEN

CMD

SYNCBUSY

PCH0_PRSCTRL


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DEBUGRUN EM2RUN EM3RUN LOCK EM4BLOCK SWOSCBLOCK PERSEL CLKSEL WARNSEL WINSEL CLRSRC WDOGRSTDIS

EN : Watchdog Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

DEBUGRUN : Debug Mode Run Enable
bits : 1 - 1 (1 bit)
access : read-write

EM2RUN : Energy Mode 2 Run Enable
bits : 2 - 2 (1 bit)
access : read-write

EM3RUN : Energy Mode 3 Run Enable
bits : 3 - 3 (1 bit)
access : read-write

LOCK : Configuration Lock
bits : 4 - 4 (1 bit)
access : read-write

EM4BLOCK : Energy Mode 4 Block
bits : 5 - 5 (1 bit)
access : read-write

SWOSCBLOCK : Software Oscillator Disable Block
bits : 6 - 6 (1 bit)
access : read-write

PERSEL : Watchdog Timeout Period Select
bits : 8 - 11 (4 bit)
access : read-write

CLKSEL : Watchdog Clock Select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x00000000 : ULFRCO

ULFRCO

0x00000001 : LFRCO

LFRCO

0x00000002 : LFXO

LFXO

0x00000003 : HFCORECLK

HFCORECLK

End of enumeration elements list.

WARNSEL : Watchdog Timeout Period Select
bits : 16 - 17 (2 bit)
access : read-write

WINSEL : Watchdog Illegal Window Select
bits : 24 - 26 (3 bit)
access : read-write

CLRSRC : Watchdog Clear Source
bits : 30 - 30 (1 bit)
access : read-write

WDOGRSTDIS : Watchdog Reset Disable
bits : 31 - 31 (1 bit)
access : read-write


PCH1_PRSCTRL

PRS Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCH1_PRSCTRL PCH1_PRSCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL PRSMISSRSTEN

PRSSEL : PRS Channel PRS Select
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

0x00000008 : PRSCH8

PRS Channel 8 selected as input

0x00000009 : PRSCH9

PRS Channel 9 selected as input

0x0000000A : PRSCH10

PRS Channel 10 selected as input

0x0000000B : PRSCH11

PRS Channel 11 selected as input

0x0000000C : PRSCH12

PRS Channel 12 selected as input

0x0000000D : PRSCH13

PRS Channel 13 selected as input

0x0000000E : PRSCH14

PRS Channel 14 selected as input

0x0000000F : PRSCH15

PRS Channel 15 selected as input

End of enumeration elements list.

PRSMISSRSTEN : PRS Missing Event Will Trigger a Watchdog Reset
bits : 8 - 8 (1 bit)
access : read-write


IF

Watchdog Interrupt Flags
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUT WARN WIN PEM0 PEM1

TOUT : WDOG Timeout Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

WARN : WDOG Warning Timeout Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

WIN : WDOG Window Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

PEM0 : PRS Channel Zero Event Missing Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

PEM1 : PRS Channel One Event Missing Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUT WARN WIN PEM0 PEM1

TOUT : Set TOUT Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

WARN : Set WARN Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

WIN : Set WIN Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

PEM0 : Set PEM0 Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

PEM1 : Set PEM1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUT WARN WIN PEM0 PEM1

TOUT : Clear TOUT Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

WARN : Clear WARN Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

WIN : Clear WIN Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

PEM0 : Clear PEM0 Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

PEM1 : Clear PEM1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUT WARN WIN PEM0 PEM1

TOUT : TOUT Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

WARN : WARN Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

WIN : WIN Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

PEM0 : PEM0 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

PEM1 : PEM1 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLEAR

CLEAR : Watchdog Timer Clear
bits : 0 - 0 (1 bit)
access : write-only


SYNCBUSY

Synchronization Busy Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL CMD PCH0_PRSCTRL PCH1_PRSCTRL

CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only

CMD : CMD Register Busy
bits : 1 - 1 (1 bit)
access : read-only

PCH0_PRSCTRL : PCH0_PRSCTRL Register Busy
bits : 2 - 2 (1 bit)
access : read-only

PCH1_PRSCTRL : PCH1_PRSCTRL Register Busy
bits : 3 - 3 (1 bit)
access : read-only


PCH0_PRSCTRL

PRS Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCH0_PRSCTRL PCH0_PRSCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL PRSMISSRSTEN

PRSSEL : PRS Channel PRS Select
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

0x00000008 : PRSCH8

PRS Channel 8 selected as input

0x00000009 : PRSCH9

PRS Channel 9 selected as input

0x0000000A : PRSCH10

PRS Channel 10 selected as input

0x0000000B : PRSCH11

PRS Channel 11 selected as input

0x0000000C : PRSCH12

PRS Channel 12 selected as input

0x0000000D : PRSCH13

PRS Channel 13 selected as input

0x0000000E : PRSCH14

PRS Channel 14 selected as input

0x0000000F : PRSCH15

PRS Channel 15 selected as input

End of enumeration elements list.

PRSMISSRSTEN : PRS Missing Event Will Trigger a Watchdog Reset
bits : 8 - 8 (1 bit)
access : read-write



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