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MSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

ADDRB

RAMCTRL

ECCCTRL

RAMECCADDR

RAM1ECCADDR

RAM2ECCADDR

WDATA

STATUS

IF

IFS

IFC

IEN

READCTRL

LOCK

CACHECMD

CACHEHITS

CACHEMISSES

MASSLOCK

STARTUP

BANKSWITCHLOCK

CMD

WRITECTRL

BOOTLOADERCTRL

AAPUNLOCKCMD

CACHECONFIG0

WRITECMD


CTRL

Memory System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRFAULTEN CLKDISFAULTEN PWRUPONDEMAND IFCREADCLEAR TIMEOUTFAULTEN RAMECCERRFAULTEN EBIFAULTEN WAITMODE

ADDRFAULTEN : Invalid Address Bus Fault Response Enable
bits : 0 - 0 (1 bit)
access : read-write

CLKDISFAULTEN : Clock-disabled Bus Fault Response Enable
bits : 1 - 1 (1 bit)
access : read-write

PWRUPONDEMAND : Power Up on Demand During Wake Up
bits : 2 - 2 (1 bit)
access : read-write

IFCREADCLEAR : IFC Read Clears IF
bits : 3 - 3 (1 bit)
access : read-write

TIMEOUTFAULTEN : Timeout Bus Fault Response Enable
bits : 4 - 4 (1 bit)
access : read-write

RAMECCERRFAULTEN : Two Bit ECC Error Bus Fault Response Enable
bits : 5 - 5 (1 bit)
access : read-write

EBIFAULTEN : EBI Bus Fault Response Enable
bits : 6 - 6 (1 bit)
access : read-write

WAITMODE : Peripheral Access Wait Mode
bits : 12 - 12 (1 bit)
access : read-write


ADDRB

Page Erase/Write Address Buffer
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRB ADDRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRB

ADDRB : Page Erase or Write Address Buffer
bits : 0 - 31 (32 bit)
access : read-write


RAMCTRL

RAM Control Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMCTRL RAMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMWSEN RAMPREFETCHEN RAM1WSEN RAM1PREFETCHEN RAM2WSEN RAM2PREFETCHEN

RAMWSEN : RAM WAIT STATE Enable
bits : 1 - 1 (1 bit)
access : read-write

RAMPREFETCHEN : RAM Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write

RAM1WSEN : RAM1 WAIT STATE Enable
bits : 9 - 9 (1 bit)
access : read-write

RAM1PREFETCHEN : RAM1 Prefetch Enable
bits : 10 - 10 (1 bit)
access : read-write

RAM2WSEN : RAM2 WAIT STATE Enable
bits : 17 - 17 (1 bit)
access : read-write

RAM2PREFETCHEN : RAM2 Prefetch Enable
bits : 18 - 18 (1 bit)
access : read-write


ECCCTRL

RAM ECC Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCCTRL ECCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMECCEWEN RAMECCCHKEN RAM1ECCEWEN RAM1ECCCHKEN RAM2ECCEWEN RAM2ECCCHKEN

RAMECCEWEN : RAM ECC Write Enable
bits : 0 - 0 (1 bit)
access : read-write

RAMECCCHKEN : RAM ECC Check Enable
bits : 1 - 1 (1 bit)
access : read-write

RAM1ECCEWEN : RAM1 ECC Write Enable
bits : 2 - 2 (1 bit)
access : read-write

RAM1ECCCHKEN : RAM1 ECC Check Enable
bits : 3 - 3 (1 bit)
access : read-write

RAM2ECCEWEN : RAM2 ECC Write Enable
bits : 4 - 4 (1 bit)
access : read-write

RAM2ECCCHKEN : RAM2 ECC Check Enable
bits : 5 - 5 (1 bit)
access : read-write


RAMECCADDR

RAM ECC Error Address Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMECCADDR RAMECCADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMECCADDR

RAMECCADDR : RAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


RAM1ECCADDR

RAM1 ECC Error Address Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM1ECCADDR RAM1ECCADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM1ECCADDR

RAM1ECCADDR : RAM1 ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


RAM2ECCADDR

RAM2 ECC Error Address Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM2ECCADDR RAM2ECCADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM2ECCADDR

RAM2ECCADDR : RAM2 ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


WDATA

Write Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDATA WDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Write Data
bits : 0 - 31 (32 bit)
access : read-write


STATUS

Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY LOCKED INVADDR WDATAREADY WORDTIMEOUT ERASEABORTED PCRUNNING BANKSWITCHED WDATAVALID PWRUPCKBDFAILCOUNT

BUSY : Erase/Write Busy
bits : 0 - 0 (1 bit)
access : read-only

LOCKED : Access Locked
bits : 1 - 1 (1 bit)
access : read-only

INVADDR : Invalid Write Address or Erase Page
bits : 2 - 2 (1 bit)
access : read-only

WDATAREADY : WDATA Write Ready
bits : 3 - 3 (1 bit)
access : read-only

WORDTIMEOUT : Flash Write Word Timeout
bits : 4 - 4 (1 bit)
access : read-only

ERASEABORTED : The Current Flash Erase Operation Aborted
bits : 5 - 5 (1 bit)
access : read-only

PCRUNNING : Performance Counters Running
bits : 6 - 6 (1 bit)
access : read-only

BANKSWITCHED : BANK SWITCHING STATUS
bits : 7 - 7 (1 bit)
access : read-only

WDATAVALID : Write Data Buffer Valid Flag
bits : 24 - 27 (4 bit)
access : read-only

PWRUPCKBDFAILCOUNT : Flash Power Up Checkerboard Pattern Check Fail Count
bits : 28 - 31 (4 bit)
access : read-only


IF

Interrupt Flag Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF PWRUPF ICACHERR WDATAOV LVEWRITE RAMERR1B RAMERR2B RAM1ERR1B RAM1ERR2B RAM2ERR1B RAM2ERR2B

ERASE : Erase Done Interrupt Read Flag
bits : 0 - 0 (1 bit)
access : read-only

WRITE : Write Done Interrupt Read Flag
bits : 1 - 1 (1 bit)
access : read-only

CHOF : Cache Hits Overflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

CMOF : Cache Misses Overflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

PWRUPF : Flash Power Up Sequence Complete Flag
bits : 4 - 4 (1 bit)
access : read-only

ICACHERR : ICache RAM Parity Error Flag
bits : 5 - 5 (1 bit)
access : read-only

WDATAOV : Flash Controller Write Buffer Overflow
bits : 6 - 6 (1 bit)
access : read-only

LVEWRITE : Flash LVE Write Error Flag
bits : 8 - 8 (1 bit)
access : read-only

RAMERR1B : RAM 1-bit ECC Error Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only

RAMERR2B : RAM 2-bit ECC Error Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-only

RAM1ERR1B : RAM1 1-bit ECC Error Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-only

RAM1ERR2B : RAM1 2-bit ECC Error Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-only

RAM2ERR1B : RAM2 1-bit ECC Error Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-only

RAM2ERR2B : RAM2 2-bit ECC Error Interrupt Flag
bits : 21 - 21 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF PWRUPF ICACHERR WDATAOV LVEWRITE RAMERR1B RAMERR2B RAM1ERR1B RAM1ERR2B RAM2ERR1B RAM2ERR2B

ERASE : Set ERASE Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

WRITE : Set WRITE Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

CHOF : Set CHOF Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

CMOF : Set CMOF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

PWRUPF : Set PWRUPF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

ICACHERR : Set ICACHERR Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

WDATAOV : Set WDATAOV Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

LVEWRITE : Set LVEWRITE Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

RAMERR1B : Set RAMERR1B Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

RAMERR2B : Set RAMERR2B Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

RAM1ERR1B : Set RAM1ERR1B Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only

RAM1ERR2B : Set RAM1ERR2B Interrupt Flag
bits : 19 - 19 (1 bit)
access : write-only

RAM2ERR1B : Set RAM2ERR1B Interrupt Flag
bits : 20 - 20 (1 bit)
access : write-only

RAM2ERR2B : Set RAM2ERR2B Interrupt Flag
bits : 21 - 21 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF PWRUPF ICACHERR WDATAOV LVEWRITE RAMERR1B RAMERR2B RAM1ERR1B RAM1ERR2B RAM2ERR1B RAM2ERR2B

ERASE : Clear ERASE Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

WRITE : Clear WRITE Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

CHOF : Clear CHOF Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

CMOF : Clear CMOF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

PWRUPF : Clear PWRUPF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

ICACHERR : Clear ICACHERR Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

WDATAOV : Clear WDATAOV Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

LVEWRITE : Clear LVEWRITE Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

RAMERR1B : Clear RAMERR1B Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

RAMERR2B : Clear RAMERR2B Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

RAM1ERR1B : Clear RAM1ERR1B Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only

RAM1ERR2B : Clear RAM1ERR2B Interrupt Flag
bits : 19 - 19 (1 bit)
access : write-only

RAM2ERR1B : Clear RAM2ERR1B Interrupt Flag
bits : 20 - 20 (1 bit)
access : write-only

RAM2ERR2B : Clear RAM2ERR2B Interrupt Flag
bits : 21 - 21 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF PWRUPF ICACHERR WDATAOV LVEWRITE RAMERR1B RAMERR2B RAM1ERR1B RAM1ERR2B RAM2ERR1B RAM2ERR2B

ERASE : ERASE Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

WRITE : WRITE Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

CHOF : CHOF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

CMOF : CMOF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

PWRUPF : PWRUPF Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

ICACHERR : ICACHERR Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

WDATAOV : WDATAOV Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

LVEWRITE : LVEWRITE Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

RAMERR1B : RAMERR1B Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

RAMERR2B : RAMERR2B Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

RAM1ERR1B : RAM1ERR1B Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

RAM1ERR2B : RAM1ERR2B Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

RAM2ERR1B : RAM2ERR1B Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write

RAM2ERR2B : RAM2ERR2B Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write


READCTRL

Read Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READCTRL READCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFCDIS AIDIS ICCDIS EBICDIS PREFETCH USEHPROT QSPICDIS MODE SCBTP

IFCDIS : Internal Flash Cache Disable
bits : 3 - 3 (1 bit)
access : read-write

AIDIS : Automatic Invalidate Disable
bits : 4 - 4 (1 bit)
access : read-write

ICCDIS : Interrupt Context Cache Disable
bits : 5 - 5 (1 bit)
access : read-write

EBICDIS : External Bus Interface Cache Disable
bits : 6 - 6 (1 bit)
access : read-write

PREFETCH : Prefetch Mode
bits : 8 - 8 (1 bit)
access : read-write

USEHPROT : AHB_HPROT Mode
bits : 9 - 9 (1 bit)
access : read-write

QSPICDIS : QSPI Cache Disable
bits : 10 - 10 (1 bit)
access : read-write

MODE : Read Mode
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : WS0

Zero wait-states inserted in fetch or read transfers

0x00000001 : WS1

One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details

0x00000002 : WS2

Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details

0x00000003 : WS3

Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details

End of enumeration elements list.

SCBTP : Suppress Conditional Branch Target Perfetch
bits : 28 - 28 (1 bit)
access : read-write


LOCK

Configuration Lock Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


CACHECMD

Flash Cache Command Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CACHECMD CACHECMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVCACHE STARTPC STOPPC

INVCACHE : Invalidate Instruction Cache
bits : 0 - 0 (1 bit)
access : write-only

STARTPC : Start Performance Counters
bits : 1 - 1 (1 bit)
access : write-only

STOPPC : Stop Performance Counters
bits : 2 - 2 (1 bit)
access : write-only


CACHEHITS

Cache Hits Performance Counter
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CACHEHITS CACHEHITS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHEHITS

CACHEHITS : Cache Hits Since Last Performance Counter Start Command
bits : 0 - 19 (20 bit)
access : read-only


CACHEMISSES

Cache Misses Performance Counter
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CACHEMISSES CACHEMISSES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHEMISSES

CACHEMISSES : Cache Misses Since Last Performance Counter Start Command
bits : 0 - 19 (20 bit)
access : read-only


MASSLOCK

Mass Erase Lock Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASSLOCK MASSLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Mass Erase Lock
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


STARTUP

Startup Control
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STARTUP STARTUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STDLY0 STDLY1 ASTWAIT STWSEN STWSAEN STWS

STDLY0 : Startup Delay 0
bits : 0 - 9 (10 bit)
access : read-write

STDLY1 : Startup Delay 0
bits : 12 - 21 (10 bit)
access : read-write

ASTWAIT : Active Startup Wait
bits : 24 - 24 (1 bit)
access : read-write

STWSEN : Startup Waitstates Enable
bits : 25 - 25 (1 bit)
access : read-write

STWSAEN : Startup Waitstates Always Enable
bits : 26 - 26 (1 bit)
access : read-write

STWS : Startup Waitstates
bits : 28 - 30 (3 bit)
access : read-write


BANKSWITCHLOCK

Bank Switching Lock Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BANKSWITCHLOCK BANKSWITCHLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BANKSWITCHLOCKKEY

BANKSWITCHLOCKKEY : Bank Switching Lock
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


CMD

Command Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRUP SWITCHINGBANK

PWRUP : Flash Power Up Command
bits : 0 - 0 (1 bit)
access : write-only

SWITCHINGBANK : BANK SWITCHING COMMAND
bits : 1 - 1 (1 bit)
access : write-only


WRITECTRL

Write Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRITECTRL WRITECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WREN IRQERASEABORT RWWEN

WREN : Enable Write/Erase Controller
bits : 0 - 0 (1 bit)
access : read-write

IRQERASEABORT : Abort Page Erase on Interrupt
bits : 1 - 1 (1 bit)
access : read-write

RWWEN : Read-While-Write Enable
bits : 5 - 5 (1 bit)
access : read-write


BOOTLOADERCTRL

Bootloader Read and Write Enable, Write Once Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOTLOADERCTRL BOOTLOADERCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLRDIS BLWDIS

BLRDIS : Flash Bootloader Read Disable
bits : 0 - 0 (1 bit)
access : read-write

BLWDIS : Flash Bootloader Write/Erase Disable
bits : 1 - 1 (1 bit)
access : read-write


AAPUNLOCKCMD

Software Unlock AAP Command Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AAPUNLOCKCMD AAPUNLOCKCMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNLOCKAAP

UNLOCKAAP : Software Unlock AAP Command
bits : 0 - 0 (1 bit)
access : write-only


CACHECONFIG0

Cache Configuration Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CACHECONFIG0 CACHECONFIG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHELPLEVEL

CACHELPLEVEL : Instruction Cache Low-Power Level
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : BASE

Base instruction cache functionality.

0x00000001 : ADVANCED

Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory.

0x00000003 : MINACTIVITY

Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality.

End of enumeration elements list.


WRITECMD

Write Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WRITECMD WRITECMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LADDRIM ERASEPAGE WRITEEND WRITEONCE WRITETRIG ERASEABORT ERASEMAIN0 ERASEMAIN1 CLEARWDATA

LADDRIM : Load MSC_ADDRB Into ADDR
bits : 0 - 0 (1 bit)
access : write-only

ERASEPAGE : Erase Page
bits : 1 - 1 (1 bit)
access : write-only

WRITEEND : End Write Mode
bits : 2 - 2 (1 bit)
access : write-only

WRITEONCE : Word Write-Once Trigger
bits : 3 - 3 (1 bit)
access : write-only

WRITETRIG : Word Write Sequence Trigger
bits : 4 - 4 (1 bit)
access : write-only

ERASEABORT : Abort Erase Sequence
bits : 5 - 5 (1 bit)
access : write-only

ERASEMAIN0 : Mass Erase Region 0
bits : 8 - 8 (1 bit)
access : write-only

ERASEMAIN1 : Mass Erase Region 1
bits : 9 - 9 (1 bit)
access : write-only

CLEARWDATA : Clear WDATA State
bits : 12 - 12 (1 bit)
access : write-only



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