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CMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

HFRCOCTRL

HFPRESC

HFBUSPRESC

HFCOREPRESC

HFPERPRESC

HFEXPPRESC

HFPERPRESCB

HFPERPRESCC

LFAPRESC0

LFBPRESC0

LFEPRESC0

SYNCBUSY

FREEZE

PCNTCTRL

ADCCTRL

SDIOCTRL

QSPICTRL

PDMCTRL

ROUTEPEN

ROUTELOC0

ROUTELOC1

AUXHFRCOCTRL

LOCK

HFRCOSS

USBCTRL

USBCRCTRL

LFRCOCTRL

HFXOCTRL

HFXOCTRL1

HFXOSTARTUPCTRL

HFXOSTEADYSTATECTRL

HFXOTIMEOUTCTRL

LFXOCTRL

DPLLCTRL

DPLLCTRL1

CALCTRL

CALCNT

OSCENCMD

CMD

DBGCLKSEL

HFCLKSEL

USHFRCOCTRL

LFACLKSEL

LFBCLKSEL

LFECLKSEL

LFCCLKSEL

STATUS

HFCLKSTATUS

HFXOTRIMSTATUS

IF

IFS

IFC

IEN

HFBUSCLKEN0

HFPERCLKEN0

HFPERCLKEN1

LFACLKEN0

LFBCLKEN0

LFCCLKEN0

LFECLKEN0


CTRL

CMU Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOUTSEL0 CLKOUTSEL1 CLKOUTSEL2 WSHFLE HFPERCLKEN

CLKOUTSEL0 : Clock Output Select 0
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Disabled

0x00000001 : ULFRCO

ULFRCO (directly from oscillator)

0x00000002 : LFRCO

LFRCO (directly from oscillator)

0x00000003 : LFXO

LFXO (directly from oscillator)

0x00000006 : HFXO

HFXO (directly from oscillator)

0x00000007 : HFEXPCLK

HFEXPCLK

0x00000009 : ULFRCOQ

ULFRCO (qualified)

0x0000000A : LFRCOQ

LFRCO (qualified)

0x0000000B : LFXOQ

LFXO (qualified)

0x0000000C : HFRCOQ

HFRCO (qualified)

0x0000000D : AUXHFRCOQ

AUXHFRCO (qualified)

0x0000000E : HFXOQ

HFXO (qualified)

0x0000000F : HFSRCCLK

HFSRCCLK

0x00000012 : USHFRCOQ

USHFRCO (qualified)

End of enumeration elements list.

CLKOUTSEL1 : Clock Output Select 1
bits : 5 - 9 (5 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Disabled

0x00000001 : ULFRCO

ULFRCO (directly from oscillator)

0x00000002 : LFRCO

LFRCO (directly from oscillator)

0x00000003 : LFXO

LFXO (directly from oscillator)

0x00000006 : HFXO

HFXO (directly from oscillator)

0x00000007 : HFEXPCLK

HFEXPCLK

0x00000009 : ULFRCOQ

ULFRCO (qualified)

0x0000000A : LFRCOQ

LFRCO (qualified)

0x0000000B : LFXOQ

LFXO (qualified)

0x0000000C : HFRCOQ

HFRCO (qualified)

0x0000000D : AUXHFRCOQ

AUXHFRCO (qualified)

0x0000000E : HFXOQ

HFXO (qualified)

0x0000000F : HFSRCCLK

HFSRCCLK

0x00000012 : USHFRCOQ

USHFRCO (qualified)

End of enumeration elements list.

CLKOUTSEL2 : Clock Output Select 2
bits : 10 - 14 (5 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Disabled

0x00000001 : ULFRCO

ULFRCO (directly from oscillator)

0x00000002 : LFRCO

LFRCO (directly from oscillator)

0x00000003 : LFXO

LFXO (directly from oscillator)

0x00000005 : HFXODIV2Q

HFXO divided by two (qualified)

0x00000006 : HFXO

HFXO (directly from oscillator)

0x00000007 : HFEXPCLK

HFEXPCLK

0x00000008 : HFXOX2Q

HFXO doubler (qualified) (doubling activated by HFXOX2EN=1)

0x00000009 : ULFRCOQ

ULFRCO (qualified)

0x0000000A : LFRCOQ

LFRCO (qualified)

0x0000000B : LFXOQ

LFXO (qualified)

0x0000000C : HFRCOQ

HFRCO (qualified)

0x0000000D : AUXHFRCOQ

AUXHFRCO (qualified)

0x0000000E : HFXOQ

HFXO (qualified)

0x0000000F : HFSRCCLK

HFSRCCLK

0x00000012 : USHFRCOQ

USHFRCO (qualified)

End of enumeration elements list.

WSHFLE : Wait State for High-Frequency LE Interface
bits : 16 - 16 (1 bit)
access : read-write

HFPERCLKEN : HFPERCLK Enable
bits : 20 - 20 (1 bit)
access : read-write


HFRCOCTRL

HFRCO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFRCOCTRL HFRCOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING FINETUNING FREQRANGE CMPBIAS LDOHP CLKDIV FINETUNINGEN VREFTC

TUNING : HFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write

FINETUNING : HFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write

FREQRANGE : HFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write

CMPBIAS : HFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write

LDOHP : HFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write

CLKDIV : Locally Divide HFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

Divide by 1.

0x00000001 : DIV2

Divide by 2.

0x00000002 : DIV4

Divide by 4.

End of enumeration elements list.

FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write

VREFTC : HFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write


HFPRESC

High Frequency Clock Prescaler Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFPRESC HFPRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC HFCLKLEPRESC

PRESC : HFCLK Prescaler
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.

HFCLKLEPRESC : HFCLKLE Prescaler
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV2

HFCLKLE is HFBUSCLKLE divided by 2.

0x00000001 : DIV4

HFCLKLE is HFBUSCLKLE divided by 4.

0x00000002 : DIV8

HFCLKLE is HFBUSCLKLE divided by 8.

End of enumeration elements list.


HFBUSPRESC

High Frequency Bus Clock Prescaler Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFBUSPRESC HFBUSPRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : HFBUSCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.


HFCOREPRESC

High Frequency Core Clock Prescaler Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFCOREPRESC HFCOREPRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : HFCORECLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.


HFPERPRESC

High Frequency Peripheral Clock Prescaler Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFPERPRESC HFPERPRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.


HFEXPPRESC

High Frequency Export Clock Prescaler Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFEXPPRESC HFEXPPRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : HFEXPCLK Prescaler
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.


HFPERPRESCB

High Frequency Peripheral Clock Prescaler B Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFPERPRESCB HFPERPRESCB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.


HFPERPRESCC

High Frequency Peripheral Clock Prescaler C Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFPERPRESCC HFPERPRESCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.


LFAPRESC0

Low Frequency a Prescaler Register 0 (Async Reg)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFAPRESC0 LFAPRESC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LETIMER0 LETIMER1 LESENSE LCD RTC

LETIMER0 : Low Energy Timer 0 Prescaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFACLKLETIMER0 = LFACLK

0x00000001 : DIV2

LFACLKLETIMER0 = LFACLK/2

0x00000002 : DIV4

LFACLKLETIMER0 = LFACLK/4

0x00000003 : DIV8

LFACLKLETIMER0 = LFACLK/8

0x00000004 : DIV16

LFACLKLETIMER0 = LFACLK/16

0x00000005 : DIV32

LFACLKLETIMER0 = LFACLK/32

0x00000006 : DIV64

LFACLKLETIMER0 = LFACLK/64

0x00000007 : DIV128

LFACLKLETIMER0 = LFACLK/128

0x00000008 : DIV256

LFACLKLETIMER0 = LFACLK/256

0x00000009 : DIV512

LFACLKLETIMER0 = LFACLK/512

0x0000000A : DIV1024

LFACLKLETIMER0 = LFACLK/1024

0x0000000B : DIV2048

LFACLKLETIMER0 = LFACLK/2048

0x0000000C : DIV4096

LFACLKLETIMER0 = LFACLK/4096

0x0000000D : DIV8192

LFACLKLETIMER0 = LFACLK/8192

0x0000000E : DIV16384

LFACLKLETIMER0 = LFACLK/16384

0x0000000F : DIV32768

LFACLKLETIMER0 = LFACLK/32768

End of enumeration elements list.

LETIMER1 : Low Energy Timer 1 Prescaler
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFACLKLETIMER1 = LFACLK

0x00000001 : DIV2

LFACLKLETIMER1 = LFACLK/2

0x00000002 : DIV4

LFACLKLETIMER1 = LFACLK/4

0x00000003 : DIV8

LFACLKLETIMER1 = LFACLK/8

0x00000004 : DIV16

LFACLKLETIMER1 = LFACLK/16

0x00000005 : DIV32

LFACLKLETIMER1 = LFACLK/32

0x00000006 : DIV64

LFACLKLETIMER1 = LFACLK/64

0x00000007 : DIV128

LFACLKLETIMER1 = LFACLK/128

0x00000008 : DIV256

LFACLKLETIMER1 = LFACLK/256

0x00000009 : DIV512

LFACLKLETIMER1 = LFACLK/512

0x0000000A : DIV1024

LFACLKLETIMER1 = LFACLK/1024

0x0000000B : DIV2048

LFACLKLETIMER1 = LFACLK/2048

0x0000000C : DIV4096

LFACLKLETIMER1 = LFACLK/4096

0x0000000D : DIV8192

LFACLKLETIMER1 = LFACLK/8192

0x0000000E : DIV16384

LFACLKLETIMER1 = LFACLK/16384

0x0000000F : DIV32768

LFACLKLETIMER1 = LFACLK/32768

End of enumeration elements list.

LESENSE : Low Energy Sensor Interface Prescaler
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFACLKLESENSE = LFACLK

0x00000001 : DIV2

LFACLKLESENSE = LFACLK/2

0x00000002 : DIV4

LFACLKLESENSE = LFACLK/4

0x00000003 : DIV8

LFACLKLESENSE = LFACLK/8

End of enumeration elements list.

LCD : Liquid Crystal Display Controller Prescaler
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFACLKLCD = LFACLK

0x00000001 : DIV2

LFACLKLCD = LFACLK/2

0x00000002 : DIV4

LFACLKLCD = LFACLK/4

0x00000003 : DIV8

LFACLKLCD = LFACLK/8

0x00000004 : DIV16

LFACLKLCD = LFACLK/16

0x00000005 : DIV32

LFACLKLCD = LFACLK/32

0x00000006 : DIV64

LFACLKLCD = LFACLK/64

0x00000007 : DIV128

LFACLKLCD = LFACLK/128

End of enumeration elements list.

RTC : Real-Time Counter Prescaler
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFACLKRTC = LFACLK

0x00000001 : DIV2

LFACLKRTC = LFACLK/2

0x00000002 : DIV4

LFACLKRTC = LFACLK/4

0x00000003 : DIV8

LFACLKRTC = LFACLK/8

0x00000004 : DIV16

LFACLKRTC = LFACLK/16

0x00000005 : DIV32

LFACLKRTC = LFACLK/32

0x00000006 : DIV64

LFACLKRTC = LFACLK/64

0x00000007 : DIV128

LFACLKRTC = LFACLK/128

0x00000008 : DIV256

LFACLKRTC = LFACLK/256

0x00000009 : DIV512

LFACLKRTC = LFACLK/512

0x0000000A : DIV1024

LFACLKRTC = LFACLK/1024

0x0000000B : DIV2048

LFACLKRTC = LFACLK/2048

0x0000000C : DIV4096

LFACLKRTC = LFACLK/4096

0x0000000D : DIV8192

LFACLKRTC = LFACLK/8192

0x0000000E : DIV16384

LFACLKRTC = LFACLK/16384

0x0000000F : DIV32768

LFACLKRTC = LFACLK/32768

End of enumeration elements list.


LFBPRESC0

Low Frequency B Prescaler Register 0 (Async Reg)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFBPRESC0 LFBPRESC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEUART0 LEUART1 SYSTICK CSEN

LEUART0 : Low Energy UART 0 Prescaler
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFBCLKLEUART0 = LFBCLK

0x00000001 : DIV2

LFBCLKLEUART0 = LFBCLK/2

0x00000002 : DIV4

LFBCLKLEUART0 = LFBCLK/4

0x00000003 : DIV8

LFBCLKLEUART0 = LFBCLK/8

End of enumeration elements list.

LEUART1 : Low Energy UART 1 Prescaler
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFBCLKLEUART1 = LFBCLK

0x00000001 : DIV2

LFBCLKLEUART1 = LFBCLK/2

0x00000002 : DIV4

LFBCLKLEUART1 = LFBCLK/4

0x00000003 : DIV8

LFBCLKLEUART1 = LFBCLK/8

End of enumeration elements list.

SYSTICK : Prescaler
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

0x00000000 : DIV1

LFBCLKSYSTICK = LFBCLK

End of enumeration elements list.

CSEN : Capacitive touch sense module Prescaler
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV16

LFBCLKCSEN = LFBCLK/16

0x00000001 : DIV32

LFBCLKCSEN = LFBCLK/32

0x00000002 : DIV64

LFBCLKCSEN = LFBCLK/64

0x00000003 : DIV128

LFBCLKCSEN = LFBCLK/128

End of enumeration elements list.


LFEPRESC0

Low Frequency E Prescaler Register 0 (Async Reg)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFEPRESC0 LFEPRESC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCC

RTCC : Real-Time Counter and Calendar Prescaler
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LFECLKRTCC = LFECLK

0x00000001 : DIV2

LFECLKRTCC = LFECLK/2

0x00000002 : DIV4

LFECLKRTCC = LFECLK/4

End of enumeration elements list.


SYNCBUSY

Synchronization Busy Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFACLKEN0 LFAPRESC0 LFBCLKEN0 LFBPRESC0 LFCCLKEN0 LFECLKEN0 LFEPRESC0 HFRCOBSY AUXHFRCOBSY LFRCOBSY LFRCOVREFBSY HFXOBSY LFXOBSY USHFRCOBSY

LFACLKEN0 : Low Frequency a Clock Enable 0 Busy
bits : 0 - 0 (1 bit)
access : read-only

LFAPRESC0 : Low Frequency a Prescaler 0 Busy
bits : 2 - 2 (1 bit)
access : read-only

LFBCLKEN0 : Low Frequency B Clock Enable 0 Busy
bits : 4 - 4 (1 bit)
access : read-only

LFBPRESC0 : Low Frequency B Prescaler 0 Busy
bits : 6 - 6 (1 bit)
access : read-only

LFCCLKEN0 : Low Frequency C Clock Enable 0 Busy
bits : 8 - 8 (1 bit)
access : read-only

LFECLKEN0 : Low Frequency E Clock Enable 0 Busy
bits : 16 - 16 (1 bit)
access : read-only

LFEPRESC0 : Low Frequency E Prescaler 0 Busy
bits : 18 - 18 (1 bit)
access : read-only

HFRCOBSY : HFRCO Busy
bits : 24 - 24 (1 bit)
access : read-only

AUXHFRCOBSY : AUXHFRCO Busy
bits : 25 - 25 (1 bit)
access : read-only

LFRCOBSY : LFRCO Busy
bits : 26 - 26 (1 bit)
access : read-only

LFRCOVREFBSY : LFRCO VREF Busy
bits : 27 - 27 (1 bit)
access : read-only

HFXOBSY : HFXO Busy
bits : 28 - 28 (1 bit)
access : read-only

LFXOBSY : LFXO Busy
bits : 29 - 29 (1 bit)
access : read-only

USHFRCOBSY : USHFRCO Busy
bits : 30 - 30 (1 bit)
access : read-only


FREEZE

Freeze Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREEZE FREEZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE

REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write


PCNTCTRL

PCNT Control Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCNTCTRL PCNTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCNT0CLKEN PCNT0CLKSEL PCNT1CLKEN PCNT1CLKSEL PCNT2CLKEN PCNT2CLKSEL

PCNT0CLKEN : PCNT0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

PCNT0CLKSEL : PCNT0 Clock Select
bits : 1 - 1 (1 bit)
access : read-write

PCNT1CLKEN : PCNT1 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write

PCNT1CLKSEL : PCNT1 Clock Select
bits : 3 - 3 (1 bit)
access : read-write

PCNT2CLKEN : PCNT2 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write

PCNT2CLKSEL : PCNT2 Clock Select
bits : 5 - 5 (1 bit)
access : read-write


ADCCTRL

ADC Control Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCCTRL ADCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0CLKDIV ADC0CLKSEL ADC0CLKINV ADC1CLKDIV ADC1CLKSEL ADC1CLKINV

ADC0CLKDIV : ADC0 Clock Prescaler
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.

ADC0CLKSEL : ADC0 Clock Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

ADC0 is not clocked

0x00000001 : AUXHFRCO

AUXHFRCO is clocking ADC0

0x00000002 : HFXO

HFXO is clocking ADC0

0x00000003 : HFSRCCLK

HFSRCCLK is clocking ADC0

End of enumeration elements list.

ADC0CLKINV : Invert Clock Selected By ADC0CLKSEL
bits : 8 - 8 (1 bit)
access : read-write

ADC1CLKDIV : ADC1 Clock Prescaler
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.

ADC1CLKSEL : ADC1 Clock Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

ADC1 is not clocked

0x00000001 : AUXHFRCO

AUXHFRCO is clocking ADC1

0x00000002 : HFXO

HFXO is clocking ADC1

0x00000003 : HFSRCCLK

HFSRCCLK is clocking ADC1

End of enumeration elements list.

ADC1CLKINV : Invert Clock Selected By ADC1CLKSEL
bits : 24 - 24 (1 bit)
access : read-write


SDIOCTRL

SDIO Control Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDIOCTRL SDIOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDIOCLKSEL SDIOCLKDIS

SDIOCLKSEL : SDIO Reference Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : HFRCO

HFRCO clock is used to clock SDIO

0x00000001 : HFXO

HFXO clock is used to clock SDIO

0x00000002 : AUXHFRCO

AUXHFRCO is used to clock SDIO

0x00000003 : USHFRCO

USHFRCO is used to clock SDIO

End of enumeration elements list.

SDIOCLKDIS : SDIO Reference Clock Disable
bits : 7 - 7 (1 bit)
access : read-write


QSPICTRL

QSPI Control Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QSPICTRL QSPICTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPI0CLKSEL QSPI0CLKDIS

QSPI0CLKSEL : QSPI0 Reference Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : HFRCO

HFRCO clock is used to clock QSPI0

0x00000001 : HFXO

HFXO clock is used to clock QSPI0

0x00000002 : AUXHFRCO

AUXHFRCO is used to clock QSPI0

0x00000003 : USHFRCO

USHFRCO is used to clock QSPI0

End of enumeration elements list.

QSPI0CLKDIS : QSPI0 Reference Clock Disable
bits : 7 - 7 (1 bit)
access : read-write


PDMCTRL

PDM Control Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMCTRL PDMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMCLKSEL PDMCLKEN

PDMCLKSEL : PDM Core Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : HFRCO

HFRCO clock is used to clock PDM

0x00000001 : HFXO

HFXO clock is used to clock PDM

0x00000002 : USHFRCO

USHFRCO is used to clock PDM

0x00000003 : CLKIN0

CLKIN0 is selected as HFCLK clock source

End of enumeration elements list.

PDMCLKEN : PDM Core Clock Enable
bits : 7 - 7 (1 bit)
access : read-write


ROUTEPEN

I/O Routing Pin Enable Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTEPEN ROUTEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOUT0PEN CLKOUT1PEN CLKOUT2PEN CLKIN0PEN

CLKOUT0PEN : CLKOUT0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

CLKOUT1PEN : CLKOUT1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CLKOUT2PEN : CLKOUT2 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CLKIN0PEN : CLKIN0 Pin Enable
bits : 28 - 28 (1 bit)
access : read-write


ROUTELOC0

I/O Routing Location Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC0 ROUTELOC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOUT0LOC CLKOUT1LOC CLKOUT2LOC

CLKOUT0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.

CLKOUT1LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.

CLKOUT2LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.


ROUTELOC1

I/O Routing Location Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC1 ROUTELOC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKIN0LOC

CLKIN0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

0x00000007 : LOC7

Location 7

End of enumeration elements list.


AUXHFRCOCTRL

AUXHFRCO Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXHFRCOCTRL AUXHFRCOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING FINETUNING FREQRANGE CMPBIAS LDOHP CLKDIV FINETUNINGEN VREFTC

TUNING : AUXHFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write

FINETUNING : AUXHFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write

FREQRANGE : AUXHFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write

CMPBIAS : AUXHFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write

LDOHP : AUXHFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write

CLKDIV : Locally Divide AUXHFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

Divide by 1.

0x00000001 : DIV2

Divide by 2.

0x00000002 : DIV4

Divide by 4.

End of enumeration elements list.

FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write

VREFTC : AUXHFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write


LOCK

Configuration Lock Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


HFRCOSS

HFRCO Spread Spectrum Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFRCOSS HFRCOSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSAMP SSINV

SSAMP : Spread Spectrum Amplitude
bits : 0 - 2 (3 bit)
access : read-write

SSINV : Spread Spectrum Update Interval
bits : 8 - 12 (5 bit)
access : read-write


USBCTRL

USB Control Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCTRL USBCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCLKSEL USBCLKEN

USBCLKSEL : USB Rate Clock Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : USHFRCO

USHFRCO (clock recovery) is clocking USB

0x00000001 : HFXO

HFXO clock is used to clock USB

0x00000002 : HFXOX2

HFXO clock doubler is used to clock USB

0x00000003 : HFRCO

HFRCO clock is used to clock USB

0x00000004 : LFXO

LFXO clock is used to clock USB

0x00000005 : LFRCO

LFRCO clock is used to clock USB

End of enumeration elements list.

USBCLKEN : USB Rate Clock Enable
bits : 7 - 7 (1 bit)
access : read-write


USBCRCTRL

USB Clock Recovery Control
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCRCTRL USBCRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCREN USBLSCRMD

USBCREN : Clock Recovery Enable
bits : 0 - 0 (1 bit)
access : read-write

USBLSCRMD : Low Speed Clock Recovery Mode
bits : 1 - 1 (1 bit)
access : read-write


LFRCOCTRL

LFRCO Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFRCOCTRL LFRCOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING ENVREF ENCHOP ENDEM VREFUPDATE TIMEOUT GMCCURTUNE

TUNING : LFRCO Tuning Value
bits : 0 - 8 (9 bit)
access : read-write

ENVREF : Enable Duty Cycling of Vref
bits : 16 - 16 (1 bit)
access : read-write

ENCHOP : Enable Comparator Chopping
bits : 17 - 17 (1 bit)
access : read-write

ENDEM : Enable Dynamic Element Matching
bits : 18 - 18 (1 bit)
access : read-write

VREFUPDATE : Control Vref Update Rate
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : 32CYCLES

32 clocks.

0x00000001 : 64CYCLES

64 clocks.

0x00000002 : 128CYCLES

128 clocks.

0x00000003 : 256CYCLES

256 clocks.

End of enumeration elements list.

TIMEOUT : LFRCO Timeout
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : 2CYCLES

Timeout period of 2 cycles

0x00000001 : 16CYCLES

Timeout period of 16 cycles

0x00000002 : 32CYCLES

Timeout period of 32 cycles

End of enumeration elements list.

GMCCURTUNE : Tuning of Gmc Current
bits : 28 - 31 (4 bit)
access : read-write


HFXOCTRL

HFXO Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFXOCTRL HFXOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HFXOX2EN PEAKDETMODE LFTIMEOUT AUTOSTARTEM0EM1 AUTOSTARTSELEM0EM1

MODE : HFXO Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : XTAL

4 MHz - 50 MHz crystal oscillator

0x00000001 : ACBUFEXTCLK

An AC coupled buffer is coupled in series with HFXTAL_N pin, suitable for external sinus wave.

0x00000002 : DCBUFEXTCLK

A DC coupled buffer is coupled in series with HFXTAL_N pin, suitable for external sinus wave.

0x00000003 : DIGEXTCLK

Digital external clock can be supplied on HFXTAL_N pin.

End of enumeration elements list.

HFXOX2EN : Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock)
bits : 3 - 3 (1 bit)
access : read-write

PEAKDETMODE : HFXO Automatic Peak Detection Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : ONCECMD

Automatic control of HFXO peak detection sequence. Only performs peak detection on initial HFXO startup. CMU_CMD HFXOPEAKDETSTART allowed to be used after HFXORDY=1.

0x00000001 : AUTOCMD

Automatic control of HFXO peak detection sequence. CMU_CMD HFXOPEAKDETSTART allowed to be used after HFXORDY=1.

0x00000002 : CMD

CMU_CMD HFXOPEAKDETSTART can be used to trigger the peak detection sequence after HFXORDY=1.

0x00000003 : MANUAL

CMU_HFXOSTEADYSTATECTRL IBTRIMXOCORE and PEAKDETEN are under full software control and are allowed to be changed once HFXO is ready.

End of enumeration elements list.

LFTIMEOUT : HFXO Low Frequency Timeout
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : 0CYCLES

Timeout period of 0 cycles (disabled)

0x00000001 : 2CYCLES

Timeout period of 2 cycles

0x00000002 : 4CYCLES

Timeout period of 4 cycles

0x00000003 : 16CYCLES

Timeout period of 16 cycles

0x00000004 : 32CYCLES

Timeout period of 32 cycles

0x00000005 : 64CYCLES

Timeout period of 64 cycles

0x00000006 : 1KCYCLES

Timeout period of 1024 cycles

0x00000007 : 4KCYCLES

Timeout period of 4096 cycles

End of enumeration elements list.

AUTOSTARTEM0EM1 : Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3
bits : 28 - 28 (1 bit)
access : read-write

AUTOSTARTSELEM0EM1 : Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3
bits : 29 - 29 (1 bit)
access : read-write


HFXOCTRL1

HFXO Control 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFXOCTRL1 HFXOCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEAKDETTHR

PEAKDETTHR : Sets the Amplitude Detection Level (mV)
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x00000000 : THR0

50mV amplitude detection level

0x00000001 : THR1

75mV amplitude detection level

0x00000002 : THR2

115mV amplitude detection level

0x00000003 : THR3

160mV amplitude detection level

0x00000004 : THR4

220mV amplitude detection level

0x00000005 : THR5

260mV amplitude detection level

0x00000006 : THR6

320mV amplitude detection level

0x00000007 : THR7

Same as THR6

End of enumeration elements list.


HFXOSTARTUPCTRL

HFXO Startup Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFXOSTARTUPCTRL HFXOSTARTUPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IBTRIMXOCORE CTUNE

IBTRIMXOCORE : Sets the Startup Oscillator Core Bias Current
bits : 0 - 10 (11 bit)
access : read-write

CTUNE : Sets Oscillator Tuning Capacitance
bits : 11 - 19 (9 bit)
access : read-write


HFXOSTEADYSTATECTRL

HFXO Steady State Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFXOSTEADYSTATECTRL HFXOSTEADYSTATECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IBTRIMXOCORE CTUNE PEAKDETEN PEAKMONEN

IBTRIMXOCORE : Sets the Steady State Oscillator Core Bias Current.
bits : 0 - 10 (11 bit)
access : read-write

CTUNE : Sets Oscillator Tuning Capacitance
bits : 11 - 19 (9 bit)
access : read-write

PEAKDETEN : Enables Oscillator Peak Detectors
bits : 26 - 26 (1 bit)
access : read-write

PEAKMONEN : Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO
bits : 27 - 27 (1 bit)
access : read-write


HFXOTIMEOUTCTRL

HFXO Timeout Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFXOTIMEOUTCTRL HFXOTIMEOUTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTUPTIMEOUT STEADYTIMEOUT PEAKDETTIMEOUT

STARTUPTIMEOUT : Wait Duration in HFXO Startup Enable Wait State
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000000 : 2CYCLES

Timeout period of 2 cycles

0x00000001 : 4CYCLES

Timeout period of 4 cycles

0x00000002 : 16CYCLES

Timeout period of 16 cycles

0x00000003 : 32CYCLES

Timeout period of 32 cycles

0x00000004 : 64CYCLES

Timeout period of 64 cycles

0x00000005 : 128CYCLES

Timeout period of 128 cycles

0x00000006 : 256CYCLES

Timeout period of 256 cycles

0x00000007 : 1KCYCLES

Timeout period of 1024 cycles

0x00000008 : 2KCYCLES

Timeout period of 2048 cycles

0x00000009 : 4KCYCLES

Timeout period of 4096 cycles

0x0000000A : 8KCYCLES

Timeout period of 8192 cycles

0x0000000B : 16KCYCLES

Timeout period of 16384 cycles

0x0000000C : 32KCYCLES

Timeout period of 32768 cycles

0x0000000D : 64KCYCLES

Timeout period of 65536 cycles

0x0000000E : 128KCYCLES

Timeout period of 131072 cycles

End of enumeration elements list.

STEADYTIMEOUT : Wait Duration in HFXO Startup Steady Wait State
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x00000000 : 2CYCLES

Timeout period of 2 cycles

0x00000001 : 4CYCLES

Timeout period of 4 cycles

0x00000002 : 16CYCLES

Timeout period of 16 cycles

0x00000003 : 32CYCLES

Timeout period of 32 cycles

0x00000004 : 64CYCLES

Timeout period of 64 cycles

0x00000005 : 128CYCLES

Timeout period of 128 cycles

0x00000006 : 256CYCLES

Timeout period of 256 cycles

0x00000007 : 1KCYCLES

Timeout period of 1024 cycles

0x00000008 : 2KCYCLES

Timeout period of 2048 cycles

0x00000009 : 4KCYCLES

Timeout period of 4096 cycles

0x0000000A : 8KCYCLES

Timeout period of 8192 cycles

0x0000000B : 16KCYCLES

Timeout period of 16384 cycles

0x0000000C : 32KCYCLES

Timeout period of 32768 cycles

0x0000000D : 64KCYCLES

Timeout period of 65536 cycles

0x0000000E : 128KCYCLES

Timeout period of 131072 cycles

End of enumeration elements list.

PEAKDETTIMEOUT : Wait Duration in HFXO Peak Detection Wait State
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0x00000000 : 2CYCLES

Timeout period of 2 cycles

0x00000001 : 4CYCLES

Timeout period of 4 cycles

0x00000002 : 16CYCLES

Timeout period of 16 cycles

0x00000003 : 32CYCLES

Timeout period of 32 cycles

0x00000004 : 64CYCLES

Timeout period of 64 cycles

0x00000005 : 128CYCLES

Timeout period of 128 cycles

0x00000006 : 256CYCLES

Timeout period of 256 cycles

0x00000007 : 1KCYCLES

Timeout period of 1024 cycles

0x00000008 : 2KCYCLES

Timeout period of 2048 cycles

0x00000009 : 4KCYCLES

Timeout period of 4096 cycles

0x0000000A : 8KCYCLES

Timeout period of 8192 cycles

0x0000000B : 16KCYCLES

Timeout period of 16384 cycles

0x0000000C : 32KCYCLES

Timeout period of 32768 cycles

0x0000000D : 64KCYCLES

Timeout period of 65536 cycles

0x0000000E : 128KCYCLES

Timeout period of 131072 cycles

End of enumeration elements list.


LFXOCTRL

LFXO Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFXOCTRL LFXOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING MODE GAIN HIGHAMPL AGC CUR BUFCUR TIMEOUT

TUNING : LFXO Internal Capacitor Array Tuning Value
bits : 0 - 6 (7 bit)
access : read-write

MODE : LFXO Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : XTAL

32768 Hz crystal oscillator

0x00000001 : BUFEXTCLK

An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32768 Hz).

0x00000002 : DIGEXTCLK

Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.

End of enumeration elements list.

GAIN : LFXO Startup Gain
bits : 11 - 12 (2 bit)
access : read-write

HIGHAMPL : LFXO High XTAL Oscillation Amplitude Enable
bits : 14 - 14 (1 bit)
access : read-write

AGC : LFXO AGC Enable
bits : 15 - 15 (1 bit)
access : read-write

CUR : LFXO Current Trim
bits : 16 - 17 (2 bit)
access : read-write

BUFCUR : LFXO Buffer Bias Current
bits : 20 - 20 (1 bit)
access : read-write

TIMEOUT : LFXO Timeout
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : 2CYCLES

Timeout period of 2 cycles

0x00000001 : 256CYCLES

Timeout period of 256 cycles

0x00000002 : 1KCYCLES

Timeout period of 1024 cycles

0x00000003 : 2KCYCLES

Timeout period of 2048 cycles

0x00000004 : 4KCYCLES

Timeout period of 4096 cycles

0x00000005 : 8KCYCLES

Timeout period of 8192 cycles

0x00000006 : 16KCYCLES

Timeout period of 16384 cycles

0x00000007 : 32KCYCLES

Timeout period of 32768 cycles

End of enumeration elements list.


DPLLCTRL

DPLL Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLCTRL DPLLCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE EDGESEL AUTORECOVER REFSEL DITHEN

MODE : Operating Mode Control
bits : 0 - 0 (1 bit)
access : read-write

EDGESEL : Reference Edge Select
bits : 1 - 1 (1 bit)
access : read-write

AUTORECOVER : Automatic Recovery Ctrl
bits : 2 - 2 (1 bit)
access : read-write

REFSEL : Reference Clock Selection Control
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x00000000 : HFXO

HFXO selected

0x00000001 : LFXO

LFXO selected

0x00000002 : USHFRCO

USHFRCO selected

0x00000003 : CLKIN0

CLKIN0 selected

End of enumeration elements list.

DITHEN : Dither Enable Control
bits : 6 - 6 (1 bit)
access : read-write


DPLLCTRL1

DPLL Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLCTRL1 DPLLCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M N

M : Factor M
bits : 0 - 11 (12 bit)
access : read-write

N : Factor N
bits : 16 - 27 (12 bit)
access : read-write


CALCTRL

Calibration Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALCTRL CALCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPSEL DOWNSEL CONT PRSUPSEL PRSDOWNSEL

UPSEL : Calibration Up-counter Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : HFXO

Select HFXO as up-counter

0x00000001 : LFXO

Select LFXO as up-counter

0x00000002 : HFRCO

Select HFRCO as up-counter

0x00000003 : LFRCO

Select LFRCO as up-counter

0x00000004 : AUXHFRCO

Select AUXHFRCO as up-counter

0x00000005 : PRS

Select PRS input selected by PRSUPSEL as up-counter

0x00000007 : USHFRCO

Select USHFRCO as up-counter

End of enumeration elements list.

DOWNSEL : Calibration Down-counter Select
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x00000000 : HFCLK

Select HFCLK for down-counter

0x00000001 : HFXO

Select HFXO for down-counter

0x00000002 : LFXO

Select LFXO for down-counter

0x00000003 : HFRCO

Select HFRCO for down-counter

0x00000004 : LFRCO

Select LFRCO for down-counter

0x00000005 : AUXHFRCO

Select AUXHFRCO for down-counter

0x00000006 : PRS

Select PRS input selected by PRSDOWNSEL as down-counter

0x00000008 : USHFRCO

Select USHFRCO for down-counter

End of enumeration elements list.

CONT : Continuous Calibration
bits : 8 - 8 (1 bit)
access : read-write

PRSUPSEL : PRS Select for PRS Input When Selected in UPSEL
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

0x00000008 : PRSCH8

PRS Channel 8 selected as input

0x00000009 : PRSCH9

PRS Channel 9 selected as input

0x0000000A : PRSCH10

PRS Channel 10 selected as input

0x0000000B : PRSCH11

PRS Channel 11 selected as input

0x0000000C : PRSCH12

PRS Channel 12 selected as input

0x0000000D : PRSCH13

PRS Channel 13 selected as input

0x0000000E : PRSCH14

PRS Channel 14 selected as input

0x0000000F : PRSCH15

PRS Channel 15 selected as input

End of enumeration elements list.

PRSDOWNSEL : PRS Select for PRS Input When Selected in DOWNSEL
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

0x00000008 : PRSCH8

PRS Channel 8 selected as input

0x00000009 : PRSCH9

PRS Channel 9 selected as input

0x0000000A : PRSCH10

PRS Channel 10 selected as input

0x0000000B : PRSCH11

PRS Channel 11 selected as input

0x0000000C : PRSCH12

PRS Channel 12 selected as input

0x0000000D : PRSCH13

PRS Channel 13 selected as input

0x0000000E : PRSCH14

PRS Channel 14 selected as input

0x0000000F : PRSCH15

PRS Channel 15 selected as input

End of enumeration elements list.


CALCNT

Calibration Counter Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALCNT CALCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALCNT

CALCNT : Calibration Counter
bits : 0 - 19 (20 bit)
access : read-write


OSCENCMD

Oscillator Enable/Disable Command Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OSCENCMD OSCENCMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCOEN HFRCODIS HFXOEN HFXODIS AUXHFRCOEN AUXHFRCODIS LFRCOEN LFRCODIS LFXOEN LFXODIS USHFRCOEN USHFRCODIS DPLLEN DPLLDIS

HFRCOEN : HFRCO Enable
bits : 0 - 0 (1 bit)
access : write-only

HFRCODIS : HFRCO Disable
bits : 1 - 1 (1 bit)
access : write-only

HFXOEN : HFXO Enable
bits : 2 - 2 (1 bit)
access : write-only

HFXODIS : HFXO Disable
bits : 3 - 3 (1 bit)
access : write-only

AUXHFRCOEN : AUXHFRCO Enable
bits : 4 - 4 (1 bit)
access : write-only

AUXHFRCODIS : AUXHFRCO Disable
bits : 5 - 5 (1 bit)
access : write-only

LFRCOEN : LFRCO Enable
bits : 6 - 6 (1 bit)
access : write-only

LFRCODIS : LFRCO Disable
bits : 7 - 7 (1 bit)
access : write-only

LFXOEN : LFXO Enable
bits : 8 - 8 (1 bit)
access : write-only

LFXODIS : LFXO Disable
bits : 9 - 9 (1 bit)
access : write-only

USHFRCOEN : USHFRCO Enable
bits : 10 - 10 (1 bit)
access : write-only

USHFRCODIS : USHFRCO Disable
bits : 11 - 11 (1 bit)
access : write-only

DPLLEN : DPLL Enable
bits : 12 - 12 (1 bit)
access : write-only

DPLLDIS : DPLL Disable
bits : 13 - 13 (1 bit)
access : write-only


CMD

Command Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALSTART CALSTOP HFXOPEAKDETSTART

CALSTART : Calibration Start
bits : 0 - 0 (1 bit)
access : write-only

CALSTOP : Calibration Stop
bits : 1 - 1 (1 bit)
access : write-only

HFXOPEAKDETSTART : HFXO Peak Detection Start
bits : 4 - 4 (1 bit)
access : write-only


DBGCLKSEL

Debug Trace Clock Select
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCLKSEL DBGCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG

DBG : Debug Trace Clock
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : AUXHFRCO

AUXHFRCO is the debug trace clock

0x00000001 : HFCLK

HFCLK is the debug trace clock

0x00000002 : HFRCODIV2

HFRCO divided by 2 is the debug trace clock

End of enumeration elements list.


HFCLKSEL

High Frequency Clock Select Command Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HFCLKSEL HFCLKSEL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HF

HF : HFCLK Select
bits : 0 - 2 (3 bit)
access : write-only

Enumeration:

0x00000001 : HFRCO

Select HFRCO as HFCLK

0x00000002 : HFXO

Select HFXO as HFCLK

0x00000003 : LFRCO

Select LFRCO as HFCLK

0x00000004 : LFXO

Select LFXO as HFCLK

0x00000005 : HFRCODIV2

Select HFRCO divided by 2 as HFCLK

0x00000006 : USHFRCO

Select USHFRCO as HFCLK

0x00000007 : CLKIN0

Select CLKIN0 as HFCLK

End of enumeration elements list.


USHFRCOCTRL

USHFRCO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USHFRCOCTRL USHFRCOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING FINETUNING FREQRANGE CMPBIAS LDOHP CLKDIV FINETUNINGEN VREFTC

TUNING : USHFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write

FINETUNING : USHFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write

FREQRANGE : USHFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write

CMPBIAS : USHFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write

LDOHP : USHFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write

CLKDIV : Locally Divide USHFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

Divide by 1.

0x00000001 : DIV2

Divide by 2.

0x00000002 : DIV4

Divide by 4.

End of enumeration elements list.

FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write

VREFTC : USHFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write


LFACLKSEL

Low Frequency A Clock Select Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFACLKSEL LFACLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFA

LFA : Clock Select for LFA
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

LFACLK is disabled

0x00000001 : LFRCO

LFRCO selected as LFACLK

0x00000002 : LFXO

LFXO selected as LFACLK

0x00000004 : ULFRCO

ULFRCO selected as LFACLK

End of enumeration elements list.


LFBCLKSEL

Low Frequency B Clock Select Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFBCLKSEL LFBCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFB

LFB : Clock Select for LFB
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

LFBCLK is disabled

0x00000001 : LFRCO

LFRCO selected as LFBCLK

0x00000002 : LFXO

LFXO selected as LFBCLK

0x00000003 : HFCLKLE

HFCLK divided by two/four is selected as LFBCLK

0x00000004 : ULFRCO

ULFRCO selected as LFBCLK

End of enumeration elements list.


LFECLKSEL

Low Frequency E Clock Select Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFECLKSEL LFECLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFE

LFE : Clock Select for LFE
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

LFECLK is disabled

0x00000001 : LFRCO

LFRCO selected as LFECLK

0x00000002 : LFXO

LFXO selected as LFECLK

0x00000004 : ULFRCO

ULFRCO selected as LFECLK

End of enumeration elements list.


LFCCLKSEL

Low Frequency C Clock Select Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFCCLKSEL LFCCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFC

LFC : Clock Select for LFC
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

LFCCLK is disabled

0x00000001 : LFRCO

LFRCO selected as LFCCLK

0x00000002 : LFXO

LFXO selected as LFCCLK

0x00000004 : ULFRCO

ULFRCO selected as LFCCLK

End of enumeration elements list.


STATUS

Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCOENS HFRCORDY HFXOENS HFXORDY AUXHFRCOENS AUXHFRCORDY LFRCOENS LFRCORDY LFXOENS LFXORDY USHFRCOENS USHFRCORDY DPLLENS DPLLRDY CALRDY SDIOCLKENS QSPI0CLKENS PDMCLKENS HFXOPEAKDETRDY HFXOAMPLOW LFXOPHASE LFRCOPHASE ULFRCOPHASE

HFRCOENS : HFRCO Enable Status
bits : 0 - 0 (1 bit)
access : read-only

HFRCORDY : HFRCO Ready
bits : 1 - 1 (1 bit)
access : read-only

HFXOENS : HFXO Enable Status
bits : 2 - 2 (1 bit)
access : read-only

HFXORDY : HFXO Ready
bits : 3 - 3 (1 bit)
access : read-only

AUXHFRCOENS : AUXHFRCO Enable Status
bits : 4 - 4 (1 bit)
access : read-only

AUXHFRCORDY : AUXHFRCO Ready
bits : 5 - 5 (1 bit)
access : read-only

LFRCOENS : LFRCO Enable Status
bits : 6 - 6 (1 bit)
access : read-only

LFRCORDY : LFRCO Ready
bits : 7 - 7 (1 bit)
access : read-only

LFXOENS : LFXO Enable Status
bits : 8 - 8 (1 bit)
access : read-only

LFXORDY : LFXO Ready
bits : 9 - 9 (1 bit)
access : read-only

USHFRCOENS : USHFRCO Enable Status
bits : 10 - 10 (1 bit)
access : read-only

USHFRCORDY : USHFRCO Ready
bits : 11 - 11 (1 bit)
access : read-only

DPLLENS : DPLL Enable Status
bits : 12 - 12 (1 bit)
access : read-only

DPLLRDY : DPLL Ready
bits : 13 - 13 (1 bit)
access : read-only

CALRDY : Calibration Ready
bits : 16 - 16 (1 bit)
access : read-only

SDIOCLKENS : SDIO Clock Enabled Status
bits : 17 - 17 (1 bit)
access : read-only

QSPI0CLKENS : QSPI0 Clock Enabled Status
bits : 18 - 18 (1 bit)
access : read-only

PDMCLKENS : PDM Clock Enabled Status
bits : 19 - 19 (1 bit)
access : read-only

HFXOPEAKDETRDY : HFXO Peak Detection Ready
bits : 22 - 22 (1 bit)
access : read-only

HFXOAMPLOW : HFXO Amplitude Tuning Value Too Low
bits : 25 - 25 (1 bit)
access : read-only

LFXOPHASE : LFXO Clock Phase
bits : 27 - 27 (1 bit)
access : read-only

LFRCOPHASE : LFRCO Clock Phase
bits : 28 - 28 (1 bit)
access : read-only

ULFRCOPHASE : ULFRCO Clock Phase
bits : 29 - 29 (1 bit)
access : read-only


HFCLKSTATUS

HFCLK Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFCLKSTATUS HFCLKSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELECTED

SELECTED : HFCLK Selected
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0x00000001 : HFRCO

HFRCO is selected as HFCLK clock source

0x00000002 : HFXO

HFXO is selected as HFCLK clock source

0x00000003 : LFRCO

LFRCO is selected as HFCLK clock source

0x00000004 : LFXO

LFXO is selected as HFCLK clock source

0x00000005 : HFRCODIV2

HFRCO divided by 2 is selected as HFCLK clock source

0x00000006 : USHFRCO

USHFRCO is selected as HFCLK clock source

0x00000007 : CLKIN0

CLKIN0 is selected as HFCLK clock source

End of enumeration elements list.


HFXOTRIMSTATUS

HFXO Trim Status
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFXOTRIMSTATUS HFXOTRIMSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IBTRIMXOCORE IBTRIMXOCOREMON VALID MONVALID

IBTRIMXOCORE : Value of IBTRIMXOCORE Found By Automatic HFXO Peak Detection Algorithm
bits : 0 - 10 (11 bit)
access : read-only

IBTRIMXOCOREMON : Value of IBTRIMXOCORE Found By Automatic HFXO Peak Detection Algorithm or Peak Monitoring Algorithm (completion of Either Algorithm Will Cause an Update of IBTRIMXOCOREMON)
bits : 16 - 26 (11 bit)
access : read-only

VALID : Peak Detection Algorithm Found a Value for IBTRIMXOCORE
bits : 30 - 30 (1 bit)
access : read-only

MONVALID : Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON
bits : 31 - 31 (1 bit)
access : read-only


IF

Interrupt Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY HFXODISERR HFXOAUTOSW HFXOPEAKDETRDY HFRCODIS LFTIMEOUTERR DPLLRDY DPLLLOCKFAILLOW DPLLLOCKFAILHIGH LFXOEDGE LFRCOEDGE ULFRCOEDGE CMUERR

HFRCORDY : HFRCO Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

HFXORDY : HFXO Ready Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

LFRCORDY : LFRCO Ready Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

LFXORDY : LFXO Ready Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

CALRDY : Calibration Ready Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only

CALOF : Calibration Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only

USHFRCORDY : USHFRCO Ready Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

HFXODISERR : HFXO Disable Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only

HFXOAUTOSW : HFXO Automatic Switch Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only

HFXOPEAKDETRDY : HFXO Automatic Peak Detection Ready Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only

HFRCODIS : HFRCO Disable Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-only

LFTIMEOUTERR : Low Frequency Timeout Error Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-only

DPLLRDY : DPLL Lock Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-only

DPLLLOCKFAILLOW : DPLL Lock Failure Low Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only

DPLLLOCKFAILHIGH : DPLL Lock Failure Low Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-only

LFXOEDGE : LFXO Clock Edge Detected Interrupt Flag
bits : 27 - 27 (1 bit)
access : read-only

LFRCOEDGE : LFRCO Clock Edge Detected Interrupt Flag
bits : 28 - 28 (1 bit)
access : read-only

ULFRCOEDGE : ULFRCO Clock Edge Detected Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-only

CMUERR : CMU Error Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY HFXODISERR HFXOAUTOSW HFXOPEAKDETRDY HFRCODIS LFTIMEOUTERR DPLLRDY DPLLLOCKFAILLOW DPLLLOCKFAILHIGH LFXOEDGE LFRCOEDGE ULFRCOEDGE CMUERR

HFRCORDY : Set HFRCORDY Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

HFXORDY : Set HFXORDY Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

LFRCORDY : Set LFRCORDY Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

LFXORDY : Set LFXORDY Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

AUXHFRCORDY : Set AUXHFRCORDY Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

CALRDY : Set CALRDY Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

CALOF : Set CALOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

USHFRCORDY : Set USHFRCORDY Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

HFXODISERR : Set HFXODISERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

HFXOAUTOSW : Set HFXOAUTOSW Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

HFXOPEAKDETRDY : Set HFXOPEAKDETRDY Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

HFRCODIS : Set HFRCODIS Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only

LFTIMEOUTERR : Set LFTIMEOUTERR Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

DPLLRDY : Set DPLLRDY Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

DPLLLOCKFAILLOW : Set DPLLLOCKFAILLOW Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

DPLLLOCKFAILHIGH : Set DPLLLOCKFAILHIGH Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

LFXOEDGE : Set LFXOEDGE Interrupt Flag
bits : 27 - 27 (1 bit)
access : write-only

LFRCOEDGE : Set LFRCOEDGE Interrupt Flag
bits : 28 - 28 (1 bit)
access : write-only

ULFRCOEDGE : Set ULFRCOEDGE Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only

CMUERR : Set CMUERR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY HFXODISERR HFXOAUTOSW HFXOPEAKDETRDY HFRCODIS LFTIMEOUTERR DPLLRDY DPLLLOCKFAILLOW DPLLLOCKFAILHIGH LFXOEDGE LFRCOEDGE ULFRCOEDGE CMUERR

HFRCORDY : Clear HFRCORDY Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

HFXORDY : Clear HFXORDY Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

LFRCORDY : Clear LFRCORDY Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

LFXORDY : Clear LFXORDY Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

AUXHFRCORDY : Clear AUXHFRCORDY Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

CALRDY : Clear CALRDY Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

CALOF : Clear CALOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

USHFRCORDY : Clear USHFRCORDY Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

HFXODISERR : Clear HFXODISERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

HFXOAUTOSW : Clear HFXOAUTOSW Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

HFXOPEAKDETRDY : Clear HFXOPEAKDETRDY Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

HFRCODIS : Clear HFRCODIS Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only

LFTIMEOUTERR : Clear LFTIMEOUTERR Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

DPLLRDY : Clear DPLLRDY Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

DPLLLOCKFAILLOW : Clear DPLLLOCKFAILLOW Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

DPLLLOCKFAILHIGH : Clear DPLLLOCKFAILHIGH Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

LFXOEDGE : Clear LFXOEDGE Interrupt Flag
bits : 27 - 27 (1 bit)
access : write-only

LFRCOEDGE : Clear LFRCOEDGE Interrupt Flag
bits : 28 - 28 (1 bit)
access : write-only

ULFRCOEDGE : Clear ULFRCOEDGE Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only

CMUERR : Clear CMUERR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY HFXODISERR HFXOAUTOSW HFXOPEAKDETRDY HFRCODIS LFTIMEOUTERR DPLLRDY DPLLLOCKFAILLOW DPLLLOCKFAILHIGH LFXOEDGE LFRCOEDGE ULFRCOEDGE CMUERR

HFRCORDY : HFRCORDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

HFXORDY : HFXORDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

LFRCORDY : LFRCORDY Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

LFXORDY : LFXORDY Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

AUXHFRCORDY : AUXHFRCORDY Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

CALRDY : CALRDY Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

CALOF : CALOF Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

USHFRCORDY : USHFRCORDY Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

HFXODISERR : HFXODISERR Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

HFXOAUTOSW : HFXOAUTOSW Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

HFXOPEAKDETRDY : HFXOPEAKDETRDY Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

HFRCODIS : HFRCODIS Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

LFTIMEOUTERR : LFTIMEOUTERR Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

DPLLRDY : DPLLRDY Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write

DPLLLOCKFAILLOW : DPLLLOCKFAILLOW Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

DPLLLOCKFAILHIGH : DPLLLOCKFAILHIGH Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

LFXOEDGE : LFXOEDGE Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write

LFRCOEDGE : LFRCOEDGE Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

ULFRCOEDGE : ULFRCOEDGE Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write

CMUERR : CMUERR Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write


HFBUSCLKEN0

High Frequency Bus Clock Enable Register 0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFBUSCLKEN0 HFBUSCLKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LE CRYPTO0 EBI SDIO GPIO PRS LDMA GPCRC QSPI0 USB

LE : Low Energy Peripheral Interface Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

CRYPTO0 : Advanced Encryption Standard Accelerator Clock Enable
bits : 1 - 1 (1 bit)
access : read-write

EBI : External Bus Interface Clock Enable
bits : 2 - 2 (1 bit)
access : read-write

SDIO : SDIO Controller Clock Enable
bits : 3 - 3 (1 bit)
access : read-write

GPIO : General purpose Input/Output Clock Enable
bits : 4 - 4 (1 bit)
access : read-write

PRS : Peripheral Reflex System Clock Enable
bits : 5 - 5 (1 bit)
access : read-write

LDMA : Linked Direct Memory Access Controller Clock Enable
bits : 6 - 6 (1 bit)
access : read-write

GPCRC : General Purpose CRC Clock Enable
bits : 7 - 7 (1 bit)
access : read-write

QSPI0 : Quad-SPI Clock Enable
bits : 8 - 8 (1 bit)
access : read-write

USB : Universal Serial Bus Interface Clock Enable
bits : 9 - 9 (1 bit)
access : read-write


HFPERCLKEN0

High Frequency Peripheral Clock Enable Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFPERCLKEN0 HFPERCLKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART0 USART1 USART2 USART3 USART4 TIMER0 TIMER1 TIMER2 TIMER3 ACMP0 ACMP1 ACMP2 I2C0 I2C1 ADC0 ADC1 PDM CRYOTIMER IDAC0 TRNG0

USART0 : Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

USART1 : Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write

USART2 : Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write

USART3 : Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write

USART4 : Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write

TIMER0 : Timer 0 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write

TIMER1 : Timer 1 Clock Enable
bits : 6 - 6 (1 bit)
access : read-write

TIMER2 : Timer 2 Clock Enable
bits : 7 - 7 (1 bit)
access : read-write

TIMER3 : Timer 3 Clock Enable
bits : 8 - 8 (1 bit)
access : read-write

ACMP0 : Analog Comparator 0 Clock Enable
bits : 9 - 9 (1 bit)
access : read-write

ACMP1 : Analog Comparator 1 Clock Enable
bits : 10 - 10 (1 bit)
access : read-write

ACMP2 : Analog Comparator 2 Clock Enable
bits : 11 - 11 (1 bit)
access : read-write

I2C0 : I2C 0 Clock Enable
bits : 12 - 12 (1 bit)
access : read-write

I2C1 : I2C 1 Clock Enable
bits : 13 - 13 (1 bit)
access : read-write

ADC0 : Analog to Digital Converter 0 Clock Enable
bits : 14 - 14 (1 bit)
access : read-write

ADC1 : Analog to Digital Converter 0 Clock Enable
bits : 15 - 15 (1 bit)
access : read-write

PDM : PDM Interface Clock Enable
bits : 16 - 16 (1 bit)
access : read-write

CRYOTIMER : CRYOTIMER Clock Enable
bits : 17 - 17 (1 bit)
access : read-write

IDAC0 : Current Digital to Analog Converter 0 Clock Enable
bits : 18 - 18 (1 bit)
access : read-write

TRNG0 : True Random Number Generator 0 Clock Enable
bits : 19 - 19 (1 bit)
access : read-write


HFPERCLKEN1

High Frequency Peripheral Clock Enable Register 1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFPERCLKEN1 HFPERCLKEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0 UART1 WTIMER0 WTIMER1 CAN0 CAN1 VDAC0 CSEN

UART0 : Universal Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

UART1 : Universal Asynchronous Receiver/Transmitter 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write

WTIMER0 : Wide Timer 0 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write

WTIMER1 : Wide Timer 0 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write

CAN0 : CAN 0 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write

CAN1 : CAN 1 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write

VDAC0 : Digital to Analog Converter 0 Clock Enable
bits : 6 - 6 (1 bit)
access : read-write

CSEN : Capacitive touch sense module Clock Enable
bits : 7 - 7 (1 bit)
access : read-write


LFACLKEN0

Low Frequency a Clock Enable Register 0 (Async Reg)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFACLKEN0 LFACLKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LETIMER0 LETIMER1 LESENSE LCD RTC

LETIMER0 : Low Energy Timer 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

LETIMER1 : Low Energy Timer 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write

LESENSE : Low Energy Sensor Interface Clock Enable
bits : 2 - 2 (1 bit)
access : read-write

LCD : Liquid Crystal Display Controller Clock Enable
bits : 3 - 3 (1 bit)
access : read-write

RTC : Real-Time Counter Clock Enable
bits : 4 - 4 (1 bit)
access : read-write


LFBCLKEN0

Low Frequency B Clock Enable Register 0 (Async Reg)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFBCLKEN0 LFBCLKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEUART0 LEUART1 SYSTICK CSEN

LEUART0 : Low Energy UART 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

LEUART1 : Low Energy UART 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write

SYSTICK : Clock Enable
bits : 2 - 2 (1 bit)
access : read-write

CSEN : Capacitive touch sense module Clock Enable
bits : 3 - 3 (1 bit)
access : read-write


LFCCLKEN0

Low Frequency C Clock Enable Register 0 (Async Reg)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFCCLKEN0 LFCCLKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB

USB : Universal Serial Bus Interface Clock Enable
bits : 0 - 0 (1 bit)
access : read-write


LFECLKEN0

Low Frequency E Clock Enable Register 0 (Async Reg)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFECLKEN0 LFECLKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCC

RTCC : Real-Time Counter and Calendar Clock Enable
bits : 0 - 0 (1 bit)
access : read-write



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