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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xDE000 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

IFC

IEN

ROUTE

CDCONF

CMD

DATTRIM1

LEMCTRL

STATUS

ROUTELOC0

IF

IFS

GOTGCTL

GOTGINT

GAHBCFG

GUSBCFG

GRSTCTL

GINTSTS

GINTMSK

GRXSTSR

GRXSTSP

GRXFSIZ

GNPTXFSIZ

GNPTXSTS

GSNPSID

GDFIFOCFG

HPTXFSIZ

DIEPTXF1

DIEPTXF2

DIEPTXF3

DIEPTXF4

DIEPTXF5

DIEPTXF6

HCFG

HFIR

HFNUM

HPTXSTS

HAINT

HAINTMSK

HPRT

HC0_CHAR

HC0_SPLT

HC0_INT

HC0_INTMSK

HC0_TSIZ

HC0_DMAADDR

HC1_CHAR

HC1_SPLT

HC1_INT

HC1_INTMSK

HC1_TSIZ

HC1_DMAADDR

HC2_CHAR

HC2_SPLT

HC2_INT

HC2_INTMSK

HC2_TSIZ

HC2_DMAADDR

HC3_CHAR

HC3_SPLT

HC3_INT

HC3_INTMSK

HC3_TSIZ

HC3_DMAADDR

HC4_CHAR

HC4_SPLT

HC4_INT

HC4_INTMSK

HC4_TSIZ

HC4_DMAADDR

HC5_CHAR

HC5_SPLT

HC5_INT

HC5_INTMSK

HC5_TSIZ

HC5_DMAADDR

HC6_CHAR

HC6_SPLT

HC6_INT

HC6_INTMSK

HC6_TSIZ

HC6_DMAADDR

HC7_CHAR

HC7_SPLT

HC7_INT

HC7_INTMSK

HC7_TSIZ

HC7_DMAADDR

HC8_CHAR

HC8_SPLT

HC8_INT

HC8_INTMSK

HC8_TSIZ

HC8_DMAADDR

HC9_CHAR

HC9_SPLT

HC9_INT

HC9_INTMSK

HC9_TSIZ

HC9_DMAADDR

HC10_CHAR

HC10_SPLT

HC10_INT

HC10_INTMSK

HC10_TSIZ

HC10_DMAADDR

HC11_CHAR

HC11_SPLT

HC11_INT

HC11_INTMSK

HC11_TSIZ

HC11_DMAADDR

HC12_CHAR

HC12_SPLT

HC12_INT

HC12_INTMSK

HC12_TSIZ

HC12_DMAADDR

HC13_CHAR

HC13_SPLT

HC13_INT

HC13_INTMSK

HC13_TSIZ

HC13_DMAADDR

DCFG

DCTL

DSTS

DIEPMSK

DOEPMSK

DAINT

DAINTMSK

DVBUSDIS

DVBUSPULSE

DTHRCTL

DIEPEMPMSK

DIEP0CTL

DIEP0INT

DIEP0TSIZ

DIEP0DMAADDR

DIEP0TXFSTS

DIEP0_CTL

DIEP0_INT

DIEP0_TSIZ

DIEP0_DMAADDR

DIEP0_DTXFSTS

DIEP1_CTL

DIEP1_INT

DIEP1_TSIZ

DIEP1_DMAADDR

DIEP1_DTXFSTS

DIEP2_CTL

DIEP2_INT

DIEP2_TSIZ

DIEP2_DMAADDR

DIEP2_DTXFSTS

DIEP3_CTL

DIEP3_INT

DIEP3_TSIZ

DIEP3_DMAADDR

DIEP3_DTXFSTS

DIEP4_CTL

DIEP4_INT

DIEP4_TSIZ

DIEP4_DMAADDR

DIEP4_DTXFSTS

DIEP5_CTL

DIEP5_INT

DIEP5_TSIZ

DIEP5_DMAADDR

DIEP5_DTXFSTS

DOEP0CTL

DOEP0INT

DOEP0TSIZ

DOEP0DMAADDR

DOEP0_CTL

DOEP0_INT

DOEP0_TSIZ

DOEP0_DMAADDR

DOEP1_CTL

DOEP1_INT

DOEP1_TSIZ

DOEP1_DMAADDR

DOEP2_CTL

DOEP2_INT

DOEP2_TSIZ

DOEP2_DMAADDR

DOEP3_CTL

DOEP3_INT

DOEP3_TSIZ

DOEP3_DMAADDR

DOEP4_CTL

DOEP4_INT

DOEP4_TSIZ

DOEP4_DMAADDR

DOEP5_CTL

DOEP5_INT

DOEP5_TSIZ

DOEP5_DMAADDR

PCGCCTL


CTRL

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSENAP SELFPOWERED LEMOSCCTRL LEMPHYCTRL LEMIDLEEN IDCDEN OTGCLKCDIS OTGIDINDIS OTGPHYCTRLDIS DCDEN PDEN SDEN

VBUSENAP : VBUSEN Active Polarity
bits : 0 - 0 (1 bit)
access : read-write

SELFPOWERED : PHY Power
bits : 3 - 3 (1 bit)
access : read-write

LEMOSCCTRL : Low Energy Mode Oscillator Control
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : NONE

Low Energy Mode has no effect on neither USBC or USHFRCO.

0x00000001 : GATE

The USBC clock is gated when Low Energy Mode is active.

End of enumeration elements list.

LEMPHYCTRL : Low Energy Mode USB PHY Control
bits : 7 - 7 (1 bit)
access : read-write

LEMIDLEEN : Low Energy Mode on Bus Idle Enable
bits : 9 - 9 (1 bit)
access : read-write

IDCDEN : ID Pull-up Enable
bits : 12 - 12 (1 bit)
access : read-write

OTGCLKCDIS : OTG CLKC Disable
bits : 25 - 25 (1 bit)
access : read-write

OTGIDINDIS : OTG ID Input Disable
bits : 26 - 26 (1 bit)
access : read-write

OTGPHYCTRLDIS : OTG Control Signals to PHY Disable
bits : 27 - 27 (1 bit)
access : read-write

DCDEN : Data Contact Detection Enable
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

DCD is disabled.

0x00000002 : TIMEOUT

Only DCD timeout will be initiated.

0x00000003 : ENABLED

Full DCD operation (physical contact and timeout) will be initiated.

End of enumeration elements list.

PDEN : Primary Detection Enable
bits : 30 - 30 (1 bit)
access : read-write

SDEN : Secondary Detection Enable
bits : 31 - 31 (1 bit)
access : read-write


IFC

Interrupt Flag Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDETH VBUSDETL ERR DCD PD SD

VBUSDETH : Clear VBUSDETH Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

VBUSDETL : Clear VBUSDETL Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

ERR : Clear ERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

DCD : Clear DCD Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

PD : Clear PD Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

SD : Clear SD Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDETH VBUSDETL ERR DCD PD SD

VBUSDETH : VBUSDETH Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

VBUSDETL : VBUSDETL Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

ERR : ERR Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

DCD : DCD Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

PD : PD Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

SD : SD Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYPEN VBUSENPEN

PHYPEN : USB PHY Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

VBUSENPEN : VBUSEN Pin Enable
bits : 1 - 1 (1 bit)
access : read-write


CDCONF

Charger Detect Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDCONF CDCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDTOCONF

DCDTOCONF : DCD Timeout (TDCD_TIMEOUT) Configuration
bits : 0 - 9 (10 bit)
access : read-write


CMD

Command Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTCD STOPCD

STARTCD : Start Charger Detection Enabled
bits : 0 - 0 (1 bit)
access : write-only

STOPCD : Start Charger Detection in Progress
bits : 1 - 1 (1 bit)
access : write-only


DATTRIM1

Data TRIM 1 Values for USB DP and DM
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATTRIM1 DATTRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROUT ENDLYPULLUP DLYPULLUPFS VCRSFS TFDMFS TRDMFS TFDPFS TRDPFS

ROUT : Trim for DP and DM Output Impedance for Both FS and LS
bits : 0 - 5 (6 bit)
access : read-write

ENDLYPULLUP : Enables Delay of Pull in TX Mode for Both FS and LS
bits : 7 - 7 (1 bit)
access : read-write

DLYPULLUPFS : Trim for Rising Crossover Voltage in FS
bits : 8 - 9 (2 bit)
access : read-write

VCRSFS : Trim for Falling Crossover Voltage in FS
bits : 10 - 11 (2 bit)
access : read-write

TFDMFS : Trim for DM Fall Time in FS
bits : 12 - 13 (2 bit)
access : read-write

TRDMFS : Trim for DM Rise Time in FS
bits : 14 - 15 (2 bit)
access : read-write

TFDPFS : Trim for DP Fall Time in FS
bits : 16 - 17 (2 bit)
access : read-write

TRDPFS : Trim for DP Rise Time in FS
bits : 18 - 19 (2 bit)
access : read-write


LEMCTRL

USB LEM Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEMCTRL LEMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEBASE

TIMEBASE : Set the Number of LFC Clk Counts to Form 3ms
bits : 0 - 9 (10 bit)
access : read-write


STATUS

System Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDETH LEMACTIVE DCDTO SDP CDP DCP ACAFS ACALS USBCDBUSY

VBUSDETH : VBUS Detect High
bits : 0 - 0 (1 bit)
access : read-only

LEMACTIVE : Low Energy Mode Active
bits : 2 - 2 (1 bit)
access : read-only

DCDTO : Data Contact Detection Timeout
bits : 8 - 8 (1 bit)
access : read-only

SDP : Standard Downstream Port Detected
bits : 9 - 9 (1 bit)
access : read-only

CDP : Charging Downstream Port Detected
bits : 10 - 10 (1 bit)
access : read-only

DCP : Dedicated Charging Port Detected
bits : 11 - 11 (1 bit)
access : read-only

ACAFS : ACA Full Speed TypeB Device
bits : 12 - 12 (1 bit)
access : read-only

ACALS : ACA Low Speed TypeB Device
bits : 13 - 13 (1 bit)
access : read-only

USBCDBUSY : USB Charger Detect Busy
bits : 15 - 15 (1 bit)
access : read-only


ROUTELOC0

I/O Routing Location Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC0 ROUTELOC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSENPENLOC

VBUSENPENLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.


IF

Interrupt Flag Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDETH VBUSDETL ERR DCD PD SD

VBUSDETH : VBUS Detect High Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

VBUSDETL : VBUS Detect Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

ERR : Detection Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only

DCD : Data Contact Detection Complete Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only

PD : Primary Detection Complete Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-only

SD : Secondary Detection Complete Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDETH VBUSDETL ERR DCD PD SD

VBUSDETH : Set VBUSDETH Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

VBUSDETL : Set VBUSDETL Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

ERR : Set ERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

DCD : Set DCD Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

PD : Set PD Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

SD : Set SD Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only


GOTGCTL

OTG Control and Status Register
address_offset : 0xDE000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GOTGCTL GOTGCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SESREQSCS SESREQ VBVALIDOVEN VBVALIDOVVAL AVALIDOVEN AVALIDOVVAL BVALIDOVEN BVALIDOVVAL HSTNEGSCS HNPREQ HSTSETHNPEN DEVHNPEN EHEN DBNCEFLTRBYPASS CONIDSTS DBNCTIME ASESVLD BSESVLD OTGVER CURMOD

SESREQSCS : Session Request Success
bits : 0 - 0 (1 bit)
access : read-only

SESREQ : Session Request
bits : 1 - 1 (1 bit)
access : read-write

VBVALIDOVEN : VBUS Valid Override Enable
bits : 2 - 2 (1 bit)
access : read-write

VBVALIDOVVAL : VBUS Valid OverrideValue
bits : 3 - 3 (1 bit)
access : read-write

AVALIDOVEN : A-Peripheral Session Valid Override Enable
bits : 4 - 4 (1 bit)
access : read-write

AVALIDOVVAL : A-Peripheral Session Valid OverrideValue
bits : 5 - 5 (1 bit)
access : read-write

BVALIDOVEN : B-Peripheral Session Valid Override Enable
bits : 6 - 6 (1 bit)
access : read-write

BVALIDOVVAL : B-Peripheral Session Valid OverrideValue
bits : 7 - 7 (1 bit)
access : read-write

HSTNEGSCS : Host Negotiation Success
bits : 8 - 8 (1 bit)
access : read-only

HNPREQ : HNP Request
bits : 9 - 9 (1 bit)
access : read-write

HSTSETHNPEN : Host Set HNP Enable
bits : 10 - 10 (1 bit)
access : read-write

DEVHNPEN : Device HNP Enabled
bits : 11 - 11 (1 bit)
access : read-write

EHEN : Embedded Host Enable
bits : 12 - 12 (1 bit)
access : read-write

DBNCEFLTRBYPASS : Debounce Filter Bypass
bits : 15 - 15 (1 bit)
access : read-write

CONIDSTS : Connector ID Status
bits : 16 - 16 (1 bit)
access : read-only

DBNCTIME : Long/Short Debounce Time
bits : 17 - 17 (1 bit)
access : read-only

ASESVLD : A-Session Valid
bits : 18 - 18 (1 bit)
access : read-only

BSESVLD : B-Session Valid
bits : 19 - 19 (1 bit)
access : read-only

OTGVER : OTG Version
bits : 20 - 20 (1 bit)
access : read-write

CURMOD : Current Mode of Operation
bits : 21 - 21 (1 bit)
access : read-only


GOTGINT

OTG Interrupt Register
address_offset : 0xDE004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GOTGINT GOTGINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SESENDDET SESREQSUCSTSCHNG HSTNEGSUCSTSCHNG HSTNEGDET ADEVTOUTCHG DBNCEDONE

SESENDDET : Session End Detected
bits : 2 - 2 (1 bit)
access : read-write

SESREQSUCSTSCHNG : Session Request Success Status Change
bits : 8 - 8 (1 bit)
access : read-write

HSTNEGSUCSTSCHNG : Host Negotiation Success Status Change
bits : 9 - 9 (1 bit)
access : read-write

HSTNEGDET : Host Negotiation Detected
bits : 17 - 17 (1 bit)
access : read-write

ADEVTOUTCHG : A-Device Timeout Change
bits : 18 - 18 (1 bit)
access : read-write

DBNCEDONE : Debounce Done
bits : 19 - 19 (1 bit)
access : read-write


GAHBCFG

AHB Configuration Register
address_offset : 0xDE008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAHBCFG GAHBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLBLINTRMSK HBSTLEN DMAEN NPTXFEMPLVL PTXFEMPLVL REMMEMSUPP NOTIALLDMAWRIT AHBSINGLE

GLBLINTRMSK : Global Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

HBSTLEN : Burst Length/Type
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

0x00000000 : SINGLE

Single transfer.

0x00000001 : INCR

Incrementing burst of unspecified length.

0x00000003 : INCR4

4-beat incrementing burst.

0x00000005 : INCR8

8-beat incrementing burst.

0x00000007 : INCR16

16-beat incrementing burst.

End of enumeration elements list.

DMAEN : DMA Enable
bits : 5 - 5 (1 bit)
access : read-write

NPTXFEMPLVL : Non-Periodic TxFIFO Empty Level
bits : 7 - 7 (1 bit)
access : read-write

PTXFEMPLVL : Periodic TxFIFO Empty Level
bits : 8 - 8 (1 bit)
access : read-write

REMMEMSUPP : Remote Memory Support
bits : 21 - 21 (1 bit)
access : read-write

NOTIALLDMAWRIT : Notify All Dma Write Transactions
bits : 22 - 22 (1 bit)
access : read-write

AHBSINGLE : AHB Single Support
bits : 23 - 23 (1 bit)
access : read-write


GUSBCFG

USB Configuration Register
address_offset : 0xDE00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUSBCFG GUSBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUTCAL FSINTF SRPCAP HNPCAP USBTRDTIM TERMSELDLPULSE TXENDDELAY FORCEHSTMODE FORCEDEVMODE CORRUPTTXPKT

TOUTCAL : Timeout Calibration (host and device)
bits : 0 - 2 (3 bit)
access : read-write

FSINTF : Full-Speed Serial Interface Select
bits : 5 - 5 (1 bit)
access : read-write

SRPCAP : SRP-Capable
bits : 8 - 8 (1 bit)
access : read-write

HNPCAP : HNP-Capable
bits : 9 - 9 (1 bit)
access : read-write

USBTRDTIM : USB Turnaround Time
bits : 10 - 13 (4 bit)
access : read-write

TERMSELDLPULSE : TermSel DLine Pulsing Selection
bits : 22 - 22 (1 bit)
access : read-write

TXENDDELAY : Tx End Delay
bits : 28 - 28 (1 bit)
access : read-write

FORCEHSTMODE : Force Host Mode
bits : 29 - 29 (1 bit)
access : read-write

FORCEDEVMODE : Force Device Mode
bits : 30 - 30 (1 bit)
access : read-write

CORRUPTTXPKT : Corrupt Tx packet (host and device)
bits : 31 - 31 (1 bit)
access : write-only


GRSTCTL

Reset Register
address_offset : 0xDE010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRSTCTL GRSTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSFTRST PIUFSSFTRST FRMCNTRRST RXFFLSH TXFFLSH TXFNUM DMAREQ AHBIDLE

CSFTRST : Core Soft Reset (host and device)
bits : 0 - 0 (1 bit)
access : read-write

PIUFSSFTRST : PIU FS Dedicated Controller Soft Reset
bits : 1 - 1 (1 bit)
access : read-write

FRMCNTRRST : Host Frame Counter Reset
bits : 2 - 2 (1 bit)
access : read-write

RXFFLSH : RxFIFO Flush
bits : 4 - 4 (1 bit)
access : read-write

TXFFLSH : TxFIFO Flush
bits : 5 - 5 (1 bit)
access : read-write

TXFNUM : TxFIFO Number (host and device)
bits : 6 - 10 (5 bit)
access : read-write

Enumeration:

0x00000000 : F0

Host mode: Non-periodic TxFIFO flush. Device: Tx FIFO 0 flush

0x00000001 : F1

Host mode: Periodic TxFIFO flush. Device: TXFIFO 1 flush.

0x00000002 : F2

Device mode: TXFIFO 2 flush.

0x00000003 : F3

Device mode: TXFIFO 3 flush.

0x00000004 : F4

Device mode: TXFIFO 4 flush.

0x00000005 : F5

Device mode: TXFIFO 5 flush.

0x00000006 : F6

Device mode: TXFIFO 6 flush.

0x00000010 : FALL

Flush all the transmit FIFOs in device or host mode.

End of enumeration elements list.

DMAREQ : DMA Request Signal
bits : 30 - 30 (1 bit)
access : read-only

AHBIDLE : AHB Master Idle
bits : 31 - 31 (1 bit)
access : read-only


GINTSTS

Interrupt Register
address_offset : 0xDE014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTSTS GINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURMOD MODEMIS OTGINT SOF RXFLVL NPTXFEMP GINNAKEFF GOUTNAKEFF ERLYSUSP USBSUSP USBRST ENUMDONE ISOOUTDROP EOPF EPMIS IEPINT OEPINT INCOMPISOIN INCOMPLP FETSUSP RESETDET PRTINT HCHINT PTXFEMP CONIDSTSCHNG DISCONNINT SESSREQINT WKUPINT

CURMOD : Current Mode of Operation (host and device)
bits : 0 - 0 (1 bit)
access : read-only

MODEMIS : Mode Mismatch Interrupt (host and device)
bits : 1 - 1 (1 bit)
access : read-write

OTGINT : OTG Interrupt (host and device)
bits : 2 - 2 (1 bit)
access : read-only

SOF : Start of Frame (host and device)
bits : 3 - 3 (1 bit)
access : read-write

RXFLVL : RxFIFO Non-Empty (host and device)
bits : 4 - 4 (1 bit)
access : read-only

NPTXFEMP : Non-Periodic TxFIFO Empty (host only)
bits : 5 - 5 (1 bit)
access : read-only

GINNAKEFF : Global IN Non-periodic NAK Effective (device only)
bits : 6 - 6 (1 bit)
access : read-only

GOUTNAKEFF : Global OUT NAK Effective (device only)
bits : 7 - 7 (1 bit)
access : read-only

ERLYSUSP : Early Suspend (device only)
bits : 10 - 10 (1 bit)
access : read-write

USBSUSP : USB Suspend (device only)
bits : 11 - 11 (1 bit)
access : read-write

USBRST : USB Reset (device only)
bits : 12 - 12 (1 bit)
access : read-write

ENUMDONE : Enumeration Done (device only)
bits : 13 - 13 (1 bit)
access : read-write

ISOOUTDROP : Isochronous OUT Packet Dropped Interrupt (device only)
bits : 14 - 14 (1 bit)
access : read-write

EOPF : End of Periodic Frame Interrupt
bits : 15 - 15 (1 bit)
access : read-write

EPMIS : Endpoint Mismatch Interrupt (device only)
bits : 17 - 17 (1 bit)
access : read-write

IEPINT : IN Endpoints Interrupt (device only)
bits : 18 - 18 (1 bit)
access : read-only

OEPINT : OUT Endpoints Interrupt (device only)
bits : 19 - 19 (1 bit)
access : read-only

INCOMPISOIN : Incomplete Isochronous IN Transfer (device only)
bits : 20 - 20 (1 bit)
access : read-write

INCOMPLP : Incomplete Periodic Transfer (device only)
bits : 21 - 21 (1 bit)
access : read-write

FETSUSP : Data Fetch Suspended (device only)
bits : 22 - 22 (1 bit)
access : read-write

RESETDET : Reset detected Interrupt (device only)
bits : 23 - 23 (1 bit)
access : read-write

PRTINT : Host Port Interrupt (host only)
bits : 24 - 24 (1 bit)
access : read-only

HCHINT : Host Channels Interrupt (host only)
bits : 25 - 25 (1 bit)
access : read-only

PTXFEMP : Periodic TxFIFO Empty (host only)
bits : 26 - 26 (1 bit)
access : read-only

CONIDSTSCHNG : Connector ID Status Change (host and device)
bits : 28 - 28 (1 bit)
access : read-write

DISCONNINT : Disconnect Detected Interrupt (host only)
bits : 29 - 29 (1 bit)
access : read-write

SESSREQINT : Session Request/New Session Detected Interrupt (host and device)
bits : 30 - 30 (1 bit)
access : read-write

WKUPINT : Resume/Remote Wakeup Detected Interrupt (host and device)
bits : 31 - 31 (1 bit)
access : read-write


GINTMSK

Interrupt Mask Register
address_offset : 0xDE018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTMSK GINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEMISMSK OTGINTMSK SOFMSK RXFLVLMSK NPTXFEMPMSK GINNAKEFFMSK GOUTNAKEFFMSK ERLYSUSPMSK USBSUSPMSK USBRSTMSK ENUMDONEMSK ISOOUTDROPMSK EOPFMSK EPMISMSK IEPINTMSK OEPINTMSK INCOMPISOINMSK INCOMPLPMSK FETSUSPMSK RESETDETMSK PRTINTMSK HCHINTMSK PTXFEMPMSK CONIDSTSCHNGMSK DISCONNINTMSK SESSREQINTMSK WKUPINTMSK

MODEMISMSK : Mode Mismatch Interrupt Mask (host and device)
bits : 1 - 1 (1 bit)
access : read-write

OTGINTMSK : OTG Interrupt Mask (host and device)
bits : 2 - 2 (1 bit)
access : read-write

SOFMSK : Start of Frame Mask (host and device)
bits : 3 - 3 (1 bit)
access : read-write

RXFLVLMSK : Receive FIFO Non-Empty Mask (host and device)
bits : 4 - 4 (1 bit)
access : read-write

NPTXFEMPMSK : Non-Periodic TxFIFO Empty Mask (host only)
bits : 5 - 5 (1 bit)
access : read-write

GINNAKEFFMSK : Global Non-periodic IN NAK Effective Mask (device only)
bits : 6 - 6 (1 bit)
access : read-write

GOUTNAKEFFMSK : Global OUT NAK Effective Mask (device only)
bits : 7 - 7 (1 bit)
access : read-write

ERLYSUSPMSK : Early Suspend Mask (device only)
bits : 10 - 10 (1 bit)
access : read-write

USBSUSPMSK : USB Suspend Mask (device only)
bits : 11 - 11 (1 bit)
access : read-write

USBRSTMSK : USB Reset Mask (device only)
bits : 12 - 12 (1 bit)
access : read-write

ENUMDONEMSK : Enumeration Done Mask (device only)
bits : 13 - 13 (1 bit)
access : read-write

ISOOUTDROPMSK : Isochronous OUT Packet Dropped Interrupt Mask (device only)
bits : 14 - 14 (1 bit)
access : read-write

EOPFMSK : End of Periodic Frame Interrupt Mask (device only)
bits : 15 - 15 (1 bit)
access : read-write

EPMISMSK : Endpoint Mismatch Interrupt Mask (device only)
bits : 17 - 17 (1 bit)
access : read-write

IEPINTMSK : IN Endpoints Interrupt Mask (device only)
bits : 18 - 18 (1 bit)
access : read-write

OEPINTMSK : OUT Endpoints Interrupt Mask (device only)
bits : 19 - 19 (1 bit)
access : read-write

INCOMPISOINMSK : Incomplete Isochronous IN Transfer Mask (device only)
bits : 20 - 20 (1 bit)
access : read-write

INCOMPLPMSK : Incomplete Periodic Transfer Mask (host only)
bits : 21 - 21 (1 bit)
access : read-write

FETSUSPMSK : Data Fetch Suspended Mask (device only)
bits : 22 - 22 (1 bit)
access : read-write

RESETDETMSK : Reset detected Interrupt Mask (device only)
bits : 23 - 23 (1 bit)
access : read-write

PRTINTMSK : Host Port Interrupt Mask (host only)
bits : 24 - 24 (1 bit)
access : read-write

HCHINTMSK : Host Channels Interrupt Mask (host only)
bits : 25 - 25 (1 bit)
access : read-write

PTXFEMPMSK : Periodic TxFIFO Empty Mask (host only)
bits : 26 - 26 (1 bit)
access : read-write

CONIDSTSCHNGMSK : Connector ID Status Change Mask (host and device)
bits : 28 - 28 (1 bit)
access : read-write

DISCONNINTMSK : Disconnect Detected Interrupt Mask (host and device)
bits : 29 - 29 (1 bit)
access : read-write

SESSREQINTMSK : Session Request/New Session Detected Interrupt Mask (host and device)
bits : 30 - 30 (1 bit)
access : read-write

WKUPINTMSK : Resume/Remote Wakeup Detected Interrupt Mask (host and device)
bits : 31 - 31 (1 bit)
access : read-write


GRXSTSR

Receive Status Debug Read Register
address_offset : 0xDE01C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GRXSTSR GRXSTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM BCNT DPID PKTSTS FN

CHNUM : Channel Number
bits : 0 - 3 (4 bit)
access : read-only

BCNT : Byte Count
bits : 4 - 14 (11 bit)
access : read-only

DPID : Data PID
bits : 15 - 16 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA1

DATA1 PID.

0x00000002 : DATA2

DATA2 PID.

0x00000003 : MDATA

MDATA PID.

End of enumeration elements list.

PKTSTS : Packet Status
bits : 17 - 20 (4 bit)
access : read-only

Enumeration:

0x00000001 : GOUTNAK

Device mode: Global OUT NAK (triggers an interrupt).

0x00000002 : PKTRCV

Host mode: IN data packet received. Device mode: OUT data packet received.

0x00000003 : XFERCOMPL

Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).

0x00000004 : SETUPCOMPL

Device mode: SETUP transaction completed (triggers an interrupt).

0x00000005 : TGLERR

Host mode: Data toggle error (triggers an interrupt).

0x00000006 : SETUPRCV

Device mode: SETUP data packet received.

0x00000007 : CHLT

Host mode: Channel halted (triggers an interrupt).

End of enumeration elements list.

FN : Frame Number
bits : 21 - 24 (4 bit)
access : read-only


GRXSTSP

Receive Status Read /Pop Register
address_offset : 0xDE020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GRXSTSP GRXSTSP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM BCNT DPID PKTSTS FN

CHNUM : Channel Number
bits : 0 - 3 (4 bit)
access : read-only

BCNT : Byte Count
bits : 4 - 14 (11 bit)
access : read-only

DPID : Data PID (host or device)
bits : 15 - 16 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA1

DATA1 PID.

0x00000002 : DATA2

DATA2 PID.

0x00000003 : MDATA

MDATA PID.

End of enumeration elements list.

PKTSTS : Packet Status (host or device)
bits : 17 - 20 (4 bit)
access : read-only

Enumeration:

0x00000001 : GOUTNAK

Device mode: Global OUT NAK (triggers an interrupt).

0x00000002 : PKTRCV

Host mode: IN data packet received. Device mode: OUT data packet received.

0x00000003 : XFERCOMPL

Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).

0x00000004 : SETUPCOMPL

Device mode: SETUP transaction completed (triggers an interrupt).

0x00000005 : TGLERR

Host mode: Data toggle error (triggers an interrupt).

0x00000006 : SETUPRCV

Device mode: SETUP data packet received.

0x00000007 : CHLT

Host mode: Channel halted (triggers an interrupt).

End of enumeration elements list.

FN : Frame Number
bits : 21 - 24 (4 bit)
access : read-only


GRXFSIZ

Receive FIFO Size Register
address_offset : 0xDE024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRXFSIZ GRXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFDEP

RXFDEP : RxFIFO Depth
bits : 0 - 9 (10 bit)
access : read-write


GNPTXFSIZ

Non-periodic Transmit FIFO Size Register
address_offset : 0xDE028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GNPTXFSIZ GNPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSTADDR NPTXFINEPTXF0DEP

NPTXFSTADDR : Non-periodic Transmit RAM Start Address
bits : 0 - 15 (16 bit)
access : read-write

NPTXFINEPTXF0DEP : Non-periodic TxFIFO Depth (host only) / IN Endpoint TxFIFO 0 Depth (device only)
bits : 16 - 31 (16 bit)
access : read-write


GNPTXSTS

Non-periodic Transmit FIFO/Queue Status Register
address_offset : 0xDE02C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GNPTXSTS GNPTXSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSPCAVAIL NPTXQSPCAVAIL NPTXQTOP

NPTXFSPCAVAIL : Non-periodic TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only

NPTXQSPCAVAIL : Non-periodic Transmit Request Queue Space Available
bits : 16 - 23 (8 bit)
access : read-only

NPTXQTOP : Top of the Non-periodic Transmit Request Queue
bits : 24 - 30 (7 bit)
access : read-only


GSNPSID

Synopsys ID Register
address_offset : 0xDE040 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GSNPSID GSNPSID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNOPSYSID

SYNOPSYSID :
bits : 0 - 31 (32 bit)
access : read-only


GDFIFOCFG

Global DFIFO Configuration Register
address_offset : 0xDE05C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GDFIFOCFG GDFIFOCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GDFIFOCFG EPINFOBASEADDR

GDFIFOCFG :
bits : 0 - 15 (16 bit)
access : read-write

EPINFOBASEADDR :
bits : 16 - 31 (16 bit)
access : read-write


HPTXFSIZ

Host Periodic Transmit FIFO Size Register
address_offset : 0xDE100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPTXFSIZ HPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFSTADDR PTXFSIZE

PTXFSTADDR : Host Periodic TxFIFO Start Address
bits : 0 - 10 (11 bit)
access : read-write

PTXFSIZE : Host Periodic TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF1

Device IN Endpoint Transmit FIFO Size Register 1
address_offset : 0xDE104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF1 DIEPTXF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 10 (11 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF2

Device IN Endpoint Transmit FIFO Size Register 2
address_offset : 0xDE108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF2 DIEPTXF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 10 (11 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF3

Device IN Endpoint Transmit FIFO Size Register 3
address_offset : 0xDE10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF3 DIEPTXF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF4

Device IN Endpoint Transmit FIFO Size Register 4
address_offset : 0xDE110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF4 DIEPTXF4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF5

Device IN Endpoint Transmit FIFO Size Register 5
address_offset : 0xDE114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF5 DIEPTXF5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF6

Device IN Endpoint Transmit FIFO Size Register 6
address_offset : 0xDE118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF6 DIEPTXF6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


HCFG

Host Configuration Register
address_offset : 0xDE400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCFG HCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSLSPCLKSEL FSLSSUPP ENA32KHZS RESVALID MODECHTIMEN

FSLSPCLKSEL : FS/LS PHY Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000001 : DIV1

Internal PHY clock is running at 48 MHz (undivided).

0x00000002 : DIV8

Internal PHY clock is running at 6 MHz (48 MHz divided by 8).

End of enumeration elements list.

FSLSSUPP : FS- and LS-Only Support
bits : 2 - 2 (1 bit)
access : read-write

ENA32KHZS : Enable 32 kHz Suspend Mode
bits : 7 - 7 (1 bit)
access : read-write

RESVALID : Resume Validation Period
bits : 8 - 15 (8 bit)
access : read-write

MODECHTIMEN : Mode Change Time
bits : 31 - 31 (1 bit)
access : read-write


HFIR

Host Frame Interval Register
address_offset : 0xDE404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFIR HFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRINT HFIRRLDCTRL

FRINT : Frame Interval
bits : 0 - 15 (16 bit)
access : read-write

HFIRRLDCTRL : Reload Control
bits : 16 - 16 (1 bit)
access : read-write


HFNUM

Host Frame Number/Frame Time Remaining Register
address_offset : 0xDE408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFNUM HFNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNUM FRREM

FRNUM : Frame Number
bits : 0 - 15 (16 bit)
access : read-only

FRREM : Frame Time Remaining
bits : 16 - 31 (16 bit)
access : read-only


HPTXSTS

Host Periodic Transmit FIFO/Queue Status Register
address_offset : 0xDE410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HPTXSTS HPTXSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFSPCAVAIL PTXQSPCAVAIL PTXQTOP

PTXFSPCAVAIL : Periodic Transmit Data FIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only

PTXQSPCAVAIL : Periodic Transmit Request Queue Space Available
bits : 16 - 23 (8 bit)
access : read-only

PTXQTOP : Top of the Periodic Transmit Request Queue
bits : 24 - 31 (8 bit)
access : read-only


HAINT

Host All Channels Interrupt Register
address_offset : 0xDE414 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HAINT HAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINT

HAINT : Channel Interrupt for channel 0 - 13.
bits : 0 - 13 (14 bit)
access : read-only


HAINTMSK

Host All Channels Interrupt Mask Register
address_offset : 0xDE418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HAINTMSK HAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINTMSK

HAINTMSK : Channel Interrupt Mask for channel 0 - 13
bits : 0 - 13 (14 bit)
access : read-write


HPRT

Host Port Control and Status Register
address_offset : 0xDE440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPRT HPRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTCONNSTS PRTCONNDET PRTENA PRTENCHNG PRTOVRCURRACT PRTOVRCURRCHNG PRTRES PRTSUSP PRTRST PRTLNSTS PRTPWR PRTTSTCTL PRTSPD

PRTCONNSTS : Port Connect Status
bits : 0 - 0 (1 bit)
access : read-only

PRTCONNDET : Port Connect Detected
bits : 1 - 1 (1 bit)
access : read-write

PRTENA : Port Enable
bits : 2 - 2 (1 bit)
access : read-write

PRTENCHNG : Port Enable/Disable Change
bits : 3 - 3 (1 bit)
access : read-write

PRTOVRCURRACT : Port Overcurrent Active
bits : 4 - 4 (1 bit)
access : read-only

PRTOVRCURRCHNG : Port Overcurrent Change
bits : 5 - 5 (1 bit)
access : read-write

PRTRES : Port Resume
bits : 6 - 6 (1 bit)
access : read-write

PRTSUSP : Port Suspend
bits : 7 - 7 (1 bit)
access : read-write

PRTRST : Port Reset
bits : 8 - 8 (1 bit)
access : read-write

PRTLNSTS : Port Line Status
bits : 10 - 11 (2 bit)
access : read-only

PRTPWR : Port Power
bits : 12 - 12 (1 bit)
access : read-write

PRTTSTCTL : Port Test Control
bits : 13 - 16 (4 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Test mode disabled.

0x00000001 : J

Test_J mode.

0x00000002 : K

Test_K mode.

0x00000003 : SE0NAK

Test_SE0_NAK mode.

0x00000004 : PACKET

Test_Packet mode.

0x00000005 : FORCE

Test_Force_Enable.

End of enumeration elements list.

PRTSPD : Port Speed
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

0x00000001 : FS

Full speed.

0x00000002 : LS

Low speed.

End of enumeration elements list.


HC0_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0_CHAR HC0_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC0_SPLT

Host Channel x Split Control Register
address_offset : 0xDE504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0_SPLT HC0_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC0_INT

Host Channel x Interrupt Register
address_offset : 0xDE508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0_INT HC0_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC0_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0_INTMSK HC0_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC0_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0_TSIZ HC0_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC0_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0_DMAADDR HC0_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC1_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC1_CHAR HC1_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC1_SPLT

Host Channel x Split Control Register
address_offset : 0xDE524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC1_SPLT HC1_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC1_INT

Host Channel x Interrupt Register
address_offset : 0xDE528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC1_INT HC1_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC1_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC1_INTMSK HC1_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC1_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC1_TSIZ HC1_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC1_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC1_DMAADDR HC1_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC2_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC2_CHAR HC2_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC2_SPLT

Host Channel x Split Control Register
address_offset : 0xDE544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC2_SPLT HC2_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC2_INT

Host Channel x Interrupt Register
address_offset : 0xDE548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC2_INT HC2_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC2_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC2_INTMSK HC2_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC2_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC2_TSIZ HC2_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC2_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC2_DMAADDR HC2_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC3_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC3_CHAR HC3_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC3_SPLT

Host Channel x Split Control Register
address_offset : 0xDE564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC3_SPLT HC3_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC3_INT

Host Channel x Interrupt Register
address_offset : 0xDE568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC3_INT HC3_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC3_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC3_INTMSK HC3_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC3_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC3_TSIZ HC3_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC3_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC3_DMAADDR HC3_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC4_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC4_CHAR HC4_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC4_SPLT

Host Channel x Split Control Register
address_offset : 0xDE584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC4_SPLT HC4_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC4_INT

Host Channel x Interrupt Register
address_offset : 0xDE588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC4_INT HC4_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC4_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC4_INTMSK HC4_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC4_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC4_TSIZ HC4_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC4_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC4_DMAADDR HC4_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC5_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC5_CHAR HC5_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC5_SPLT

Host Channel x Split Control Register
address_offset : 0xDE5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC5_SPLT HC5_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC5_INT

Host Channel x Interrupt Register
address_offset : 0xDE5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC5_INT HC5_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC5_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC5_INTMSK HC5_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC5_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC5_TSIZ HC5_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC5_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC5_DMAADDR HC5_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC6_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC6_CHAR HC6_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC6_SPLT

Host Channel x Split Control Register
address_offset : 0xDE5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC6_SPLT HC6_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC6_INT

Host Channel x Interrupt Register
address_offset : 0xDE5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC6_INT HC6_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC6_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC6_INTMSK HC6_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC6_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC6_TSIZ HC6_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC6_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC6_DMAADDR HC6_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC7_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC7_CHAR HC7_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC7_SPLT

Host Channel x Split Control Register
address_offset : 0xDE5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC7_SPLT HC7_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC7_INT

Host Channel x Interrupt Register
address_offset : 0xDE5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC7_INT HC7_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC7_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC7_INTMSK HC7_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC7_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC7_TSIZ HC7_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC7_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC7_DMAADDR HC7_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC8_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC8_CHAR HC8_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC8_SPLT

Host Channel x Split Control Register
address_offset : 0xDE604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC8_SPLT HC8_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC8_INT

Host Channel x Interrupt Register
address_offset : 0xDE608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC8_INT HC8_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC8_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC8_INTMSK HC8_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC8_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC8_TSIZ HC8_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC8_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC8_DMAADDR HC8_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC9_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC9_CHAR HC9_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC9_SPLT

Host Channel x Split Control Register
address_offset : 0xDE624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC9_SPLT HC9_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC9_INT

Host Channel x Interrupt Register
address_offset : 0xDE628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC9_INT HC9_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC9_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC9_INTMSK HC9_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC9_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC9_TSIZ HC9_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC9_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC9_DMAADDR HC9_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC10_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC10_CHAR HC10_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC10_SPLT

Host Channel x Split Control Register
address_offset : 0xDE644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC10_SPLT HC10_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC10_INT

Host Channel x Interrupt Register
address_offset : 0xDE648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC10_INT HC10_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC10_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC10_INTMSK HC10_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC10_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC10_TSIZ HC10_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC10_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC10_DMAADDR HC10_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC11_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC11_CHAR HC11_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC11_SPLT

Host Channel x Split Control Register
address_offset : 0xDE664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC11_SPLT HC11_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC11_INT

Host Channel x Interrupt Register
address_offset : 0xDE668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC11_INT HC11_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC11_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC11_INTMSK HC11_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC11_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC11_TSIZ HC11_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC11_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC11_DMAADDR HC11_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC12_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC12_CHAR HC12_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC12_SPLT

Host Channel x Split Control Register
address_offset : 0xDE684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC12_SPLT HC12_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC12_INT

Host Channel x Interrupt Register
address_offset : 0xDE688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC12_INT HC12_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC12_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC12_INTMSK HC12_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC12_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC12_TSIZ HC12_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC12_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC12_DMAADDR HC12_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


HC13_CHAR

Host Channel x Characteristics Register
address_offset : 0xDE6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC13_CHAR HC13_CHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNUM EPDIR LSPDDEV EPTYPE MC DEVADDR ODDFRM CHDIS CHENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write

EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write

LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control endpoint.

0x00000001 : ISO

Isochronous endpoint.

0x00000002 : BULK

Bulk endpoint.

0x00000003 : INT

Interrupt endpoint.

End of enumeration elements list.

MC : Multi Count (MC) / Error Count
bits : 20 - 21 (2 bit)
access : read-write

DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write

ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write

CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write

CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write


HC13_SPLT

Host Channel x Split Control Register
address_offset : 0xDE6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC13_SPLT HC13_SPLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPSPLT SPLTENA

PRTADDR : Port Address
bits : 0 - 6 (7 bit)
access : read-write

HUBADDR : Hub Address
bits : 7 - 13 (7 bit)
access : read-write

XACTPOS : Transaction Position
bits : 14 - 15 (2 bit)
access : read-write

COMPSPLT : Do Complete Split
bits : 16 - 16 (1 bit)
access : read-write

SPLTENA : Split Enable
bits : 31 - 31 (1 bit)
access : read-write


HC13_INT

Host Channel x Interrupt Register
address_offset : 0xDE6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC13_INT HC13_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL CHHLTD AHBERR STALL NAK ACK XACTERR BBLERR FRMOVRUN DATATGLERR

XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write

CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write

XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write

BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write


HC13_INTMSK

Host Channel x Interrupt Mask Register
address_offset : 0xDE6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC13_INTMSK HC13_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK CHHLTDMSK AHBERRMSK STALLMSK NAKMSK ACKMSK XACTERRMSK BBLERRMSK FRMOVRUNMSK DATATGLERRMSK

XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write

CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write

NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write

ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write

XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write

BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write

FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write

DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write


HC13_TSIZ

Host Channel x Transfer Size Register
address_offset : 0xDE6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC13_TSIZ HC13_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT PID

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

PID : The Application Programs This Field With the Type of
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID.

0x00000002 : DATA1

DATA1 PID.

0x00000003 : MDATA

MDATA (non-control) / SETUP (control) PID.

End of enumeration elements list.


HC13_DMAADDR

Host Channel x DMA Address Register
address_offset : 0xDE6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC13_DMAADDR HC13_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DCFG

Device Configuration Register
address_offset : 0xDE800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG DCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVSPD NZSTSOUTHSHK ENA32KHZSUSP DEVADDR PERFRINT ENDEVOUTNAK XCVRDLY ERRATICINTMSK RESVALID

DEVSPD : Device Speed
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000002 : LS

Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.

0x00000003 : FS

Full speed (PHY clock is 48 MHz).

End of enumeration elements list.

NZSTSOUTHSHK : Non-Zero-Length Status OUT Handshake
bits : 2 - 2 (1 bit)
access : read-write

ENA32KHZSUSP : Enable 32 kHz Suspend Mode
bits : 3 - 3 (1 bit)
access : read-write

DEVADDR : Device Address
bits : 4 - 10 (7 bit)
access : read-write

PERFRINT : Periodic Frame Interval
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x00000000 : 80PCNT

80% of the frame interval.

0x00000001 : 85PCNT

85% of the frame interval.

0x00000002 : 90PCNT

90% of the frame interval.

0x00000003 : 95PCNT

95% of the frame interval.

End of enumeration elements list.

ENDEVOUTNAK : Enable Device OUT NAK
bits : 13 - 13 (1 bit)
access : read-write

XCVRDLY :
bits : 14 - 14 (1 bit)
access : read-write

ERRATICINTMSK :
bits : 15 - 15 (1 bit)
access : read-write

RESVALID : Resume Validation Period
bits : 26 - 31 (6 bit)
access : read-write


DCTL

Device Control Register
address_offset : 0xDE804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTL DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMTWKUPSIG SFTDISCON GNPINNAKSTS GOUTNAKSTS TSTCTL SGNPINNAK CGNPINNAK SGOUTNAK CGOUTNAK PWRONPRGDONE IGNRFRMNUM NAKONBBLE

RMTWKUPSIG : Remote Wakeup Signaling
bits : 0 - 0 (1 bit)
access : read-write

SFTDISCON : Soft Disconnect
bits : 1 - 1 (1 bit)
access : read-write

GNPINNAKSTS : Global Non-periodic IN NAK Status
bits : 2 - 2 (1 bit)
access : read-only

GOUTNAKSTS : Global OUT NAK Status
bits : 3 - 3 (1 bit)
access : read-only

TSTCTL : Test Control
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Test mode disabled.

0x00000001 : J

Test_J mode.

0x00000002 : K

Test_K mode.

0x00000003 : SE0NAK

Test_SE0_NAK mode.

0x00000004 : PACKET

Test_Packet mode.

0x00000005 : FORCE

Test_Force_Enable.

End of enumeration elements list.

SGNPINNAK : Set Global Non-periodic IN NAK
bits : 7 - 7 (1 bit)
access : write-only

CGNPINNAK : Clear Global Non-periodic IN NAK
bits : 8 - 8 (1 bit)
access : write-only

SGOUTNAK : Set Global OUT NAK
bits : 9 - 9 (1 bit)
access : write-only

CGOUTNAK : Clear Global OUT NAK
bits : 10 - 10 (1 bit)
access : write-only

PWRONPRGDONE : Power-On Programming Done
bits : 11 - 11 (1 bit)
access : read-write

IGNRFRMNUM : Ignore Frame number For Isochronous End points
bits : 15 - 15 (1 bit)
access : read-write

NAKONBBLE : NAK on Babble Error
bits : 16 - 16 (1 bit)
access : read-write


DSTS

Device Status Register
address_offset : 0xDE808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSTS DSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPSTS ENUMSPD ERRTICERR SOFFN DEVLNSTS

SUSPSTS : Suspend Status
bits : 0 - 0 (1 bit)
access : read-only

ENUMSPD : Enumerated Speed
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0x00000002 : LS

Low speed (PHY clock is running at 6 MHz).

0x00000003 : FS

Full speed (PHY clock is running at 48 MHz).

End of enumeration elements list.

ERRTICERR : Erratic Error
bits : 3 - 3 (1 bit)
access : read-only

SOFFN : Frame Number of the Received SOF
bits : 8 - 21 (14 bit)
access : read-only

DEVLNSTS : Device Line Status
bits : 22 - 23 (2 bit)
access : read-only


DIEPMSK

Device IN Endpoint Common Interrupt Mask Register
address_offset : 0xDE810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPMSK DIEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK EPDISBLDMSK AHBERRMSK TIMEOUTMSK INTKNTXFEMPMSK INTKNEPMISMSK INEPNAKEFFMSK TXFIFOUNDRNMSK NAKMSK

XFERCOMPLMSK : Transfer Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLDMSK : Endpoint Disabled Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUTMSK : Timeout Condition Mask
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMPMSK : IN Token Received When TxFIFO Empty Mask
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMISMSK : IN Token received with EP Mismatch Mask
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFFMSK : IN Endpoint NAK Effective Mask
bits : 6 - 6 (1 bit)
access : read-write

TXFIFOUNDRNMSK : Fifo Underrun Mask
bits : 8 - 8 (1 bit)
access : read-write

NAKMSK : NAK interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write


DOEPMSK

Device OUT Endpoint Common Interrupt Mask Register
address_offset : 0xDE814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPMSK DOEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK EPDISBLDMSK AHBERRMSK SETUPMSK OUTTKNEPDISMSK STSPHSERCVDMSK BACK2BACKSETUP OUTPKTERRMSK BBLEERRMSK NAKMSK

XFERCOMPLMSK : Transfer Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLDMSK : Endpoint Disabled Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUPMSK : SETUP Phase Done Mask
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDISMSK : OUT Token Received when Endpoint Disabled Mask
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVDMSK : Status Phase Received Mask
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received Mask
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERRMSK : OUT Packet Error Mask
bits : 8 - 8 (1 bit)
access : read-write

BBLEERRMSK : Babble Error interrupt Mask
bits : 12 - 12 (1 bit)
access : read-write

NAKMSK : NAK interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write


DAINT

Device All Endpoints Interrupt Register
address_offset : 0xDE818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAINT DAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPINT0 INEPINT1 INEPINT2 INEPINT3 INEPINT4 INEPINT5 INEPINT6 OUTEPINT0 OUTEPINT1 OUTEPINT2 OUTEPINT3 OUTEPINT4 OUTEPINT5 OUTEPINT6

INEPINT0 : IN Endpoint 0 Interrupt Bit
bits : 0 - 0 (1 bit)
access : read-only

INEPINT1 : IN Endpoint 1 Interrupt Bit
bits : 1 - 1 (1 bit)
access : read-only

INEPINT2 : IN Endpoint 2 Interrupt Bit
bits : 2 - 2 (1 bit)
access : read-only

INEPINT3 : IN Endpoint 3 Interrupt Bit
bits : 3 - 3 (1 bit)
access : read-only

INEPINT4 : IN Endpoint 4 Interrupt Bit
bits : 4 - 4 (1 bit)
access : read-only

INEPINT5 : IN Endpoint 5 Interrupt Bit
bits : 5 - 5 (1 bit)
access : read-only

INEPINT6 : IN Endpoint 6 Interrupt Bit
bits : 6 - 6 (1 bit)
access : read-only

OUTEPINT0 : OUT Endpoint 0 Interrupt Bit
bits : 16 - 16 (1 bit)
access : read-only

OUTEPINT1 : OUT Endpoint 1 Interrupt Bit
bits : 17 - 17 (1 bit)
access : read-only

OUTEPINT2 : OUT Endpoint 2 Interrupt Bit
bits : 18 - 18 (1 bit)
access : read-only

OUTEPINT3 : OUT Endpoint 3 Interrupt Bit
bits : 19 - 19 (1 bit)
access : read-only

OUTEPINT4 : OUT Endpoint 4 Interrupt Bit
bits : 20 - 20 (1 bit)
access : read-only

OUTEPINT5 : OUT Endpoint 5 Interrupt Bit
bits : 21 - 21 (1 bit)
access : read-only

OUTEPINT6 : OUT Endpoint 6 Interrupt Bit
bits : 22 - 22 (1 bit)
access : read-only


DAINTMSK

Device All Endpoints Interrupt Mask Register
address_offset : 0xDE81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAINTMSK DAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPMSK0 INEPMSK1 INEPMSK2 INEPMSK3 INEPMSK4 INEPMSK5 INEPMSK6 OUTEPMSK0 OUTEPMSK1 OUTEPMSK2 OUTEPMSK3 OUTEPMSK4 OUTEPMSK5 OUTEPMSK6

INEPMSK0 : IN Endpoint 0 Interrupt mask Bit
bits : 0 - 0 (1 bit)
access : read-write

INEPMSK1 : IN Endpoint 1 Interrupt mask Bit
bits : 1 - 1 (1 bit)
access : read-write

INEPMSK2 : IN Endpoint 2 Interrupt mask Bit
bits : 2 - 2 (1 bit)
access : read-write

INEPMSK3 : IN Endpoint 3 Interrupt mask Bit
bits : 3 - 3 (1 bit)
access : read-write

INEPMSK4 : IN Endpoint 4 Interrupt mask Bit
bits : 4 - 4 (1 bit)
access : read-write

INEPMSK5 : IN Endpoint 5 Interrupt mask Bit
bits : 5 - 5 (1 bit)
access : read-write

INEPMSK6 : IN Endpoint 6 Interrupt mask Bit
bits : 6 - 6 (1 bit)
access : read-write

OUTEPMSK0 : OUT Endpoint 0 Interrupt mask Bit
bits : 16 - 16 (1 bit)
access : read-write

OUTEPMSK1 : OUT Endpoint 1 Interrupt mask Bit
bits : 17 - 17 (1 bit)
access : read-write

OUTEPMSK2 : OUT Endpoint 2 Interrupt mask Bit
bits : 18 - 18 (1 bit)
access : read-write

OUTEPMSK3 : OUT Endpoint 3 Interrupt mask Bit
bits : 19 - 19 (1 bit)
access : read-write

OUTEPMSK4 : OUT Endpoint 4 Interrupt mask Bit
bits : 20 - 20 (1 bit)
access : read-write

OUTEPMSK5 : OUT Endpoint 5 Interrupt mask Bit
bits : 21 - 21 (1 bit)
access : read-write

OUTEPMSK6 : OUT Endpoint 6 Interrupt mask Bit
bits : 22 - 22 (1 bit)
access : read-write


DVBUSDIS

Device VBUS Discharge Time Register
address_offset : 0xDE828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVBUSDIS DVBUSDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVBUSDIS

DVBUSDIS : Device VBUS Discharge Time
bits : 0 - 15 (16 bit)
access : read-write


DVBUSPULSE

Device VBUS Pulsing Time Register
address_offset : 0xDE82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVBUSPULSE DVBUSPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVBUSPULSE

DVBUSPULSE : Device VBUS Pulsing Time
bits : 0 - 11 (12 bit)
access : read-write


DTHRCTL

Device Threshold Control Register
address_offset : 0xDE830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTHRCTL DTHRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONISOTHREN ISOTHREN TXTHRLEN AHBTHRRATIO RXTHREN RXTHRLEN ARBPRKEN

NONISOTHREN : Non-ISO IN Endpoints Threshold Enable
bits : 0 - 0 (1 bit)
access : read-write

ISOTHREN : ISO IN Endpoints Threshold Enable
bits : 1 - 1 (1 bit)
access : read-write

TXTHRLEN : Transmit Threshold Length
bits : 2 - 10 (9 bit)
access : read-write

AHBTHRRATIO : AHB Threshold Ratio
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

AHB threshold = MAC threshold.

0x00000001 : DIV2

AHB threshold = MAC threshold / 2.

0x00000002 : DIV4

AHB threshold = MAC threshold / 4.

0x00000003 : DIV8

AHB threshold = MAC threshold / 8.

End of enumeration elements list.

RXTHREN : Receive Threshold Enable
bits : 16 - 16 (1 bit)
access : read-write

RXTHRLEN : Receive Threshold Length
bits : 17 - 25 (9 bit)
access : read-write

ARBPRKEN : Arbiter Parking Enable
bits : 27 - 27 (1 bit)
access : read-write


DIEPEMPMSK

Device IN Endpoint FIFO Empty Interrupt Mask Register
address_offset : 0xDE834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPEMPMSK DIEPEMPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXFEMPMSK

INEPTXFEMPMSK : IN EP Tx FIFO Empty Interrupt Mask Bits
bits : 0 - 15 (16 bit)
access : read-write


DIEP0CTL

Device Control IN Endpoint 0 Control Register
address_offset : 0xDE900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0CTL DIEP0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP NAKSTS EPTYPE STALL TXFNUM CNAK SNAK EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : 64B

64 bytes.

0x00000001 : 32B

32 bytes.

0x00000002 : 16B

16 bytes.

0x00000003 : 8B

8 bytes.

End of enumeration elements list.

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP0INT

Device IN Endpoint 0 Interrupt Register
address_offset : 0xDE908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0INT DIEP0INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP0TSIZ

Device IN Endpoint 0 Transfer Size Register
address_offset : 0xDE910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0TSIZ DIEP0TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT

XFERSIZE : Transfer Size
bits : 0 - 6 (7 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 20 (2 bit)
access : read-write


DIEP0DMAADDR

Device IN Endpoint 0 DMA Address Register
address_offset : 0xDE914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0DMAADDR DIEP0DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP0TXFSTS

Device IN Endpoint Transmit FIFO Status Register 0
address_offset : 0xDE918 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP0TXFSTS DIEP0TXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DIEP0_CTL

Device Control IN Endpoint x+1 Control Register
address_offset : 0xDE920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_CTL DIEP0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP0_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0xDE928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_INT DIEP0_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP0_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0xDE930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_TSIZ DIEP0_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP0_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0xDE934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_DMAADDR DIEP0_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP0_DTXFSTS

Device IN Endpoint Transmit FIFO Status Register 1
address_offset : 0xDE938 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP0_DTXFSTS DIEP0_DTXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DIEP1_CTL

Device Control IN Endpoint x+1 Control Register
address_offset : 0xDE940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_CTL DIEP1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP1_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0xDE948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_INT DIEP1_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP1_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0xDE950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_TSIZ DIEP1_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP1_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0xDE954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_DMAADDR DIEP1_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP1_DTXFSTS

Device IN Endpoint Transmit FIFO Status Register 1
address_offset : 0xDE958 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP1_DTXFSTS DIEP1_DTXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DIEP2_CTL

Device Control IN Endpoint x+1 Control Register
address_offset : 0xDE960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_CTL DIEP2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP2_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0xDE968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_INT DIEP2_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP2_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0xDE970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_TSIZ DIEP2_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP2_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0xDE974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_DMAADDR DIEP2_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP2_DTXFSTS

Device IN Endpoint Transmit FIFO Status Register 1
address_offset : 0xDE978 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP2_DTXFSTS DIEP2_DTXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DIEP3_CTL

Device Control IN Endpoint x+1 Control Register
address_offset : 0xDE980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP3_CTL DIEP3_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP3_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0xDE988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP3_INT DIEP3_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP3_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0xDE990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP3_TSIZ DIEP3_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP3_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0xDE994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP3_DMAADDR DIEP3_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP3_DTXFSTS

Device IN Endpoint Transmit FIFO Status Register 1
address_offset : 0xDE998 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP3_DTXFSTS DIEP3_DTXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DIEP4_CTL

Device Control IN Endpoint x+1 Control Register
address_offset : 0xDE9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP4_CTL DIEP4_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP4_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0xDE9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP4_INT DIEP4_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP4_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0xDE9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP4_TSIZ DIEP4_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP4_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0xDE9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP4_DMAADDR DIEP4_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP4_DTXFSTS

Device IN Endpoint Transmit FIFO Status Register 1
address_offset : 0xDE9B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP4_DTXFSTS DIEP4_DTXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DIEP5_CTL

Device Control IN Endpoint x+1 Control Register
address_offset : 0xDE9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP5_CTL DIEP5_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP5_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0xDE9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP5_INT DIEP5_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INTKNEPMIS INEPNAKEFF TXFEMP TXFIFOUNDRN PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INTKNEPMIS : IN Token Received with EP Mismatch
bits : 5 - 5 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUNDRN : Fifo Underrun
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP5_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0xDE9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP5_TSIZ DIEP5_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP5_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0xDE9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP5_DMAADDR DIEP5_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DIEP5_DTXFSTS

Device IN Endpoint Transmit FIFO Status Register 1
address_offset : 0xDE9D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP5_DTXFSTS DIEP5_DTXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : IN Endpoint TxFIFO Space Avail
bits : 0 - 15 (16 bit)
access : read-only


DOEP0CTL

Device Control OUT Endpoint 0 Control Register
address_offset : 0xDEB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0CTL DOEP0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP NAKSTS EPTYPE SNP STALL CNAK SNAK EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

0x00000000 : 64B

64 bytes.

0x00000001 : 32B

32 bytes.

0x00000002 : 16B

16 bytes.

0x00000003 : 8B

8 bytes.

End of enumeration elements list.

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-only

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP0INT

Device OUT Endpoint 0 Interrupt Register
address_offset : 0xDEB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0INT DOEP0INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP0TSIZ

Device OUT Endpoint 0 Transfer Size Register
address_offset : 0xDEB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0TSIZ DOEP0TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT SUPCNT

XFERSIZE : Transfer Size
bits : 0 - 6 (7 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 19 (1 bit)
access : read-write

SUPCNT : SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-write


DOEP0DMAADDR

Device OUT Endpoint 0 DMA Address Register
address_offset : 0xDEB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0DMAADDR DOEP0DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DOEP0_CTL

Device Control OUT Endpoint x+1 Control Register
address_offset : 0xDEB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_CTL DOEP0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP0_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0xDEB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_INT DOEP0_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP0_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0xDEB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_TSIZ DOEP0_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP0_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0xDEB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_DMAADDR DOEP0_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DOEP1_CTL

Device Control OUT Endpoint x+1 Control Register
address_offset : 0xDEB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_CTL DOEP1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP1_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0xDEB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_INT DOEP1_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP1_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0xDEB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_TSIZ DOEP1_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP1_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0xDEB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_DMAADDR DOEP1_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DOEP2_CTL

Device Control OUT Endpoint x+1 Control Register
address_offset : 0xDEB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_CTL DOEP2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP2_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0xDEB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_INT DOEP2_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP2_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0xDEB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_TSIZ DOEP2_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP2_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0xDEB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_DMAADDR DOEP2_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DOEP3_CTL

Device Control OUT Endpoint x+1 Control Register
address_offset : 0xDEB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP3_CTL DOEP3_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP3_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0xDEB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP3_INT DOEP3_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP3_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0xDEB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP3_TSIZ DOEP3_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP3_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0xDEB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP3_DMAADDR DOEP3_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DOEP4_CTL

Device Control OUT Endpoint x+1 Control Register
address_offset : 0xDEBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP4_CTL DOEP4_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP4_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0xDEBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP4_INT DOEP4_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP4_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0xDEBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP4_TSIZ DOEP4_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP4_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0xDEBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP4_DMAADDR DOEP4_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


DOEP5_CTL

Device Control OUT Endpoint x+1 Control Register
address_offset : 0xDEBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP5_CTL DOEP5_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP5_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0xDEBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP5_INT DOEP5_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP OUTPKTERR PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERR : OUT Packet Error
bits : 8 - 8 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD :
bits : 15 - 15 (1 bit)
access : read-write


DOEP5_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0xDEBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP5_TSIZ DOEP5_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP5_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0xDEBD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP5_DMAADDR DOEP5_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR :
bits : 0 - 31 (32 bit)
access : read-write


PCGCCTL

Power and Clock Gating Control Register
address_offset : 0xDEE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCGCCTL PCGCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPCLK GATEHCLK PWRCLMP RSTPDWNMODULE PHYSLEEP RESETAFTERSUSP

STOPPCLK : Stop PHY clock
bits : 0 - 0 (1 bit)
access : read-write

GATEHCLK : Gate HCLK
bits : 1 - 1 (1 bit)
access : read-write

PWRCLMP : Power Clamp
bits : 2 - 2 (1 bit)
access : read-write

RSTPDWNMODULE : Reset Power-Down Modules
bits : 3 - 3 (1 bit)
access : read-write

PHYSLEEP : PHY In Sleep
bits : 6 - 6 (1 bit)
access : read-only

RESETAFTERSUSP : Reset after suspend
bits : 8 - 8 (1 bit)
access : read-only



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