CR1

SR

EGR

CCMR1_Output

CCMR1_Input

CCER

CNT

PSC

ARR

CCR1

TISEL

DIER

CEN : Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDIS : Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URS : Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPM : One-pulse mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKD : Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UIFREMAP : UIF status bit remapping
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UIF : Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=’0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1IF : Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1OF : Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UG : Update generation This bit can be set by software, it is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

CC1G : Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

CC1S : Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1FE : Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1PE : Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1M1 : Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1M2 : Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1S : Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1PSC : Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1F : Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1E : Capture/Compare 1 output enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1P : Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1NP : Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description).
bits : 3 - 3 (1 bit)
access : read-write

CNT : low counter value
bits : 0 - 15 (16 bit)

UIFCPY : UIF Copy
bits : 31 - 31 (1 bit)

PSC : Prescaler value
bits : 0 - 15 (16 bit)

ARR : Low Auto-reload value
bits : 0 - 15 (16 bit)

CCR1 : Low Capture/Compare 1 value
bits : 0 - 15 (16 bit)

TI1SEL : selects TI1[0] to TI1[15] input Others: Reserved
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.