CR1

SR

EGR

CCMR1_Output

CCMR1_Input

CCER

CNT

PSC

ARR

RCR

CCR1

CR2

BDTR

DCR

DMAR

AF1

TISEL

DIER

CEN : Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDIS : Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URS : Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPM : One pulse mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKD : Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UIFREMAP : UIF status bit remapping
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UIF : Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1IF : Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMIF : COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIF : Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1OF : Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UG : Update generation This bit can be set by software, it is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

CC1G : Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

COMG : Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

BG : Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

CC1S : Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1FE : Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1PE : Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1M1 : Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OC1M2 : Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1S : Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1PSC : Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1F : Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1E : Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1P : Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1NE : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1NP : Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT : counter value
bits : 0 - 15 (16 bit)
access : read-write

UIFCPY : UIF Copy
bits : 31 - 31 (1 bit)
access : read-only

PSC : Prescaler value
bits : 0 - 15 (16 bit)

ARR : Auto-reload value
bits : 0 - 15 (16 bit)

REP : Repetition counter value
bits : 0 - 7 (8 bit)

CCR1 : Capture/Compare 1 value
bits : 0 - 15 (16 bit)

CCPC : Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCUS : Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCDS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS1 : Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OIS1N : Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTG : Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 0 - 7 (8 bit)
access : read-write

LOCK : Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSSI : Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSSR : Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKE : Break enable 1 Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKP : Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOE : Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MOE : Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846).
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKF : Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKDSRM : Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKBID : Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBA : DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBL : DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)

BKINE : BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKINP : BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TI1SEL : selects TI1[0] to TI1[15] input Others: Reserved
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMIE : COM interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIE : Break interrupt enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDE : Update DMA request enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1DE : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.