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WWDG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WWDG_CR (CR)

WWDG_CFR (CFR)

WWDG_SR (SR)


WWDG_CR (CR)

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDG_CR WWDG_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T WDGA

T : 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
bits : 0 - 6 (7 bit)
access : read-write

WDGA : Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Watchdog disabled

0x1 : B_0x1

Watchdog enabled

End of enumeration elements list.


WWDG_CFR (CFR)

Configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDG_CFR WWDG_CFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W EWI WDGTB

W : 7-bit window value These bits contain the window value to be compared with the down-counter.
bits : 0 - 6 (7 bit)
access : read-write

EWI : Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
bits : 9 - 9 (1 bit)
access : read-write

WDGTB : Timer base The timebase of the prescaler can be modified as follows:
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0x0 : B_0x0

CK Counter Clock (PCLK div 4096) div 1

0x1 : B_0x1

CK Counter Clock (PCLK div 4096) div 2

0x2 : B_0x2

CK Counter Clock (PCLK div 4096) div 4

0x3 : B_0x3

CK Counter Clock (PCLK div 4096) div 8

0x4 : B_0x4

CK Counter Clock (PCLK div 4096) div 16

0x5 : B_0x5

CK Counter Clock (PCLK div 4096) div 32

0x6 : B_0x6

CK Counter Clock (PCLK div 4096) div 64

0x7 : B_0x7

CK Counter Clock (PCLK div 4096) div 128

End of enumeration elements list.


WWDG_SR (SR)

Status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDG_SR WWDG_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWIF

EWIF : Early wakeup interrupt flag
bits : 0 - 0 (1 bit)



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