\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDY : ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
ADC is ready to start conversion
End of enumeration elements list.
EOSMP : End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1â.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
End of sampling phase reached
End of enumeration elements list.
EOC : End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Channel conversion complete
End of enumeration elements list.
EOS : End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Conversion sequence complete
End of enumeration elements list.
OVR : ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No overrun occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Overrun has occurred
End of enumeration elements list.
AWD1 : Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog event occurred
End of enumeration elements list.
AWD2 : Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog event occurred
End of enumeration elements list.
AWD3 : Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1 : B_0x1
Analog watchdog event occurred
End of enumeration elements list.
EOCAL : End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Calibration is not complete
0x1 : B_0x1
Calibration is complete
End of enumeration elements list.
CCRDY : Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel configuration update not applied.
0x1 : B_0x1
Channel configuration update is applied.
End of enumeration elements list.
ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVSE : Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Oversampler disabled
0x1 : B_0x1
Oversampler enabled
End of enumeration elements list.
OVSR : Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
2x
0x1 : B_0x1
4x
0x2 : B_0x2
8x
0x3 : B_0x3
16x
0x4 : B_0x4
32x
0x5 : B_0x5
64x
0x6 : B_0x6
128x
0x7 : B_0x7
256x
End of enumeration elements list.
OVSS : Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No shift
0x1 : B_0x1
Shift 1-bit
0x2 : B_0x2
Shift 2-bits
0x3 : B_0x3
Shift 3-bits
0x4 : B_0x4
Shift 4-bits
0x5 : B_0x5
Shift 5-bits
0x6 : B_0x6
Shift 6-bits
0x7 : B_0x7
Shift 7-bits
0x8 : B_0x8
Shift 8-bits
End of enumeration elements list.
TOVS : Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
All oversampled conversions for a channel are done consecutively after a trigger
0x1 : B_0x1
Each oversampled conversion for a channel needs a trigger
End of enumeration elements list.
LFTRIG : Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Low Frequency Trigger Mode disabled
0x1 : B_0x1
Low Frequency Trigger Mode enabled
End of enumeration elements list.
CKMODE : ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
0x1 : B_0x1
PCLK/2 (Synchronous clock mode)
0x2 : B_0x2
PCLK/4 (Synchronous clock mode)
0x3 : B_0x3
PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)
End of enumeration elements list.
ADC sampling time register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP1 : Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
3.5 ADC clock cycles
0x2 : B_0x2
7.5 ADC clock cycles
0x3 : B_0x3
12.5 ADC clock cycles
0x4 : B_0x4
19.5 ADC clock cycles
0x5 : B_0x5
39.5 ADC clock cycles
0x6 : B_0x6
79.5 ADC clock cycles
0x7 : B_0x7
160.5 ADC clock cycles
End of enumeration elements list.
SMP2 : Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1.5 ADC clock cycles
0x1 : B_0x1
3.5 ADC clock cycles
0x2 : B_0x2
7.5 ADC clock cycles
0x3 : B_0x3
12.5 ADC clock cycles
0x4 : B_0x4
19.5 ADC clock cycles
0x5 : B_0x5
39.5 ADC clock cycles
0x6 : B_0x6
79.5 ADC clock cycles
0x7 : B_0x7
160.5 ADC clock cycles
End of enumeration elements list.
SMPSEL0 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL1 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL2 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL3 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL4 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL5 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL6 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL7 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL8 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL9 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL10 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL11 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL12 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL13 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL14 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL15 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL16 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL17 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
SMPSEL18 : Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1 : B_0x1
Sampling time of CHANNELx use the setting of SMP2[2:0] register.
End of enumeration elements list.
ADC watchdog threshold register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT1 : Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
bits : 0 - 11 (12 bit)
access : read-write
HT1 : Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
bits : 16 - 27 (12 bit)
access : read-write
ADC watchdog threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT2 : Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
bits : 0 - 11 (12 bit)
access : read-write
HT2 : Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
bits : 16 - 27 (12 bit)
access : read-write
ADC channel selection register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL0 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL1 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL2 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL3 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL4 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL5 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL6 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL7 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL8 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL9 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL10 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL11 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL12 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL13 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL14 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL15 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL16 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL17 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
CHSEL18 : Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Input Channel-x is not selected for conversion
0x1 : B_0x1
Input Channel-x is selected for conversion
End of enumeration elements list.
ADC channel selection register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : ADC_CHSELRMOD0
reset_Mask : 0x0
SQ1 : 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 0 - 3 (4 bit)
access : read-write
SQ2 : 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 4 - 7 (4 bit)
access : read-write
SQ3 : 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 8 - 11 (4 bit)
access : read-write
SQ4 : 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 12 - 15 (4 bit)
access : read-write
SQ5 : 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 16 - 19 (4 bit)
access : read-write
SQ6 : 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 20 - 23 (4 bit)
access : read-write
SQ7 : 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 24 - 27 (4 bit)
access : read-write
SQ8 : 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CH0
0x1 : B_0x1
CH1
0xC : B_0xC
CH12
0xD : B_0xD
CH13
0xE : B_0xE
CH14
0xF : B_0xF
No channel selected (End of sequence)
End of enumeration elements list.
ADC watchdog threshold register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT3 : Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
bits : 0 - 11 (12 bit)
access : read-write
HT3 : Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
bits : 16 - 27 (12 bit)
access : read-write
ADC common configuration register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
bits : 18 - 21 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
input ADC clock not divided
0x1 : B_0x1
input ADC clock divided by 2
0x2 : B_0x2
input ADC clock divided by 4
0x3 : B_0x3
input ADC clock divided by 6
0x4 : B_0x4
input ADC clock divided by 8
0x5 : B_0x5
input ADC clock divided by 10
0x6 : B_0x6
input ADC clock divided by 12
0x7 : B_0x7
input ADC clock divided by 16
0x8 : B_0x8
input ADC clock divided by 32
0x9 : B_0x9
input ADC clock divided by 64
0xA : B_0xA
input ADC clock divided by 128
0xB : B_0xB
input ADC clock divided by 256
End of enumeration elements list.
VREFEN : VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VREFINT disabled
0x1 : B_0x1
VREFINT enabled
End of enumeration elements list.
TSEN : Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Temperature sensor disabled, DAC_OUT1 connected to ADC channel 12
0x1 : B_0x1
Temperature sensor enabled
End of enumeration elements list.
VBATEN : VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VBAT channel disabled, DAC_OUT2 connected to ADC channel 14
0x1 : B_0x1
VBAT channel enabled
End of enumeration elements list.
ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDYIE : ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADRDY interrupt disabled.
0x1 : B_0x1
ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
End of enumeration elements list.
EOSMPIE : End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOSMP interrupt disabled.
0x1 : B_0x1
EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
End of enumeration elements list.
EOCIE : End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOC interrupt disabled
0x1 : B_0x1
EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
End of enumeration elements list.
EOSIE : End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
EOS interrupt disabled
0x1 : B_0x1
EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
End of enumeration elements list.
OVRIE : Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Overrun interrupt disabled
0x1 : B_0x1
Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
End of enumeration elements list.
AWD1IE : Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt disabled
0x1 : B_0x1
Analog watchdog interrupt enabled
End of enumeration elements list.
AWD2IE : Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt disabled
0x1 : B_0x1
Analog watchdog interrupt enabled
End of enumeration elements list.
AWD3IE : Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog interrupt disabled
0x1 : B_0x1
Analog watchdog interrupt enabled
End of enumeration elements list.
EOCALIE : End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
End of calibration interrupt disabled
0x1 : B_0x1
End of calibration interrupt enabled
End of enumeration elements list.
CCRDYIE : Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Channel configuration ready interrupt disabled
0x1 : B_0x1
Channel configuration ready interrupt enabled
End of enumeration elements list.
ADC data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 389. Just after a calibration is complete, DATA[6:0] contains the calibration factor.
bits : 0 - 15 (16 bit)
access : read-only
ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, ADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC is disabled (OFF state)
0x1 : B_0x1
Write 1 to enable the ADC.
End of enumeration elements list.
ADDIS : ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1â is only effective when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADDIS command ongoing
0x1 : B_0x1
Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
End of enumeration elements list.
ADSTART : ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0), when software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC conversion is ongoing.
0x1 : B_0x1
Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
End of enumeration elements list.
ADSTP : ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1â is only effective when ADSTARTÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No ADC stop conversion command ongoing
0x1 : B_0x1
Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
End of enumeration elements list.
ADVREGEN : ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC voltage regulator disabled
0x1 : B_0x1
ADC voltage regulator enabled
End of enumeration elements list.
ADCAL : ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (ADC enabled and no conversion is ongoing).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Calibration complete
0x1 : B_0x1
Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
End of enumeration elements list.
ADC Analog Watchdog 2 Configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD2CH0 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH1 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH2 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH3 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH4 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH5 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH6 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH7 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH8 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH9 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH10 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH11 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH12 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH13 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH14 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH15 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH16 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH17 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
AWD2CH18 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD2
0x1 : B_0x1
ADC analog channel-x is monitored by AWD2
End of enumeration elements list.
ADC Analog Watchdog 3 Configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD3CH0 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH1 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH2 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH3 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH4 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH5 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH6 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH7 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH8 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH9 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH10 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH11 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH12 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH13 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH14 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH15 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH16 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH17 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
AWD3CH18 : Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog channel-x is not monitored by AWD3
0x1 : B_0x1
ADC analog channel-x is monitored by AWD3
End of enumeration elements list.
ADC Calibration factor
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALFACT : Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.
bits : 0 - 6 (7 bit)
access : read-write
ADC configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA disabled
0x1 : B_0x1
DMA enabled
End of enumeration elements list.
DMACFG : Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 391 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA one shot mode selected
0x1 : B_0x1
DMA circular mode selected
End of enumeration elements list.
SCANDIR : Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Upward scan (from CHSEL0 to CHSEL18)
0x1 : B_0x1
Backward scan (from CHSEL18 to CHSEL0)
End of enumeration elements list.
RES : Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADENÂ =Â 0.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
12 bits
0x1 : B_0x1
10 bits
0x2 : B_0x2
8 bits
0x3 : B_0x3
6 bits
End of enumeration elements list.
ALIGN : Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 389 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Right alignment
0x1 : B_0x1
Left alignment
End of enumeration elements list.
EXTSEL : External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TRG0
0x1 : B_0x1
TRG1
0x2 : B_0x2
TRG2
0x3 : B_0x3
TRG3
0x4 : B_0x4
TRG4
0x5 : B_0x5
TRG5
0x6 : B_0x6
TRG6
0x7 : B_0x7
TRG7
End of enumeration elements list.
EXTEN : External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Hardware trigger detection disabled (conversions can be started by software)
0x1 : B_0x1
Hardware trigger detection on the rising edge
0x2 : B_0x2
Hardware trigger detection on the falling edge
0x3 : B_0x3
Hardware trigger detection on both the rising and falling edges
End of enumeration elements list.
OVRMOD : Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC_DR register is preserved with the old data when an overrun is detected.
0x1 : B_0x1
ADC_DR register is overwritten with the last conversion result when an overrun is detected.
End of enumeration elements list.
CONT : Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Single conversion mode
0x1 : B_0x1
Continuous conversion mode
End of enumeration elements list.
WAIT : Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wait conversion mode off
0x1 : B_0x1
Wait conversion mode on
End of enumeration elements list.
AUTOFF : Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Auto-off mode disabled
0x1 : B_0x1
Auto-off mode enabled
End of enumeration elements list.
DISCEN : Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Discontinuous mode disabled
0x1 : B_0x1
Discontinuous mode enabled
End of enumeration elements list.
CHSELRMOD : Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Each bit of the ADC_CHSELR register enables an input
0x1 : B_0x1
ADC_CHSELR register is able to sequence up to 8 channels
End of enumeration elements list.
AWD1SGL : Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 enabled on all channels
0x1 : B_0x1
Analog watchdog 1 enabled on a single channel
End of enumeration elements list.
AWD1EN : Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Analog watchdog 1 disabled
0x1 : B_0x1
Analog watchdog 1 enabled
End of enumeration elements list.
AWD1CH : Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
bits : 26 - 30 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC analog input Channel 0 monitored by AWD
0x1 : B_0x1
ADC analog input Channel 1 monitored by AWD
0x11 : B_0x11
ADC analog input Channel 17 monitored by AWD
0x12 : B_0x12
ADC analog input Channel 18 monitored by AWD
End of enumeration elements list.
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