Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected
DMAMUX request line multiplexer channel x configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX request line multiplexer channel x configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX request generator channel x configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
bits : 0 - 4 (5 bit)
access : read-write
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event occurrence is enabled
End of enumeration elements list.
GE : DMA request generator channel x enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x disabled
0x1 : B_0x1
DMA request generator channel x enabled
End of enumeration elements list.
GPOL : DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
GNBREQ : Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX request generator channel x configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
bits : 0 - 4 (5 bit)
access : read-write
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event occurrence is enabled
End of enumeration elements list.
GE : DMA request generator channel x enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x disabled
0x1 : B_0x1
DMA request generator channel x enabled
End of enumeration elements list.
GPOL : DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
GNBREQ : Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX request generator channel x configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
bits : 0 - 4 (5 bit)
access : read-write
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event occurrence is enabled
End of enumeration elements list.
GE : DMA request generator channel x enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x disabled
0x1 : B_0x1
DMA request generator channel x enabled
End of enumeration elements list.
GPOL : DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
GNBREQ : Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX request generator channel x configuration register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
bits : 0 - 4 (5 bit)
access : read-write
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event occurrence is enabled
End of enumeration elements list.
GE : DMA request generator channel x enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x disabled
0x1 : B_0x1
DMA request generator channel x enabled
End of enumeration elements list.
GPOL : DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
GNBREQ : Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX request line multiplexer channel x configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX request generator interrupt status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OF0 : Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
bits : 0 - 0 (1 bit)
access : read-only
OF1 : Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
bits : 1 - 1 (1 bit)
access : read-only
OF2 : Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
bits : 2 - 2 (1 bit)
access : read-only
OF3 : Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
bits : 3 - 3 (1 bit)
access : read-only
DMAMUX request generator interrupt clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COF0 : Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
bits : 0 - 0 (1 bit)
access : write-only
COF1 : Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
bits : 1 - 1 (1 bit)
access : write-only
COF2 : Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
bits : 2 - 2 (1 bit)
access : write-only
COF3 : Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
bits : 3 - 3 (1 bit)
access : write-only
DMAMUX request line multiplexer channel x configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX request line multiplexer channel x configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX request line multiplexer channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF0 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 0 - 0 (1 bit)
access : read-only
SOF1 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 1 - 1 (1 bit)
access : read-only
SOF2 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 2 - 2 (1 bit)
access : read-only
SOF3 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 3 - 3 (1 bit)
access : read-only
SOF4 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 4 - 4 (1 bit)
access : read-only
SOF5 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 5 - 5 (1 bit)
access : read-only
SOF6 : Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
bits : 6 - 6 (1 bit)
access : read-only
DMAMUX request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CSOF0 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 0 - 0 (1 bit)
access : write-only
CSOF1 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 1 - 1 (1 bit)
access : write-only
CSOF2 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 2 - 2 (1 bit)
access : write-only
CSOF3 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 3 - 3 (1 bit)
access : write-only
CSOF4 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 4 - 4 (1 bit)
access : write-only
CSOF5 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 5 - 5 (1 bit)
access : write-only
CSOF6 : Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
bits : 6 - 6 (1 bit)
access : write-only
DMAMUX request line multiplexer channel x configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
bits : 0 - 5 (6 bit)
access : read-write
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : Event generation enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation disabled
0x1 : B_0x1
event generation enabled
End of enumeration elements list.
SE : Synchronization enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization disabled
0x1 : B_0x1
synchronization enabled
End of enumeration elements list.
SPOL : Synchronization polarity Defines the edge polarity of the selected synchronization input:
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event, i.e. no synchronization nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling edge
End of enumeration elements list.
NBREQ : Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
bits : 24 - 28 (5 bit)
access : read-write
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