\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Key register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Key value (write only, read 0x0000)
bits : 0 - 15 (16 bit)
Window register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIN : Watchdog counter window value
bits : 0 - 11 (12 bit)
Prescaler register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
divider /4
0x1 : B_0x1
divider /8
0x2 : B_0x2
divider /16
0x3 : B_0x3
divider /32
0x4 : B_0x4
divider /64
0x5 : B_0x5
divider /128
0x6 : B_0x6
divider /256
0x7 : B_0x7
divider /256
End of enumeration elements list.
Reload register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RL : Watchdog counter reload value
bits : 0 - 11 (12 bit)
Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PVU : Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
bits : 0 - 0 (1 bit)
access : read-only
RVU : Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
bits : 1 - 1 (1 bit)
access : read-only
WVU : Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
bits : 2 - 2 (1 bit)
access : read-only
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