LPTIM_ISR

LPTIM_CR

LPTIM_CMP

LPTIM_ARR

LPTIM_CNT

LPTIM_CFGR2

LPTIM_ICR

LPTIM_IER

LPTIM_CFGR

CMPM : Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value.
bits : 0 - 0 (1 bit)
access : read-only

ARRM : Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
bits : 1 - 1 (1 bit)
access : read-only

EXTTRIG : External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
bits : 2 - 2 (1 bit)
access : read-only

CMPOK : Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed.
bits : 3 - 3 (1 bit)
access : read-only

ARROK : Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
bits : 4 - 4 (1 bit)
access : read-only

UP : Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 5 - 5 (1 bit)
access : read-only

DOWN : Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 6 - 6 (1 bit)
access : read-only

ENABLE : LPTIM enable The ENABLE bit is set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SNGSTRT : LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
bits : 1 - 1 (1 bit)
access : read-write

CNTSTRT : Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
bits : 2 - 2 (1 bit)
access : read-write

COUNTRST : Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
bits : 3 - 3 (1 bit)
access : read-write

RSTARE : Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
bits : 4 - 4 (1 bit)
access : read-write

CMP : Compare value
bits : 0 - 15 (16 bit)

ARR : Auto reload value
bits : 0 - 15 (16 bit)

CNT : Counter value
bits : 0 - 15 (16 bit)

IN1SEL : LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to .
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IN2SEL : LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to .
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMCF : Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register
bits : 0 - 0 (1 bit)
access : write-only

ARRMCF : Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
bits : 1 - 1 (1 bit)
access : write-only

EXTTRIGCF : External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
bits : 2 - 2 (1 bit)
access : write-only

CMPOKCF : Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
bits : 3 - 3 (1 bit)
access : write-only

ARROKCF : Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
bits : 4 - 4 (1 bit)
access : write-only

UPCF : Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 5 - 5 (1 bit)
access : write-only

DOWNCF : Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 6 - 6 (1 bit)
access : write-only

CMPMIE : Compare match Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ARRMIE : Autoreload match Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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EXTTRIGIE : External trigger valid edge Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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CMPOKIE : Compare register update OK Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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ARROKIE : Autoreload register update OK Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

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UPIE : Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOWNIE : Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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CKSEL : Clock selector The CKSEL bit selects which clock source the LPTIM will use:
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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CKPOL : Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKFLT : Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

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TRGFLT : Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

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PRESC : Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

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TRIGSEL : Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGEN : Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

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TIMOUT : Timeout enable The TIMOUT bit controls the Timeout feature
bits : 19 - 19 (1 bit)
access : read-write

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WAVE : Waveform shape The WAVE bit controls the output shape
bits : 20 - 20 (1 bit)
access : read-write

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WAVPOL : Waveform shape polarity The WAVEPOL bit controls the output polarity
bits : 21 - 21 (1 bit)
access : read-write

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PRELOAD : Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

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COUNTMODE : counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

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ENC : Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.