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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR

SMPR1

SMPR2

TR1

TR2

TR3

SQR1

SQR2

SQR3

SQR4

IER

DR

JSQR

OFR1

OFR2

OFR3

OFR4

CR

JDR1

JDR2

JDR3

JDR4

AWD2CR

AWD3CR

DIFSEL

CALFACT

CFGR


ISR

interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDY EOSMP EOC EOS OVR JEOC JEOS AWD1 AWD2 AWD3 JQOVF

ADRDY : ADRDY
bits : 0 - 0 (1 bit)

EOSMP : EOSMP
bits : 1 - 1 (1 bit)

EOC : EOC
bits : 2 - 2 (1 bit)

EOS : EOS
bits : 3 - 3 (1 bit)

OVR : OVR
bits : 4 - 4 (1 bit)

JEOC : JEOC
bits : 5 - 5 (1 bit)

JEOS : JEOS
bits : 6 - 6 (1 bit)

AWD1 : AWD1
bits : 7 - 7 (1 bit)

AWD2 : AWD2
bits : 8 - 8 (1 bit)

AWD3 : AWD3
bits : 9 - 9 (1 bit)

JQOVF : JQOVF
bits : 10 - 10 (1 bit)


SMPR1

sample time register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR1 SMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP1 SMP2 SMP3 SMP4 SMP5 SMP6 SMP7 SMP8 SMP9

SMP1 : SMP1
bits : 3 - 5 (3 bit)

SMP2 : SMP2
bits : 6 - 8 (3 bit)

SMP3 : SMP3
bits : 9 - 11 (3 bit)

SMP4 : SMP4
bits : 12 - 14 (3 bit)

SMP5 : SMP5
bits : 15 - 17 (3 bit)

SMP6 : SMP6
bits : 18 - 20 (3 bit)

SMP7 : SMP7
bits : 21 - 23 (3 bit)

SMP8 : SMP8
bits : 24 - 26 (3 bit)

SMP9 : SMP9
bits : 27 - 29 (3 bit)


SMPR2

sample time register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR2 SMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP10 SMP11 SMP12 SMP13 SMP14 SMP15 SMP16 SMP17 SMP18

SMP10 : SMP10
bits : 0 - 2 (3 bit)

SMP11 : SMP11
bits : 3 - 5 (3 bit)

SMP12 : SMP12
bits : 6 - 8 (3 bit)

SMP13 : SMP13
bits : 9 - 11 (3 bit)

SMP14 : SMP14
bits : 12 - 14 (3 bit)

SMP15 : SMP15
bits : 15 - 17 (3 bit)

SMP16 : SMP16
bits : 18 - 20 (3 bit)

SMP17 : SMP17
bits : 21 - 23 (3 bit)

SMP18 : SMP18
bits : 24 - 26 (3 bit)


TR1

watchdog threshold register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TR1 TR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT1 HT1

LT1 : LT1
bits : 0 - 11 (12 bit)

HT1 : HT1
bits : 16 - 27 (12 bit)


TR2

watchdog threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TR2 TR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT2 HT2

LT2 : LT2
bits : 0 - 7 (8 bit)

HT2 : HT2
bits : 16 - 23 (8 bit)


TR3

watchdog threshold register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TR3 TR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT3 HT3

LT3 : LT3
bits : 0 - 7 (8 bit)

HT3 : HT3
bits : 16 - 23 (8 bit)


SQR1

regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR1 SQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L3 SQ1 SQ2 SQ3 SQ4

L3 : L3
bits : 0 - 3 (4 bit)

SQ1 : SQ1
bits : 6 - 10 (5 bit)

SQ2 : SQ2
bits : 12 - 16 (5 bit)

SQ3 : SQ3
bits : 18 - 22 (5 bit)

SQ4 : SQ4
bits : 24 - 28 (5 bit)


SQR2

regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR2 SQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ5 SQ6 SQ7 SQ8 SQ9

SQ5 : SQ5
bits : 0 - 4 (5 bit)

SQ6 : SQ6
bits : 6 - 10 (5 bit)

SQ7 : SQ7
bits : 12 - 16 (5 bit)

SQ8 : SQ8
bits : 18 - 22 (5 bit)

SQ9 : SQ9
bits : 24 - 28 (5 bit)


SQR3

regular sequence register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR3 SQR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ10 SQ11 SQ12 SQ13 SQ14

SQ10 : SQ10
bits : 0 - 4 (5 bit)

SQ11 : SQ11
bits : 6 - 10 (5 bit)

SQ12 : SQ12
bits : 12 - 16 (5 bit)

SQ13 : SQ13
bits : 18 - 22 (5 bit)

SQ14 : SQ14
bits : 24 - 28 (5 bit)


SQR4

regular sequence register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR4 SQR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ15 SQ16

SQ15 : SQ15
bits : 0 - 4 (5 bit)

SQ16 : SQ16
bits : 6 - 10 (5 bit)


IER

interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDYIE EOSMPIE EOCIE EOSIE OVRIE JEOCIE JEOSIE AWD1IE AWD2IE AWD3IE JQOVFIE

ADRDYIE : ADRDYIE
bits : 0 - 0 (1 bit)

EOSMPIE : EOSMPIE
bits : 1 - 1 (1 bit)

EOCIE : EOCIE
bits : 2 - 2 (1 bit)

EOSIE : EOSIE
bits : 3 - 3 (1 bit)

OVRIE : OVRIE
bits : 4 - 4 (1 bit)

JEOCIE : JEOCIE
bits : 5 - 5 (1 bit)

JEOSIE : JEOSIE
bits : 6 - 6 (1 bit)

AWD1IE : AWD1IE
bits : 7 - 7 (1 bit)

AWD2IE : AWD2IE
bits : 8 - 8 (1 bit)

AWD3IE : AWD3IE
bits : 9 - 9 (1 bit)

JQOVFIE : JQOVFIE
bits : 10 - 10 (1 bit)


DR

regular Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 regularDATA

regularDATA : regularDATA
bits : 0 - 15 (16 bit)


JSQR

injected sequence register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JSQR JSQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JL JEXTSEL JEXTEN JSQ1 JSQ2 JSQ3 JSQ4

JL : JL
bits : 0 - 1 (2 bit)

JEXTSEL : JEXTSEL
bits : 2 - 5 (4 bit)

JEXTEN : JEXTEN
bits : 6 - 7 (2 bit)

JSQ1 : JSQ1
bits : 8 - 12 (5 bit)

JSQ2 : JSQ2
bits : 14 - 18 (5 bit)

JSQ3 : JSQ3
bits : 20 - 24 (5 bit)

JSQ4 : JSQ4
bits : 26 - 30 (5 bit)


OFR1

offset register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR1 OFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 OFFSET1_CH OFFSET1_EN

OFFSET1 : OFFSET1
bits : 0 - 11 (12 bit)

OFFSET1_CH : OFFSET1_CH
bits : 26 - 30 (5 bit)

OFFSET1_EN : OFFSET1_EN
bits : 31 - 31 (1 bit)


OFR2

offset register 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR2 OFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET2 OFFSET2_CH OFFSET2_EN

OFFSET2 : OFFSET2
bits : 0 - 11 (12 bit)

OFFSET2_CH : OFFSET2_CH
bits : 26 - 30 (5 bit)

OFFSET2_EN : OFFSET2_EN
bits : 31 - 31 (1 bit)


OFR3

offset register 3
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR3 OFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET3 OFFSET3_CH OFFSET3_EN

OFFSET3 : OFFSET3
bits : 0 - 11 (12 bit)

OFFSET3_CH : OFFSET3_CH
bits : 26 - 30 (5 bit)

OFFSET3_EN : OFFSET3_EN
bits : 31 - 31 (1 bit)


OFR4

offset register 4
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFR4 OFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET4 OFFSET4_CH OFFSET4_EN

OFFSET4 : OFFSET4
bits : 0 - 11 (12 bit)

OFFSET4_CH : OFFSET4_CH
bits : 26 - 30 (5 bit)

OFFSET4_EN : OFFSET4_EN
bits : 31 - 31 (1 bit)


CR

control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN ADDIS ADSTART JADSTART ADSTP JADSTP ADVREGEN DEEPPWD ADCALDIF ADCAL

ADEN : ADEN
bits : 0 - 0 (1 bit)

ADDIS : ADDIS
bits : 1 - 1 (1 bit)

ADSTART : ADSTART
bits : 2 - 2 (1 bit)

JADSTART : JADSTART
bits : 3 - 3 (1 bit)

ADSTP : ADSTP
bits : 4 - 4 (1 bit)

JADSTP : JADSTP
bits : 5 - 5 (1 bit)

ADVREGEN : ADVREGEN
bits : 28 - 28 (1 bit)

DEEPPWD : DEEPPWD
bits : 29 - 29 (1 bit)

ADCALDIF : ADCALDIF
bits : 30 - 30 (1 bit)

ADCAL : ADCAL
bits : 31 - 31 (1 bit)


JDR1

injected data register 1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR1 JDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA1

JDATA1 : JDATA1
bits : 0 - 15 (16 bit)


JDR2

injected data register 2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR2 JDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA2

JDATA2 : JDATA2
bits : 0 - 15 (16 bit)


JDR3

injected data register 3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR3 JDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA3

JDATA3 : JDATA3
bits : 0 - 15 (16 bit)


JDR4

injected data register 4
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR4 JDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA4

JDATA4 : JDATA4
bits : 0 - 15 (16 bit)


AWD2CR

Analog Watchdog 2 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD2CR AWD2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD2CH

AWD2CH : AWD2CH
bits : 1 - 18 (18 bit)


AWD3CR

Analog Watchdog 3 Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD3CR AWD3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD3CH

AWD3CH : AWD3CH
bits : 1 - 18 (18 bit)


DIFSEL

Differential Mode Selection Register 2
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIFSEL DIFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIFSEL_1_15 DIFSEL_16_18

DIFSEL_1_15 : Differential mode for channels 15 to 1
bits : 1 - 15 (15 bit)
access : read-write

DIFSEL_16_18 : Differential mode for channels 18 to 16
bits : 16 - 18 (3 bit)
access : read-only


CALFACT

Calibration Factors
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALFACT CALFACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALFACT_S CALFACT_D

CALFACT_S : CALFACT_S
bits : 0 - 6 (7 bit)

CALFACT_D : CALFACT_D
bits : 16 - 22 (7 bit)


CFGR

configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMACFG RES ALIGN EXTSEL EXTEN OVRMOD CONT AUTDLY AUTOFF DISCEN DISCNUM JDISCEN JQM AWD1SGL AWD1EN JAWD1EN JAUTO AWDCH1CH

DMAEN : DMAEN
bits : 0 - 0 (1 bit)

DMACFG : DMACFG
bits : 1 - 1 (1 bit)

RES : RES
bits : 3 - 4 (2 bit)

ALIGN : ALIGN
bits : 5 - 5 (1 bit)

EXTSEL : EXTSEL
bits : 6 - 9 (4 bit)

EXTEN : EXTEN
bits : 10 - 11 (2 bit)

OVRMOD : OVRMOD
bits : 12 - 12 (1 bit)

CONT : CONT
bits : 13 - 13 (1 bit)

AUTDLY : AUTDLY
bits : 14 - 14 (1 bit)

AUTOFF : AUTOFF
bits : 15 - 15 (1 bit)

DISCEN : DISCEN
bits : 16 - 16 (1 bit)

DISCNUM : DISCNUM
bits : 17 - 19 (3 bit)

JDISCEN : JDISCEN
bits : 20 - 20 (1 bit)

JQM : JQM
bits : 21 - 21 (1 bit)

AWD1SGL : AWD1SGL
bits : 22 - 22 (1 bit)

AWD1EN : AWD1EN
bits : 23 - 23 (1 bit)

JAWD1EN : JAWD1EN
bits : 24 - 24 (1 bit)

JAUTO : JAUTO
bits : 25 - 25 (1 bit)

AWDCH1CH : AWDCH1CH
bits : 26 - 30 (5 bit)



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