\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
DAC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel1 disabled
0x1 : B_0x1
DAC channel1 enabled
End of enumeration elements list.
TEN1 : DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register
0x1 : B_0x1
DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register
End of enumeration elements list.
TSEL1 : DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SWTRIG1
0x1 : B_0x1
dac_ch1_trg1
0x2 : B_0x2
dac_ch1_trg2
0xF : B_0xF
dac_ch1_trg15
End of enumeration elements list.
WAVE1 : DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
wave generation disabled
0x1 : B_0x1
Noise wave generation enabled
End of enumeration elements list.
MAMP1 : DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1 : B_0x1
Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2 : B_0x2
Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3 : B_0x3
Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4 : B_0x4
Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5 : B_0x5
Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6 : B_0x6
Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7 : B_0x7
Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8 : B_0x8
Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9 : B_0x9
Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA : B_0xA
Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
End of enumeration elements list.
DMAEN1 : DAC channel1 DMA enable This bit is set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel1 DMA mode disabled
0x1 : B_0x1
DAC channel1 DMA mode enabled
End of enumeration elements list.
DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel1 DMA Underrun Interrupt disabled
0x1 : B_0x1
DAC channel1 DMA Underrun Interrupt enabled
End of enumeration elements list.
CEN1 : DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel1 in Normal operating mode
0x1 : B_0x1
DAC channel1 in calibration mode
End of enumeration elements list.
EN2 : DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel2 disabled
0x1 : B_0x1
DAC channel2 enabled
End of enumeration elements list.
TEN2 : DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_pclk clock cycle later to the DAC_DOR2 register
0x1 : B_0x1
DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_pclk clock cycles later to the DAC_DOR2 register
End of enumeration elements list.
TSEL2 : DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation.
bits : 18 - 21 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SWTRIG2
0x1 : B_0x1
dac_ch2_trg1
0x2 : B_0x2
dac_ch2_trg2
0xF : B_0xF
dac_ch2_trg15
End of enumeration elements list.
WAVE2 : DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
wave generation disabled
0x1 : B_0x1
Noise wave generation enabled
End of enumeration elements list.
MAMP2 : DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1 : B_0x1
Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2 : B_0x2
Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3 : B_0x3
Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4 : B_0x4
Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5 : B_0x5
Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6 : B_0x6
Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7 : B_0x7
Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8 : B_0x8
Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9 : B_0x9
Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA : B_0xA
Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
End of enumeration elements list.
DMAEN2 : DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel2 DMA mode disabled
0x1 : B_0x1
DAC channel2 DMA mode enabled
End of enumeration elements list.
DMAUDRIE2 : DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel2 DMA underrun interrupt disabled
0x1 : B_0x1
DAC channel2 DMA underrun interrupt enabled
End of enumeration elements list.
CEN2 : DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel2 in Normal operating mode
0x1 : B_0x1
DAC channel2 in calibration mode
End of enumeration elements list.
DAC channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1.
bits : 0 - 7 (8 bit)
access : read-write
DAC channel2 12-bit right aligned data holding register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2.
bits : 0 - 11 (12 bit)
access : read-write
DAC channel2 12-bit left aligned data holding register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.
bits : 4 - 15 (12 bit)
access : read-write
DAC channel2 8-bit right-aligned data holding register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
bits : 0 - 7 (8 bit)
access : read-write
Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
bits : 0 - 11 (12 bit)
access : read-write
DACC2DHR : DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
bits : 16 - 27 (12 bit)
access : read-write
DUAL DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
bits : 4 - 15 (12 bit)
access : read-write
DACC2DHR : DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
bits : 20 - 31 (12 bit)
access : read-write
DUAL DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
bits : 0 - 7 (8 bit)
access : read-write
DACC2DHR : DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
bits : 8 - 15 (8 bit)
access : read-write
DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC1DOR : DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
bits : 0 - 11 (12 bit)
access : read-only
DAC channel2 data output register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC2DOR : DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.
bits : 0 - 11 (12 bit)
access : read-only
DAC status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAUDR1 : DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No DMA underrun error condition occurred for DAC channel1
0x1 : B_0x1
DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
End of enumeration elements list.
CAL_FLAG1 : DAC channel1 calibration offset status This bit is set and cleared by hardware
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
calibration trimming value is lower than the offset correction value
0x1 : B_0x1
calibration trimming value is equal or greater than the offset correction value
End of enumeration elements list.
BWST1 : DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0x1 : B_0x1
There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
End of enumeration elements list.
DMAUDR2 : DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No DMA underrun error condition occurred for DAC channel2
0x1 : B_0x1
DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).
End of enumeration elements list.
CAL_FLAG2 : DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
calibration trimming value is lower than the offset correction value
0x1 : B_0x1
calibration trimming value is equal or greater than the offset correction value
End of enumeration elements list.
BWST2 : DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
0x1 : B_0x1
There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written
End of enumeration elements list.
DAC calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTRIM1 : DAC channel1 offset trimming value
bits : 0 - 4 (5 bit)
access : read-write
OTRIM2 : DAC channel2 offset trimming value These bits are available only on dual-channel DACs. Refer to implementation.
bits : 16 - 20 (5 bit)
access : read-write
DAC mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE1 : DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample and hold mode Note: This register can be modified only when EN1=0.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel1 is connected to external pin with Buffer enabled
0x1 : B_0x1
DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x2 : B_0x2
DAC channel1 is connected to external pin with Buffer disabled
0x3 : B_0x3
DAC channel1 is connected to on chip peripherals with Buffer disabled
0x4 : B_0x4
DAC channel1 is connected to external pin with Buffer enabled
0x5 : B_0x5
DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x6 : B_0x6
DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled
0x7 : B_0x7
DAC channel1 is connected to on chip peripherals with Buffer disabled
End of enumeration elements list.
MODE2 : DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2=0. Refer to for the availability of DAC channel2.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC channel2 is connected to external pin with Buffer enabled
0x1 : B_0x1
DAC channel2 is connected to external pin and to on chip peripherals with buffer enabled
0x2 : B_0x2
DAC channel2 is connected to external pin with buffer disabled
0x3 : B_0x3
DAC channel2 is connected to on chip peripherals with Buffer disabled
0x4 : B_0x4
DAC channel2 is connected to external pin with Buffer enabled
0x5 : B_0x5
DAC channel2 is connected to external pin and to on chip peripherals with Buffer enabled
0x6 : B_0x6
DAC channel2 is connected to external pin and to on chip peripherals with Buffer disabled
0x7 : B_0x7
DAC channel2 is connected to on chip peripherals with Buffer disabled
End of enumeration elements list.
DAC software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRIG1 : DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No trigger
0x1 : B_0x1
Trigger
End of enumeration elements list.
SWTRIG2 : DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No trigger
0x1 : B_0x1
Trigger
End of enumeration elements list.
DAC Sample and Hold sample time register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE1 : DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored.
bits : 0 - 9 (10 bit)
access : read-write
DAC Sample and Hold sample time register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE2 : DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored.
bits : 0 - 9 (10 bit)
access : read-write
DAC Sample and Hold hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THOLD1 : DAC channel1 hold time (only valid in Sample and hold mode) Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN1=0.
bits : 0 - 9 (10 bit)
access : read-write
THOLD2 : DAC channel2 hold time (only valid in Sample and hold mode). Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.
bits : 16 - 25 (10 bit)
access : read-write
DAC Sample and Hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TREFRESH1 : DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN1=0.
bits : 0 - 7 (8 bit)
access : read-write
TREFRESH2 : DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.
bits : 16 - 23 (8 bit)
access : read-write
DAC channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1.
bits : 0 - 11 (12 bit)
access : read-write
DAC channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1.
bits : 4 - 15 (12 bit)
access : read-write
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