\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UE : USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART prescaler and outputs disabled, low-power mode
0x1 : B_0x1
USART enabled
End of enumeration elements list.
UESM : USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART not able to wake up the MCU from low-power mode.
0x1 : B_0x1
USART able to wake up the MCU from low-power mode.
End of enumeration elements list.
RE : Receiver enable This bit enables the receiver. It is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receiver is disabled
0x1 : B_0x1
Receiver is enabled and begins searching for a start bit
End of enumeration elements list.
TE : Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Transmitter is disabled
0x1 : B_0x1
Transmitter is enabled
End of enumeration elements list.
IDLEIE : IDLE interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever IDLE = 1 in the USART_ISR register
End of enumeration elements list.
RXFNEIE : RXFIFO not empty interrupt enable This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register
End of enumeration elements list.
TCIE : Transmission complete interrupt enable This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever TC = 1 in the USART_ISR register
End of enumeration elements list.
TXFNFIE : TXFIFO not full interrupt enable This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever TXFNF =1 in the USART_ISR register
End of enumeration elements list.
PEIE : PE interrupt enable This bit is set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever PE = 1 in the USART_ISR register
End of enumeration elements list.
PS : Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Even parity
0x1 : B_0x1
Odd parity
End of enumeration elements list.
PCE : Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Parity control disabled
0x1 : B_0x1
Parity control enabled
End of enumeration elements list.
WAKE : Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Idle line
0x1 : B_0x1
Address mark
End of enumeration elements list.
M0 : Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
bits : 12 - 12 (1 bit)
access : read-write
MME : Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receiver in active mode permanently
0x1 : B_0x1
Receiver can switch between Mute mode and active mode.
End of enumeration elements list.
CMIE : Character match interrupt enable This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when the CMF bit is set in the USART_ISR register.
End of enumeration elements list.
OVER8 : Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Oversampling by 16
0x1 : B_0x1
Oversampling by 8
End of enumeration elements list.
DEDT : Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 16 - 20 (5 bit)
access : read-write
DEAT : Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 21 - 25 (5 bit)
access : read-write
RTOIE : Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when the RTOF bit is set in the USART_ISR register.
End of enumeration elements list.
EOBIE : End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when the EOBF flag is set in the USART_ISR register
End of enumeration elements list.
M1 : Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
bits : 28 - 28 (1 bit)
access : read-write
FIFOEN : FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FIFO mode is disabled.
0x1 : B_0x1
FIFO mode is enabled.
End of enumeration elements list.
TXFEIE : TXFIFO empty interrupt enable This bit is set and cleared by software.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when TXFE = 1 in the USART_ISR register
End of enumeration elements list.
RXFFIE : RXFIFO Full interrupt enable This bit is set and cleared by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when RXFF = 1 in the USART_ISR register
End of enumeration elements list.
Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CR1_FIFO_ENABLED
reset_Mask : 0x0
UE : USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART prescaler and outputs disabled, low-power mode
0x1 : B_0x1
USART enabled
End of enumeration elements list.
UESM : USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART not able to wake up the MCU from low-power mode.
0x1 : B_0x1
USART able to wake up the MCU from low-power mode.
End of enumeration elements list.
RE : Receiver enable This bit enables the receiver. It is set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receiver is disabled
0x1 : B_0x1
Receiver is enabled and begins searching for a start bit
End of enumeration elements list.
TE : Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Transmitter is disabled
0x1 : B_0x1
Transmitter is enabled
End of enumeration elements list.
IDLEIE : IDLE interrupt enable This bit is set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever IDLE = 1 in the USART_ISR register
End of enumeration elements list.
RXNEIE : Receive data register not empty This bit is set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register
End of enumeration elements list.
TCIE : Transmission complete interrupt enable This bit is set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever TC = 1 in the USART_ISR register
End of enumeration elements list.
TXEIE : Transmit data register empty This bit is set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever TXE =1 in the USART_ISR register
End of enumeration elements list.
PEIE : PE interrupt enable This bit is set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever PE = 1 in the USART_ISR register
End of enumeration elements list.
PS : Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Even parity
0x1 : B_0x1
Odd parity
End of enumeration elements list.
PCE : Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Parity control disabled
0x1 : B_0x1
Parity control enabled
End of enumeration elements list.
WAKE : Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Idle line
0x1 : B_0x1
Address mark
End of enumeration elements list.
M0 : Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
bits : 12 - 12 (1 bit)
access : read-write
MME : Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receiver in active mode permanently
0x1 : B_0x1
Receiver can switch between Mute mode and active mode.
End of enumeration elements list.
CMIE : Character match interrupt enable This bit is set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when the CMF bit is set in the USART_ISR register.
End of enumeration elements list.
OVER8 : Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Oversampling by 16
0x1 : B_0x1
Oversampling by 8
End of enumeration elements list.
DEDT : Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 16 - 20 (5 bit)
access : read-write
DEAT : Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 21 - 25 (5 bit)
access : read-write
RTOIE : Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when the RTOF bit is set in the USART_ISR register.
End of enumeration elements list.
EOBIE : End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when the EOBF flag is set in the USART_ISR register
End of enumeration elements list.
M1 : Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
bits : 28 - 28 (1 bit)
access : read-write
FIFOEN : FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FIFO mode is disabled.
0x1 : B_0x1
FIFO mode is enabled.
End of enumeration elements list.
Guard time and prescaler register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to .
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Reserved - do not program this value
0x1 : B_0x1
Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2 : B_0x2
Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3 : B_0x3
Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F : B_0x1F
Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
End of enumeration elements list.
GT : Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 8 - 15 (8 bit)
access : read-write
Receiver timeout register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTO : Receiver timeout value
bits : 0 - 23 (24 bit)
BLEN : Block Length
bits : 24 - 31 (8 bit)
Request register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ABRRQ : Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
bits : 0 - 0 (1 bit)
access : write-only
SBKRQ : Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
bits : 1 - 1 (1 bit)
access : write-only
MMRQ : Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
bits : 2 - 2 (1 bit)
access : write-only
RXFRQ : Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
bits : 3 - 3 (1 bit)
access : write-only
TXFRQ : Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
bits : 4 - 4 (1 bit)
access : write-only
Interrupt and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PE : Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No parity error
0x1 : B_0x1
Parity error
End of enumeration elements list.
FE : Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Framing error is detected
0x1 : B_0x1
Framing error or break character is detected
End of enumeration elements list.
NE : Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No noise is detected
0x1 : B_0x1
Noise is detected
End of enumeration elements list.
ORE : Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No overrun error
0x1 : B_0x1
Overrun error is detected
End of enumeration elements list.
IDLE : Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Idle line is detected
0x1 : B_0x1
Idle line is detected
End of enumeration elements list.
RXFNE : RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Data is not received
0x1 : B_0x1
Received data is ready to be read.
End of enumeration elements list.
TC : Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Transmission is not complete
0x1 : B_0x1
Transmission is complete
End of enumeration elements list.
TXFNF : TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Transmit FIFO is full
0x1 : B_0x1
Transmit FIFO is not full
End of enumeration elements list.
LBDF : LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LIN Break not detected
0x1 : B_0x1
LIN break detected
End of enumeration elements list.
CTSIF : CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No change occurred on the nCTS status line
0x1 : B_0x1
A change occurred on the nCTS status line
End of enumeration elements list.
CTS : CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
nCTS line set
0x1 : B_0x1
nCTS line reset
End of enumeration elements list.
RTOF : Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Timeout value not reached
0x1 : B_0x1
Timeout value reached without any data reception
End of enumeration elements list.
EOBF : End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
End of Block not reached
0x1 : B_0x1
End of Block (number of characters) reached
End of enumeration elements list.
UDR : SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No underrun error
0x1 : B_0x1
underrun error
End of enumeration elements list.
ABRE : Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
bits : 14 - 14 (1 bit)
access : read-only
ABRF : Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
bits : 15 - 15 (1 bit)
access : read-only
BUSY : Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
USART is idle (no reception)
0x1 : B_0x1
Reception on going
End of enumeration elements list.
CMF : Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Character match detected
0x1 : B_0x1
Character Match detected
End of enumeration elements list.
SBKF : Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Break character transmitted
0x1 : B_0x1
Break character requested by setting SBKRQ bit in USART_RQR register
End of enumeration elements list.
RWU : Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Receiver in active mode
0x1 : B_0x1
Receiver in Mute mode
End of enumeration elements list.
WUF : Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
bits : 20 - 20 (1 bit)
access : read-only
TEACK : Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
bits : 21 - 21 (1 bit)
access : read-only
REACK : Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
bits : 22 - 22 (1 bit)
access : read-only
TXFE : TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
TXFIFO not empty.
0x1 : B_0x1
TXFIFO empty.
End of enumeration elements list.
RXFF : RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
RXFIFO not full.
0x1 : B_0x1
RXFIFO Full.
End of enumeration elements list.
TCBGT : Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1 : B_0x1
Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
End of enumeration elements list.
RXFT : RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Receive FIFO does not reach the programmed threshold.
0x1 : B_0x1
Receive FIFO reached the programmed threshold.
End of enumeration elements list.
TXFT : TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
TXFIFO does not reach the programmed threshold.
0x1 : B_0x1
TXFIFO reached the programmed threshold.
End of enumeration elements list.
Interrupt and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISR_FIFO_ENABLED
reset_Mask : 0x0
PE : Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No parity error
0x1 : B_0x1
Parity error
End of enumeration elements list.
FE : Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Framing error is detected
0x1 : B_0x1
Framing error or break character is detected
End of enumeration elements list.
NE : Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861).
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No noise is detected
0x1 : B_0x1
Noise is detected
End of enumeration elements list.
ORE : Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No overrun error
0x1 : B_0x1
Overrun error is detected
End of enumeration elements list.
IDLE : Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Idle line is detected
0x1 : B_0x1
Idle line is detected
End of enumeration elements list.
RXNE : Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Data is not received
0x1 : B_0x1
Received data is ready to be read.
End of enumeration elements list.
TC : Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Transmission is not complete
0x1 : B_0x1
Transmission is complete
End of enumeration elements list.
TXE : Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Data register full
0x1 : B_0x1
Data register not full
End of enumeration elements list.
LBDF : LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LIN Break not detected
0x1 : B_0x1
LIN break detected
End of enumeration elements list.
CTSIF : CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No change occurred on the nCTS status line
0x1 : B_0x1
A change occurred on the nCTS status line
End of enumeration elements list.
CTS : CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
nCTS line set
0x1 : B_0x1
nCTS line reset
End of enumeration elements list.
RTOF : Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Timeout value not reached
0x1 : B_0x1
Timeout value reached without any data reception
End of enumeration elements list.
EOBF : End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
End of Block not reached
0x1 : B_0x1
End of Block (number of characters) reached
End of enumeration elements list.
UDR : SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No underrun error
0x1 : B_0x1
underrun error
End of enumeration elements list.
ABRE : Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
bits : 14 - 14 (1 bit)
access : read-only
ABRF : Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
bits : 15 - 15 (1 bit)
access : read-only
BUSY : Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
USART is idle (no reception)
0x1 : B_0x1
Reception on going
End of enumeration elements list.
CMF : Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No Character match detected
0x1 : B_0x1
Character Match detected
End of enumeration elements list.
SBKF : Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Break character transmitted
0x1 : B_0x1
Break character requested by setting SBKRQ bit in USART_RQR register
End of enumeration elements list.
RWU : Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Receiver in active mode
0x1 : B_0x1
Receiver in Mute mode
End of enumeration elements list.
WUF : Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
bits : 20 - 20 (1 bit)
access : read-only
TEACK : Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
bits : 21 - 21 (1 bit)
access : read-only
REACK : Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
bits : 22 - 22 (1 bit)
access : read-only
TCBGT : Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1 : B_0x1
Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
End of enumeration elements list.
Interrupt flag clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PECF : Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
bits : 0 - 0 (1 bit)
access : write-only
FECF : Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
bits : 1 - 1 (1 bit)
access : write-only
NECF : Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
bits : 2 - 2 (1 bit)
access : write-only
ORECF : Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
bits : 3 - 3 (1 bit)
access : write-only
IDLECF : Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
bits : 4 - 4 (1 bit)
access : write-only
TXFECF : TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
bits : 5 - 5 (1 bit)
access : write-only
TCCF : Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
bits : 6 - 6 (1 bit)
access : write-only
TCBGTCF : Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
bits : 7 - 7 (1 bit)
access : write-only
LBDCF : LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 8 - 8 (1 bit)
access : write-only
CTSCF : CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 9 - 9 (1 bit)
access : write-only
RTOCF : Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835.
bits : 11 - 11 (1 bit)
access : write-only
EOBCF : End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 12 - 12 (1 bit)
access : write-only
UDRCF : SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
bits : 13 - 13 (1 bit)
access : write-only
CMCF : Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
bits : 17 - 17 (1 bit)
access : write-only
WUCF : Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
bits : 20 - 20 (1 bit)
access : write-only
Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive data value
bits : 0 - 8 (9 bit)
Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit data value
bits : 0 - 8 (9 bit)
Prescaler register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALER : Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
input clock not divided
0x1 : B_0x1
input clock divided by 2
0x2 : B_0x2
input clock divided by 4
0x3 : B_0x3
input clock divided by 6
0x4 : B_0x4
input clock divided by 8
0x5 : B_0x5
input clock divided by 10
0x6 : B_0x6
input clock divided by 12
0x7 : B_0x7
input clock divided by 16
0x8 : B_0x8
input clock divided by 32
0x9 : B_0x9
input clock divided by 64
0xA : B_0xA
input clock divided by 128
0xB : B_0xB
input clock divided by 256
End of enumeration elements list.
Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVEN : Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Slave mode disabled.
0x1 : B_0x1
Slave mode enabled.
End of enumeration elements list.
DIS_NSS : When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI slave selection depends on NSS input pin.
0x1 : B_0x1
SPI slave is always selected and NSS input pin is ignored.
End of enumeration elements list.
ADDM7 : 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
4-bit address detection
0x1 : B_0x1
7-bit address detection (in 8-bit data mode)
End of enumeration elements list.
LBDL : LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
10-bit break detection
0x1 : B_0x1
11-bit break detection
End of enumeration elements list.
LBDIE : LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt is inhibited
0x1 : B_0x1
An interrupt is generated whenever LBDF = 1 in the USART_ISR register
End of enumeration elements list.
LBCL : Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The clock pulse of the last data bit is not output to the SCLK pin
0x1 : B_0x1
The clock pulse of the last data bit is output to the SCLK pin
End of enumeration elements list.
CPHA : Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The first clock transition is the first data capture edge
0x1 : B_0x1
The second clock transition is the first data capture edge
End of enumeration elements list.
CPOL : Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Steady low value on SCLK pin outside transmission window
0x1 : B_0x1
Steady high value on SCLK pin outside transmission window
End of enumeration elements list.
CLKEN : Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SCLK pin disabled
0x1 : B_0x1
SCLK pin enabled
End of enumeration elements list.
STOP : stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 stop bit
0x1 : B_0x1
0.5 stop bit.
0x2 : B_0x2
2 stop bits
0x3 : B_0x3
1.5 stop bits
End of enumeration elements list.
LINEN : LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LIN mode disabled
0x1 : B_0x1
LIN mode enabled
End of enumeration elements list.
SWAP : Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TX/RX pins are used as defined in standard pinout
0x1 : B_0x1
The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
End of enumeration elements list.
RXINV : RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1 : B_0x1
RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
End of enumeration elements list.
TXINV : TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1 : B_0x1
TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
End of enumeration elements list.
DATAINV : Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1 : B_0x1
Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
End of enumeration elements list.
MSBFIRST : Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
data is transmitted/received with data bit 0 first, following the start bit.
0x1 : B_0x1
data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
End of enumeration elements list.
ABREN : Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Auto baud rate detection is disabled.
0x1 : B_0x1
Auto baud rate detection is enabled.
End of enumeration elements list.
ABRMOD : Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Measurement of the start bit is used to detect the baud rate.
0x1 : B_0x1
Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2 : B_0x2
0x7F frame detection.
0x3 : B_0x3
0x55 frame detection
End of enumeration elements list.
RTOEN : Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receiver timeout feature disabled.
0x1 : B_0x1
Receiver timeout feature enabled.
End of enumeration elements list.
ADD : Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0).
bits : 24 - 31 (8 bit)
access : read-write
Control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIE : Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
End of enumeration elements list.
IREN : IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IrDA disabled
0x1 : B_0x1
IrDA enabled
End of enumeration elements list.
IRLP : IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Normal mode
0x1 : B_0x1
Low-power mode
End of enumeration elements list.
HDSEL : Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Half duplex mode is not selected
0x1 : B_0x1
Half duplex mode is selected
End of enumeration elements list.
NACK : Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
NACK transmission in case of parity error is disabled
0x1 : B_0x1
NACK transmission during parity error is enabled
End of enumeration elements list.
SCEN : Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Smartcard Mode disabled
0x1 : B_0x1
Smartcard Mode enabled
End of enumeration elements list.
DMAR : DMA enable receiver This bit is set/reset by software
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x1 : B_0x1
DMA mode is enabled for reception
0x0 : B_0x0
DMA mode is disabled for reception
End of enumeration elements list.
DMAT : DMA enable transmitter This bit is set/reset by software
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x1 : B_0x1
DMA mode is enabled for transmission
0x0 : B_0x0
DMA mode is disabled for transmission
End of enumeration elements list.
RTSE : RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RTS hardware flow control disabled
0x1 : B_0x1
RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
End of enumeration elements list.
CTSE : CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CTS hardware flow control disabled
0x1 : B_0x1
CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
End of enumeration elements list.
CTSIE : CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt is inhibited
0x1 : B_0x1
An interrupt is generated whenever CTSIF = 1 in the USART_ISR register
End of enumeration elements list.
ONEBIT : One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Three sample bit method
0x1 : B_0x1
One sample bit method
End of enumeration elements list.
OVRDIS : Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1 : B_0x1
Overrun functionality is disabled. If new data is received while the RXNE flag is still set
End of enumeration elements list.
DDRE : DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1 : B_0x1
DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
End of enumeration elements list.
DEM : Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DE function is disabled.
0x1 : B_0x1
DE function is enabled. The DE signal is output on the RTS pin.
End of enumeration elements list.
DEP : Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DE signal is active high.
0x1 : B_0x1
DE signal is active low.
End of enumeration elements list.
SCARCNT : Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
retransmission disabled - No automatic retransmission in transmit mode.
0x1 : B_0x1
number of automatic retransmission attempts (before signaling error)
0x2 : B_0x2
number of automatic retransmission attempts (before signaling error)
0x3 : B_0x3
number of automatic retransmission attempts (before signaling error)
0x4 : B_0x4
number of automatic retransmission attempts (before signaling error)
0x5 : B_0x5
number of automatic retransmission attempts (before signaling error)
0x6 : B_0x6
number of automatic retransmission attempts (before signaling error)
0x7 : B_0x7
number of automatic retransmission attempts (before signaling error)
End of enumeration elements list.
WUS : Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2 : B_0x2
WUF active on start bit detection
0x3 : B_0x3
WUF active on RXNE/RXFNE.
End of enumeration elements list.
WUFIE : Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever WUF = 1 in the USART_ISR register
End of enumeration elements list.
TXFTIE : TXFIFO threshold interrupt enable This bit is set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.
End of enumeration elements list.
TCBGTIE : Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated whenever TCBGT=1 in the USART_ISR register
End of enumeration elements list.
RXFTCFG : Receive FIFO threshold configuration Remaining combinations: Reserved
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Receive FIFO reaches 1/8 of its depth
0x1 : B_0x1
Receive FIFO reaches 1/4 of its depth
0x2 : B_0x2
Receive FIFO reaches 1/2 of its depth
0x3 : B_0x3
Receive FIFO reaches 3/4 of its depth
0x4 : B_0x4
Receive FIFO reaches 7/8 of its depth
0x5 : B_0x5
Receive FIFO becomes full
End of enumeration elements list.
RXFTIE : RXFIFO threshold interrupt enable This bit is set and cleared by software.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Interrupt inhibited
0x1 : B_0x1
USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.
End of enumeration elements list.
TXFTCFG : TXFIFO threshold configuration Remaining combinations: Reserved
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TXFIFO reaches 1/8 of its depth
0x1 : B_0x1
TXFIFO reaches 1/4 of its depth
0x2 : B_0x2
TXFIFO reaches 1/2 of its depth
0x3 : B_0x3
TXFIFO reaches 3/4 of its depth
0x4 : B_0x4
TXFIFO reaches 7/8 of its depth
0x5 : B_0x5
TXFIFO becomes empty
End of enumeration elements list.
Baud rate register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRR : USART baud rate
bits : 0 - 15 (16 bit)
access : read-write
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