\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Mode Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLE
The module is disabled.
0x00000001 : OVSSINGLE
Single input LFACLK oversampling mode (available in EM0-EM3).
0x00000002 : EXTCLKSINGLE
Externally clocked single input counter mode (available in EM0-EM3).
0x00000003 : EXTCLKQUAD
Externally clocked quadrature decoder mode (available in EM0-EM3).
0x00000004 : OVSQUAD1X
LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM3).
0x00000005 : OVSQUAD2X
LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM3).
0x00000006 : OVSQUAD4X
LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM3).
End of enumeration elements list.
FILT : Enable Digital Pulse Width Filter
bits : 3 - 3 (1 bit)
access : read-write
RSTEN : Enable PCNT Clock Domain Reset
bits : 4 - 4 (1 bit)
access : read-write
CNTRSTEN : Enable CNT Reset
bits : 5 - 5 (1 bit)
access : read-write
AUXCNTRSTEN : Enable AUXCNT Reset
bits : 6 - 6 (1 bit)
access : read-write
DEBUGHALT : Debug Mode Halt Enable
bits : 7 - 7 (1 bit)
access : read-write
HYST : Enable Hysteresis
bits : 8 - 8 (1 bit)
access : read-write
S1CDIR : Count Direction Determined By S1
bits : 9 - 9 (1 bit)
access : read-write
CNTEV : Controls When the Counter Counts
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x00000000 : BOTH
Counts up on up-count and down on down-count events.
0x00000001 : UP
Only counts up on up-count events.
0x00000002 : DOWN
Only counts down on down-count events.
0x00000003 : NONE
Never counts.
End of enumeration elements list.
AUXCNTEV : Controls When the Auxiliary Counter Counts
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x00000000 : NONE
Never counts.
0x00000001 : UP
Counts up on up-count events.
0x00000002 : DOWN
Counts up on down-count events.
0x00000003 : BOTH
Counts up on both up-count and down-count events.
End of enumeration elements list.
CNTDIR : Non-Quadrature Mode Counter Direction Control
bits : 14 - 14 (1 bit)
access : read-write
EDGE : Edge Select
bits : 15 - 15 (1 bit)
access : read-write
TCCMODE : Sets the Mode for Triggered Compare and Clear
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
Triggered compare and clear not enabled.
0x00000001 : LFA
Compare and clear performed on each (optionally prescaled) LFA clock cycle.
0x00000002 : PRS
Compare and clear performed on positive PRS edges.
End of enumeration elements list.
TCCPRESC : Set the LFA Prescaler for Triggered Compare and Clear
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
Compare and clear event each LFA cycle.
0x00000001 : DIV2
Compare and clear performed on every other LFA cycle.
0x00000002 : DIV4
Compare and clear performed on every 4th LFA cycle.
0x00000003 : DIV8
Compare and clear performed on every 8th LFA cycle.
End of enumeration elements list.
TCCCOMP : Triggered Compare and Clear Compare Mode
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x00000000 : LTOE
Compare match if PCNT_CNT is less than, or equal to PCNT_TOP.
0x00000001 : GTOE
Compare match if PCNT_CNT is greater than or equal to PCNT_TOP.
0x00000002 : RANGE
Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater than, or equal to PCNT_TOP[7:0].
End of enumeration elements list.
PRSGATEEN : PRS Gate Enable
bits : 24 - 24 (1 bit)
access : read-write
TCCPRSPOL : TCC PRS Polarity Select
bits : 25 - 25 (1 bit)
access : read-write
TCCPRSSEL : TCC PRS Channel Select
bits : 26 - 29 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected.
0x00000001 : PRSCH1
PRS Channel 1 selected.
0x00000002 : PRSCH2
PRS Channel 2 selected.
0x00000003 : PRSCH3
PRS Channel 3 selected.
0x00000004 : PRSCH4
PRS Channel 4 selected.
0x00000005 : PRSCH5
PRS Channel 5 selected.
0x00000006 : PRSCH6
PRS Channel 6 selected.
0x00000007 : PRSCH7
PRS Channel 7 selected.
0x00000008 : PRSCH8
PRS Channel 8 selected.
0x00000009 : PRSCH9
PRS Channel 9 selected.
0x0000000A : PRSCH10
PRS Channel 10 selected.
0x0000000B : PRSCH11
PRS Channel 11 selected.
0x0000000C : PRSCH12
PRS Channel 12 selected.
0x0000000D : PRSCH13
PRS Channel 13 selected.
0x0000000E : PRSCH14
PRS Channel 14 selected.
0x0000000F : PRSCH15
PRS Channel 15 selected.
End of enumeration elements list.
TOPBHFSEL : TOPB High Frequency Value Select
bits : 31 - 31 (1 bit)
access : read-write
Top Value Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOP : Counter Top Value
bits : 0 - 15 (16 bit)
access : read-only
Top Value Buffer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOPB : Counter Top Buffer
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UF : Underflow Interrupt Read Flag
bits : 0 - 0 (1 bit)
access : read-only
OF : Overflow Interrupt Read Flag
bits : 1 - 1 (1 bit)
access : read-only
DIRCNG : Direction Change Detect Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
AUXOF : Auxiliary Overflow Interrupt Read Flag
bits : 3 - 3 (1 bit)
access : read-only
TCC : Triggered Compare Interrupt Read Flag
bits : 4 - 4 (1 bit)
access : read-only
OQSTERR : Oversampling Quadrature State Error Interrupt
bits : 5 - 5 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UF : Set UF Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
OF : Set OF Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
DIRCNG : Set DIRCNG Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
AUXOF : Set AUXOF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
TCC : Set TCC Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
OQSTERR : Set OQSTERR Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UF : Clear UF Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
OF : Clear OF Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
DIRCNG : Clear DIRCNG Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
AUXOF : Clear AUXOF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
TCC : Clear TCC Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
OQSTERR : Clear OQSTERR Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UF : UF Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
OF : OF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
DIRCNG : DIRCNG Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
AUXOF : AUXOF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
TCC : TCC Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
OQSTERR : OQSTERR Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
I/O Routing Location Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0INLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
S1INLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LCNTIM : Load CNT Immediately
bits : 0 - 0 (1 bit)
access : write-only
LTOPBIM : Load TOPB Immediately
bits : 1 - 1 (1 bit)
access : write-only
Freeze Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write
Synchronization Busy Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only
CMD : CMD Register Busy
bits : 1 - 1 (1 bit)
access : read-only
TOPB : TOPB Register Busy
bits : 2 - 2 (1 bit)
access : read-only
OVSCFG : OVSCFG Register Busy
bits : 3 - 3 (1 bit)
access : read-only
Auxiliary Counter Value Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AUXCNT : Auxiliary Counter Value
bits : 0 - 15 (16 bit)
access : read-only
PCNT Input Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0PRSSEL : S0IN PRS Channel Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected.
0x00000001 : PRSCH1
PRS Channel 1 selected.
0x00000002 : PRSCH2
PRS Channel 2 selected.
0x00000003 : PRSCH3
PRS Channel 3 selected.
0x00000004 : PRSCH4
PRS Channel 4 selected.
0x00000005 : PRSCH5
PRS Channel 5 selected.
0x00000006 : PRSCH6
PRS Channel 6 selected.
0x00000007 : PRSCH7
PRS Channel 7 selected.
0x00000008 : PRSCH8
PRS Channel 8 selected.
0x00000009 : PRSCH9
PRS Channel 9 selected.
0x0000000A : PRSCH10
PRS Channel 10 selected.
0x0000000B : PRSCH11
PRS Channel 11 selected.
0x0000000C : PRSCH12
PRS Channel 12 selected.
0x0000000D : PRSCH13
PRS Channel 13 selected.
0x0000000E : PRSCH14
PRS Channel 14 selected.
0x0000000F : PRSCH15
PRS Channel 15 selected.
End of enumeration elements list.
S0PRSEN : S0IN PRS Enable
bits : 5 - 5 (1 bit)
access : read-write
S1PRSSEL : S1IN PRS Channel Select
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected.
0x00000001 : PRSCH1
PRS Channel 1 selected.
0x00000002 : PRSCH2
PRS Channel 2 selected.
0x00000003 : PRSCH3
PRS Channel 3 selected.
0x00000004 : PRSCH4
PRS Channel 4 selected.
0x00000005 : PRSCH5
PRS Channel 5 selected.
0x00000006 : PRSCH6
PRS Channel 6 selected.
0x00000007 : PRSCH7
PRS Channel 7 selected.
0x00000008 : PRSCH8
PRS Channel 8 selected.
0x00000009 : PRSCH9
PRS Channel 9 selected.
0x0000000A : PRSCH10
PRS Channel 10 selected.
0x0000000B : PRSCH11
PRS Channel 11 selected.
0x0000000C : PRSCH12
PRS Channel 12 selected.
0x0000000D : PRSCH13
PRS Channel 13 selected.
0x0000000E : PRSCH14
PRS Channel 14 selected.
0x0000000F : PRSCH15
PRS Channel 15 selected.
End of enumeration elements list.
S1PRSEN : S1IN PRS Enable
bits : 11 - 11 (1 bit)
access : read-write
Oversampling Config Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTLEN : Configure Filter Length for Inputs S0IN and S1IN
bits : 0 - 7 (8 bit)
access : read-write
FLUTTERRM : Flutter Remove
bits : 12 - 12 (1 bit)
access : read-write
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DIR : Current Counter Direction
bits : 0 - 0 (1 bit)
access : read-only
Counter Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-only
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