\n

SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSCFG_CFGR1

SYSCFG_EXTICR3

SYSCFG_EXTICR4

SYSCFG_CFGR2

COMP2_CSR

COMP4_CSR

COMP6_CSR

OPAMP2_CSR

SYSCFG_RCR

SYSCFG_CFGR3

SYSCFG_EXTICR1

SYSCFG_EXTICR2


SYSCFG_CFGR1

configuration register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_CFGR1 SYSCFG_CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE USB_IT_RMP TIM1_ITR_RMP DAC_TRIG_RMP ADC24_DMA_RMP TIM16_DMA_RMP TIM17_DMA_RMP TIM6_DAC1_DMA_RMP TIM7_DAC2_DMA_RMP I2C_PB6_FM I2C_PB7_FM I2C_PB8_FM I2C_PB9_FM I2C1_FM I2C2_FM ENCODER_MODE FPU_IT

MEM_MODE : Memory mapping selection bits
bits : 0 - 1 (2 bit)

USB_IT_RMP : USB interrupt remap
bits : 5 - 5 (1 bit)

TIM1_ITR_RMP : Timer 1 ITR3 selection
bits : 6 - 6 (1 bit)

DAC_TRIG_RMP : DAC trigger remap (when TSEL = 001)
bits : 7 - 7 (1 bit)

ADC24_DMA_RMP : ADC24 DMA remapping bit
bits : 8 - 8 (1 bit)

TIM16_DMA_RMP : TIM16 DMA request remapping bit
bits : 11 - 11 (1 bit)

TIM17_DMA_RMP : TIM17 DMA request remapping bit
bits : 12 - 12 (1 bit)

TIM6_DAC1_DMA_RMP : TIM6 and DAC1 DMA request remapping bit
bits : 13 - 13 (1 bit)

TIM7_DAC2_DMA_RMP : TIM7 and DAC2 DMA request remapping bit
bits : 14 - 14 (1 bit)

I2C_PB6_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 16 - 16 (1 bit)

I2C_PB7_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 17 - 17 (1 bit)

I2C_PB8_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 18 - 18 (1 bit)

I2C_PB9_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 19 - 19 (1 bit)

I2C1_FM : I2C1 Fast Mode Plus
bits : 20 - 20 (1 bit)

I2C2_FM : I2C2 Fast Mode Plus
bits : 21 - 21 (1 bit)

ENCODER_MODE : Encoder mode
bits : 22 - 23 (2 bit)

FPU_IT : Interrupt enable bits from FPU
bits : 26 - 31 (6 bit)


SYSCFG_EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_EXTICR3 SYSCFG_EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI 8 configuration bits
bits : 0 - 3 (4 bit)

EXTI9 : EXTI 9 configuration bits
bits : 4 - 7 (4 bit)

EXTI10 : EXTI 10 configuration bits
bits : 8 - 11 (4 bit)

EXTI11 : EXTI 11 configuration bits
bits : 12 - 15 (4 bit)


SYSCFG_EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_EXTICR4 SYSCFG_EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI 12 configuration bits
bits : 0 - 3 (4 bit)

EXTI13 : EXTI 13 configuration bits
bits : 4 - 7 (4 bit)

EXTI14 : EXTI 14 configuration bits
bits : 8 - 11 (4 bit)

EXTI15 : EXTI 15 configuration bits
bits : 12 - 15 (4 bit)


SYSCFG_CFGR2

configuration register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_CFGR2 SYSCFG_CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCUP_LOCK SRAM_PARITY_LOCK PVD_LOCK BYP_ADD_PAR SRAM_PEF

LOCUP_LOCK : Cortex-M0 LOCKUP bit enable bit
bits : 0 - 0 (1 bit)

SRAM_PARITY_LOCK : SRAM parity lock bit
bits : 1 - 1 (1 bit)

PVD_LOCK : PVD lock enable bit
bits : 2 - 2 (1 bit)

BYP_ADD_PAR : Bypass address bit 29 in parity calculation
bits : 4 - 4 (1 bit)

SRAM_PEF : SRAM parity flag
bits : 8 - 8 (1 bit)


COMP2_CSR

control and status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP2_CSR COMP2_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP2EN COMP2MODE COMP2INSEL COMP2INPSEL COMP2INMSEL COMP2_OUT_SEL COMP2POL COMP2HYST COMP2_BLANKING COMP2OUT COMP2LOCK

COMP2EN : Comparator 2 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP2MODE : Comparator 2 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP2INSEL : Comparator 2 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP2INPSEL : Comparator 2 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COMP2INMSEL : Comparator 1inverting input selection
bits : 9 - 9 (1 bit)
access : read-write

COMP2_OUT_SEL : Comparator 2 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP2POL : Comparator 2 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP2HYST : Comparator 2 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP2_BLANKING : Comparator 2 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP2OUT : Comparator 2 output
bits : 30 - 30 (1 bit)
access : read-only

COMP2LOCK : Comparator 2 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP4_CSR

control and status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP4_CSR COMP4_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP4EN COMP4MODE COMP4INSEL COMP4INPSEL COM4WINMODE COMP4_OUT_SEL COMP4POL COMP4HYST COMP4_BLANKING COMP4OUT COMP4LOCK

COMP4EN : Comparator 4 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP4MODE : Comparator 4 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP4INSEL : Comparator 4 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP4INPSEL : Comparator 4 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COM4WINMODE : Comparator 4 window mode
bits : 9 - 9 (1 bit)
access : read-write

COMP4_OUT_SEL : Comparator 4 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP4POL : Comparator 4 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP4HYST : Comparator 4 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP4_BLANKING : Comparator 4 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP4OUT : Comparator 4 output
bits : 30 - 30 (1 bit)
access : read-only

COMP4LOCK : Comparator 4 lock
bits : 31 - 31 (1 bit)
access : read-write


COMP6_CSR

control and status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP6_CSR COMP6_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP6EN COMP6MODE COMP6INSEL COMP6INPSEL COM6WINMODE COMP6_OUT_SEL COMP6POL COMP6HYST COMP6_BLANKING COMP6OUT COMP6LOCK

COMP6EN : Comparator 6 enable
bits : 0 - 0 (1 bit)
access : read-write

COMP6MODE : Comparator 6 mode
bits : 2 - 3 (2 bit)
access : read-write

COMP6INSEL : Comparator 6 inverting input selection
bits : 4 - 6 (3 bit)
access : read-write

COMP6INPSEL : Comparator 6 non inverted input selection
bits : 7 - 7 (1 bit)
access : read-write

COM6WINMODE : Comparator 6 window mode
bits : 9 - 9 (1 bit)
access : read-write

COMP6_OUT_SEL : Comparator 6 output selection
bits : 10 - 13 (4 bit)
access : read-write

COMP6POL : Comparator 6 output polarity
bits : 15 - 15 (1 bit)
access : read-write

COMP6HYST : Comparator 6 hysteresis
bits : 16 - 17 (2 bit)
access : read-write

COMP6_BLANKING : Comparator 6 blanking source
bits : 18 - 20 (3 bit)
access : read-write

COMP6OUT : Comparator 6 output
bits : 30 - 30 (1 bit)
access : read-only

COMP6LOCK : Comparator 6 lock
bits : 31 - 31 (1 bit)
access : read-write


OPAMP2_CSR

OPAMP2 control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP2_CSR OPAMP2_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPAMP2EN FORCE_VP VP_SEL VM_SEL TCM_EN VMS_SEL VPS_SEL CALON CAL_SEL PGA_GAIN USER_TRIM TRIMOFFSETP TRIMOFFSETN TSTREF OUTCAL LOCK

OPAMP2EN : OPAMP2 enable
bits : 0 - 0 (1 bit)
access : read-write

FORCE_VP : FORCE_VP
bits : 1 - 1 (1 bit)
access : read-write

VP_SEL : OPAMP2 Non inverting input selection
bits : 2 - 3 (2 bit)
access : read-write

VM_SEL : OPAMP2 inverting input selection
bits : 5 - 6 (2 bit)
access : read-write

TCM_EN : Timer controlled Mux mode enable
bits : 7 - 7 (1 bit)
access : read-write

VMS_SEL : OPAMP2 inverting input secondary selection
bits : 8 - 8 (1 bit)
access : read-write

VPS_SEL : OPAMP2 Non inverting input secondary selection
bits : 9 - 10 (2 bit)
access : read-write

CALON : Calibration mode enable
bits : 11 - 11 (1 bit)
access : read-write

CAL_SEL : Calibration selection
bits : 12 - 13 (2 bit)
access : read-write

PGA_GAIN : Gain in PGA mode
bits : 14 - 17 (4 bit)
access : read-write

USER_TRIM : User trimming enable
bits : 18 - 18 (1 bit)
access : read-write

TRIMOFFSETP : Offset trimming value (PMOS)
bits : 19 - 23 (5 bit)
access : read-write

TRIMOFFSETN : Offset trimming value (NMOS)
bits : 24 - 28 (5 bit)
access : read-write

TSTREF : TSTREF
bits : 29 - 29 (1 bit)
access : read-write

OUTCAL : OPAMP 2 ouput status flag
bits : 30 - 30 (1 bit)
access : read-only

LOCK : OPAMP 2 lock
bits : 31 - 31 (1 bit)
access : read-write


SYSCFG_RCR

CCM SRAM protection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_RCR SYSCFG_RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE0_WP PAGE1_WP PAGE2_WP PAGE3_WP PAGE4_WP PAGE5_WP PAGE6_WP PAGE7_WP

PAGE0_WP : CCM SRAM page write protection bit
bits : 0 - 0 (1 bit)

PAGE1_WP : CCM SRAM page write protection bit
bits : 1 - 1 (1 bit)

PAGE2_WP : CCM SRAM page write protection bit
bits : 2 - 2 (1 bit)

PAGE3_WP : CCM SRAM page write protection bit
bits : 3 - 3 (1 bit)

PAGE4_WP : CCM SRAM page write protection bit
bits : 4 - 4 (1 bit)

PAGE5_WP : CCM SRAM page write protection bit
bits : 5 - 5 (1 bit)

PAGE6_WP : CCM SRAM page write protection bit
bits : 6 - 6 (1 bit)

PAGE7_WP : CCM SRAM page write protection bit
bits : 7 - 7 (1 bit)


SYSCFG_CFGR3

configuration register 3
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_CFGR3 SYSCFG_CFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1_RX_DMA_RMP SPI1_TX_DMA_RMP I2C1_RX_DMA_RMP ADC2_DMA_RMP_0 ADC2_DMA_RMP_1 DAC1_TRIG3_RMP DAC1_TRIG5_RMP

SPI1_RX_DMA_RMP : SPI1_RX DMA remapping bit
bits : 0 - 1 (2 bit)

SPI1_TX_DMA_RMP : SPI1_TX DMA remapping bit
bits : 2 - 3 (2 bit)

I2C1_RX_DMA_RMP : I2C1_RX DMA remapping bit
bits : 4 - 5 (2 bit)

ADC2_DMA_RMP_0 : ADC2 DMA channel remapping bit
bits : 6 - 7 (2 bit)

ADC2_DMA_RMP_1 : ADC2 DMA controller remapping bit
bits : 9 - 9 (1 bit)

DAC1_TRIG3_RMP : DAC1_CH1 / DAC1_CH2 Trigger remap
bits : 16 - 16 (1 bit)

DAC1_TRIG5_RMP : DAC1_CH1 / DAC1_CH2 Trigger remap
bits : 17 - 17 (1 bit)


SYSCFG_EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_EXTICR1 SYSCFG_EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI 0 configuration bits
bits : 0 - 3 (4 bit)

EXTI1 : EXTI 1 configuration bits
bits : 4 - 7 (4 bit)

EXTI2 : EXTI 2 configuration bits
bits : 8 - 11 (4 bit)

EXTI3 : EXTI 3 configuration bits
bits : 12 - 15 (4 bit)


SYSCFG_EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG_EXTICR2 SYSCFG_EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI 4 configuration bits
bits : 0 - 3 (4 bit)

EXTI5 : EXTI 5 configuration bits
bits : 4 - 7 (4 bit)

EXTI6 : EXTI 6 configuration bits
bits : 8 - 11 (4 bit)

EXTI7 : EXTI 7 configuration bits
bits : 12 - 15 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.