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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CIER

CIFR

CICR

IOPRSTR

AHBRSTR

APBRSTR1

APBRSTR2

IOPENR

AHBENR

APBENR1

ICSCR

APBENR2

IOPSMENR

AHBSMENR

APBSMENR1

APBSMENR2

CCIPR

BDCR

CSR

CFGR

PLLSYSCFGR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIKERON HSIRDY HSIDIV HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

HSION : HSI16 clock enable
bits : 8 - 8 (1 bit)

HSIKERON : HSI16 always enable for peripheral kernels
bits : 9 - 9 (1 bit)

HSIRDY : HSI16 clock ready flag
bits : 10 - 10 (1 bit)

HSIDIV : HSI16 clock division factor
bits : 11 - 13 (3 bit)

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)

HSEBYP : HSE crystal oscillator bypass
bits : 18 - 18 (1 bit)

CSSON : Clock security system enable
bits : 19 - 19 (1 bit)

PLLON : PLL enable
bits : 24 - 24 (1 bit)

PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)


CIER

Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLSYSRDYIE

LSIRDYIE : LSI ready interrupt enable
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)

HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)

HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)

PLLSYSRDYIE : PLL ready interrupt enable
bits : 5 - 5 (1 bit)


CIFR

Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLSYSRDYF CSSF LSECSSF

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)

HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)

PLLSYSRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)

CSSF : Clock security system interrupt flag
bits : 8 - 8 (1 bit)

LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)


CICR

Clock interrupt clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CICR CICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYC LSERDYC HSIRDYC HSERDYC PLLSYSRDYC CSSC LSECSSC

LSIRDYC : LSI ready interrupt clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)

HSIRDYC : HSI ready interrupt clear
bits : 3 - 3 (1 bit)

HSERDYC : HSE ready interrupt clear
bits : 4 - 4 (1 bit)

PLLSYSRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)

CSSC : Clock security system interrupt clear
bits : 8 - 8 (1 bit)

LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)


IOPRSTR

GPIO reset register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPRSTR IOPRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPARST IOPBRST IOPCRST IOPDRST IOPFRST

IOPARST : I/O port A reset
bits : 0 - 0 (1 bit)

IOPBRST : I/O port B reset
bits : 1 - 1 (1 bit)

IOPCRST : I/O port C reset
bits : 2 - 2 (1 bit)

IOPDRST : I/O port D reset
bits : 3 - 3 (1 bit)

IOPFRST : I/O port F reset
bits : 5 - 5 (1 bit)


AHBRSTR

AHB peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARST FLASHRST CRCRST AESRST RNGRST

DMARST : DMA1 reset
bits : 0 - 0 (1 bit)

FLASHRST : FLITF reset
bits : 8 - 8 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

AESRST : AES hardware accelerator reset
bits : 16 - 16 (1 bit)

RNGRST : Random number generator reset
bits : 18 - 18 (1 bit)


APBRSTR1

APB peripheral reset register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBRSTR1 APBRSTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM6RST TIM7RST SPI2RST USART2RST USART3RST USART4RST LPUART1RST I2C1RST I2C2RST CECRST UCPD1RST UCPD2RST DBGRST PWRRST DAC1RST LPTIM2RST LPTIM1RST

TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)

TIM3RST : TIM3 timer reset
bits : 1 - 1 (1 bit)

TIM6RST : TIM6 timer reset
bits : 4 - 4 (1 bit)

TIM7RST : TIM7 timer reset
bits : 5 - 5 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

USART2RST : USART2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART3 reset
bits : 18 - 18 (1 bit)

USART4RST : USART4 reset
bits : 19 - 19 (1 bit)

LPUART1RST : LPUART1 reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

CECRST : HDMI CEC reset
bits : 24 - 24 (1 bit)

UCPD1RST : UCPD1 reset
bits : 25 - 25 (1 bit)

UCPD2RST : UCPD2 reset
bits : 26 - 26 (1 bit)

DBGRST : Debug support reset
bits : 27 - 27 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DAC1RST : DAC1 interface reset
bits : 29 - 29 (1 bit)

LPTIM2RST : Low Power Timer 2 reset
bits : 30 - 30 (1 bit)

LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)


APBRSTR2

APB peripheral reset register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBRSTR2 APBRSTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST TIM1RST SPI1RST USART1RST TIM14RST TIM15RST TIM16RST TIM17RST ADCRST

SYSCFGRST : SYSCFG, COMP and VREFBUF reset
bits : 0 - 0 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

TIM14RST : TIM14 timer reset
bits : 15 - 15 (1 bit)

TIM15RST : TIM15 timer reset
bits : 16 - 16 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)

ADCRST : ADC reset
bits : 20 - 20 (1 bit)


IOPENR

GPIO clock enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPENR IOPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPAEN IOPBEN IOPCEN IOPDEN IOPFEN

IOPAEN : I/O port A clock enable
bits : 0 - 0 (1 bit)

IOPBEN : I/O port B clock enable
bits : 1 - 1 (1 bit)

IOPCEN : I/O port C clock enable
bits : 2 - 2 (1 bit)

IOPDEN : I/O port D clock enable
bits : 3 - 3 (1 bit)

IOPFEN : I/O port F clock enable
bits : 5 - 5 (1 bit)


AHBENR

AHB peripheral clock enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN FLASHEN CRCEN AESEN RNGEN

DMAEN : DMA clock enable
bits : 0 - 0 (1 bit)

FLASHEN : Flash memory interface clock enable
bits : 8 - 8 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

AESEN : AES hardware accelerator
bits : 16 - 16 (1 bit)

RNGEN : Random number generator clock enable
bits : 18 - 18 (1 bit)


APBENR1

APB peripheral clock enable register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBENR1 APBENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM6EN TIM7EN RTCAPBEN WWDGEN SPI2EN USART2EN USART3EN USART4EN LPUART1EN I2C1EN I2C2EN CECEN UCPD1EN UCPD2EN DBGEN PWREN DAC1EN LPTIM2EN LPTIM1EN

TIM2EN : TIM2 timer clock enable
bits : 0 - 0 (1 bit)

TIM3EN : TIM3 timer clock enable
bits : 1 - 1 (1 bit)

TIM6EN : TIM6 timer clock enable
bits : 4 - 4 (1 bit)

TIM7EN : TIM7 timer clock enable
bits : 5 - 5 (1 bit)

RTCAPBEN : RTC APB clock enable
bits : 10 - 10 (1 bit)

WWDGEN : WWDG clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)

USART2EN : USART2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 clock enable
bits : 18 - 18 (1 bit)

USART4EN : USART4 clock enable
bits : 19 - 19 (1 bit)

LPUART1EN : LPUART1 clock enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)

CECEN : HDMI CEC clock enable
bits : 24 - 24 (1 bit)

UCPD1EN : UCPD1 clock enable
bits : 25 - 25 (1 bit)

UCPD2EN : UCPD2 clock enable
bits : 26 - 26 (1 bit)

DBGEN : Debug support clock enable
bits : 27 - 27 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DAC1EN : DAC1 interface clock enable
bits : 29 - 29 (1 bit)

LPTIM2EN : LPTIM2 clock enable
bits : 30 - 30 (1 bit)

LPTIM1EN : LPTIM1 clock enable
bits : 31 - 31 (1 bit)


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSICAL HSITRIM

HSICAL : HSI16 clock calibration
bits : 0 - 7 (8 bit)
access : read-only

HSITRIM : HSI16 clock trimming
bits : 8 - 14 (7 bit)
access : read-write


APBENR2

APB peripheral clock enable register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBENR2 APBENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN TIM1EN SPI1EN USART1EN TIM14EN TIM15EN TIM16EN TIM17EN ADCEN

SYSCFGEN : SYSCFG, COMP and VREFBUF clock enable
bits : 0 - 0 (1 bit)

TIM1EN : TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)

TIM14EN : TIM14 timer clock enable
bits : 15 - 15 (1 bit)

TIM15EN : TIM15 timer clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : TIM16 timer clock enable
bits : 18 - 18 (1 bit)

ADCEN : ADC clock enable
bits : 20 - 20 (1 bit)


IOPSMENR

GPIO in Sleep mode clock enable register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPSMENR IOPSMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPASMEN IOPBSMEN IOPCSMEN IOPDSMEN IOPFSMEN

IOPASMEN : I/O port A clock enable during Sleep mode
bits : 0 - 0 (1 bit)

IOPBSMEN : I/O port B clock enable during Sleep mode
bits : 1 - 1 (1 bit)

IOPCSMEN : I/O port C clock enable during Sleep mode
bits : 2 - 2 (1 bit)

IOPDSMEN : I/O port D clock enable during Sleep mode
bits : 3 - 3 (1 bit)

IOPFSMEN : I/O port F clock enable during Sleep mode
bits : 5 - 5 (1 bit)


AHBSMENR

AHB peripheral clock enable in Sleep mode register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBSMENR AHBSMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASMEN FLASHSMEN SRAMSMEN CRCSMEN AESSMEN RNGSMEN

DMASMEN : DMA clock enable during Sleep mode
bits : 0 - 0 (1 bit)

FLASHSMEN : Flash memory interface clock enable during Sleep mode
bits : 8 - 8 (1 bit)

SRAMSMEN : SRAM clock enable during Sleep mode
bits : 9 - 9 (1 bit)

CRCSMEN : CRC clock enable during Sleep mode
bits : 12 - 12 (1 bit)

AESSMEN : AES hardware accelerator clock enable during Sleep mode
bits : 16 - 16 (1 bit)

RNGSMEN : Random number generator clock enable during Sleep mode
bits : 18 - 18 (1 bit)


APBSMENR1

APB peripheral clock enable in Sleep mode register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBSMENR1 APBSMENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN TIM3SMEN TIM6SMEN TIM7SMEN RTCAPBSMEN WWDGSMEN SPI2SMEN USART2SMEN USART3SMEN USART4SMEN LPUART1SMEN I2C1SMEN I2C2SMEN CECSMEN UCPD1SMEN UCPD2SMEN DBGSMEN PWRSMEN DAC1SMEN LPTIM2SMEN LPTIM1SMEN

TIM2SMEN : TIM2 timer clock enable during Sleep mode
bits : 0 - 0 (1 bit)

TIM3SMEN : TIM3 timer clock enable during Sleep mode
bits : 1 - 1 (1 bit)

TIM6SMEN : TIM6 timer clock enable during Sleep mode
bits : 4 - 4 (1 bit)

TIM7SMEN : TIM7 timer clock enable during Sleep mode
bits : 5 - 5 (1 bit)

RTCAPBSMEN : RTC APB clock enable during Sleep mode
bits : 10 - 10 (1 bit)

WWDGSMEN : WWDG clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI2SMEN : SPI2 clock enable during Sleep mode
bits : 14 - 14 (1 bit)

USART2SMEN : USART2 clock enable during Sleep mode
bits : 17 - 17 (1 bit)

USART3SMEN : USART3 clock enable during Sleep mode
bits : 18 - 18 (1 bit)

USART4SMEN : USART4 clock enable during Sleep mode
bits : 19 - 19 (1 bit)

LPUART1SMEN : LPUART1 clock enable during Sleep mode
bits : 20 - 20 (1 bit)

I2C1SMEN : I2C1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

I2C2SMEN : I2C2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

CECSMEN : HDMI CEC clock enable during Sleep mode
bits : 24 - 24 (1 bit)

UCPD1SMEN : UCPD1 clock enable during Sleep mode
bits : 25 - 25 (1 bit)

UCPD2SMEN : UCPD2 clock enable during Sleep mode
bits : 26 - 26 (1 bit)

DBGSMEN : Debug support clock enable during Sleep mode
bits : 27 - 27 (1 bit)

PWRSMEN : Power interface clock enable during Sleep mode
bits : 28 - 28 (1 bit)

DAC1SMEN : DAC1 interface clock enable during Sleep mode
bits : 29 - 29 (1 bit)

LPTIM2SMEN : Low Power Timer 2 clock enable during Sleep mode
bits : 30 - 30 (1 bit)

LPTIM1SMEN : Low Power Timer 1 clock enable during Sleep mode
bits : 31 - 31 (1 bit)


APBSMENR2

APB peripheral clock enable in Sleep mode register 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBSMENR2 APBSMENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGSMEN TIM1SMEN SPI1SMEN USART1SMEN TIM14SMEN TIM15SMEN TIM16SMEN TIM17SMEN ADCSMEN

SYSCFGSMEN : SYSCFG, COMP and VREFBUF clock enable during Sleep mode
bits : 0 - 0 (1 bit)

TIM1SMEN : TIM1 timer clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clock enable during Sleep mode
bits : 12 - 12 (1 bit)

USART1SMEN : USART1 clock enable during Sleep mode
bits : 14 - 14 (1 bit)

TIM14SMEN : TIM14 timer clock enable during Sleep mode
bits : 15 - 15 (1 bit)

TIM15SMEN : TIM15 timer clock enable during Sleep mode
bits : 16 - 16 (1 bit)

TIM16SMEN : TIM16 timer clock enable during Sleep mode
bits : 17 - 17 (1 bit)

TIM17SMEN : TIM16 timer clock enable during Sleep mode
bits : 18 - 18 (1 bit)

ADCSMEN : ADC clock enable during Sleep mode
bits : 20 - 20 (1 bit)


CCIPR

Peripherals independent clock configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCIPR CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SEL USART2SEL CECSEL LPUART1SEL I2C1SEL I2S2SEL LPTIM1SEL LPTIM2SEL TIM1SEL TIM15SEL RNGSEL RNGDIV ADCSEL

USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)

USART2SEL : USART2 clock source selection
bits : 2 - 3 (2 bit)

CECSEL : HDMI CEC clock source selection
bits : 6 - 6 (1 bit)

LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)

I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)

I2S2SEL : I2S1 clock source selection
bits : 14 - 15 (2 bit)

LPTIM1SEL : LPTIM1 clock source selection
bits : 18 - 19 (2 bit)

LPTIM2SEL : LPTIM2 clock source selection
bits : 20 - 21 (2 bit)

TIM1SEL : TIM1 clock source selection
bits : 22 - 22 (1 bit)

TIM15SEL : TIM15 clock source selection
bits : 24 - 24 (1 bit)

RNGSEL : RNG clock source selection
bits : 26 - 27 (2 bit)

RNGDIV : Division factor of RNG clock divider
bits : 28 - 29 (2 bit)

ADCSEL : ADCs clock source selection
bits : 30 - 31 (2 bit)


BDCR

RTC domain control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV LSECSSON LSECSSD RTCSEL RTCEN BDRST LSCOEN LSCOSEL

LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)

LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)

LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)

LSEDRV : LSE oscillator drive capability
bits : 3 - 4 (2 bit)

LSECSSON : CSS on LSE enable
bits : 5 - 5 (1 bit)

LSECSSD : CSS on LSE failure Detection
bits : 6 - 6 (1 bit)

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)

BDRST : RTC domain software reset
bits : 16 - 16 (1 bit)

LSCOEN : Low-speed clock output (LSCO) enable
bits : 24 - 24 (1 bit)

LSCOSEL : Low-speed clock output selection
bits : 25 - 25 (1 bit)


CSR

Control/status register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY RMVF OBLRSTF PINRSTF PWRRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)

LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)

RMVF : Remove reset flags
bits : 23 - 23 (1 bit)

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)

PINRSTF : Pin reset flag
bits : 26 - 26 (1 bit)

PWRRSTF : BOR or POR/PDR flag
bits : 27 - 27 (1 bit)

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)

IWDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)


CFGR

Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE MCOSEL MCOPRE

SW : System clock switch
bits : 0 - 2 (3 bit)
access : read-write

SWS : System clock switch status
bits : 3 - 5 (3 bit)
access : read-only

HPRE : AHB prescaler
bits : 8 - 11 (4 bit)
access : read-write

PPRE : APB prescaler
bits : 12 - 14 (3 bit)
access : read-write

MCOSEL : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write

MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-only


PLLSYSCFGR

PLL configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSYSCFGR PLLSYSCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC PLLM PLLN PLLPEN PLLP PLLQEN PLLQ PLLREN PLLR

PLLSRC : PLL input clock source
bits : 0 - 1 (2 bit)

PLLM : Division factor M of the PLL input clock divider
bits : 4 - 6 (3 bit)

PLLN : PLL frequency multiplication factor N
bits : 8 - 14 (7 bit)

PLLPEN : PLLPCLK clock output enable
bits : 16 - 16 (1 bit)

PLLP : PLL VCO division factor P for PLLPCLK clock output
bits : 17 - 21 (5 bit)

PLLQEN : PLLQCLK clock output enable
bits : 24 - 24 (1 bit)

PLLQ : PLL VCO division factor Q for PLLQCLK clock output
bits : 25 - 27 (3 bit)

PLLREN : PLLRCLK clock output enable
bits : 28 - 28 (1 bit)

PLLR : PLL VCO division factor R for PLLRCLK clock output
bits : 29 - 31 (3 bit)



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