Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Counter disabled
0x1 : B_0x1
Counter enabled
End of enumeration elements list.
UDIS : Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1 : B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
End of enumeration elements list.
URS : Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Any of the following events generate an update interrupt if enabled. These events can be:
0x1 : B_0x1
Only counter overflow/underflow generates an update interrupt if enabled
End of enumeration elements list.
OPM : One-pulse mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Counter is not stopped at update event
0x1 : B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
End of enumeration elements list.
ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIMx_ARR register is not buffered
0x1 : B_0x1
TIMx_ARR register is buffered
End of enumeration elements list.
CKD : Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
tDTS = tCK_INT
0x1 : B_0x1
tDTS = 2*tCK_INT
0x2 : B_0x2
tDTS = 4*tCK_INT
0x3 : B_0x3
Reserved, do not program this value
End of enumeration elements list.
UIFREMAP : UIF status bit remapping
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1 : B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
End of enumeration elements list.
status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No update occurred.
0x1 : B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
End of enumeration elements list.
CC1IF : Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No compare match / No input capture occurred
0x1 : B_0x1
A compare match or an input capture occurred
End of enumeration elements list.
CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description
bits : 2 - 2 (1 bit)
access : read-write
COMIF : COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No COM event occurred
0x1 : B_0x1
COM interrupt pending
End of enumeration elements list.
TIF : Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No trigger event occurred
0x1 : B_0x1
Trigger interrupt pending
End of enumeration elements list.
BIF : Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No break event occurred
0x1 : B_0x1
An active level has been detected on the break input
End of enumeration elements list.
CC1OF : Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No overcapture has been detected
0x1 : B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
End of enumeration elements list.
CC2OF : Capture/Compare 2 overcapture flag Refer to CC1OF description
bits : 10 - 10 (1 bit)
access : read-write
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation This bit can be set by software, it is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
End of enumeration elements list.
CC1G : Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
A capture/compare event is generated on channel 1:
End of enumeration elements list.
CC2G : Capture/Compare 2 generation Refer to CC1G description
bits : 2 - 2 (1 bit)
access : write-only
COMG : Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
End of enumeration elements list.
TG : Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled
End of enumeration elements list.
BG : Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
End of enumeration elements list.
capture/compare mode register (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 channel is configured as output.
0x1 : B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1.
0x2 : B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2.
0x3 : B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
End of enumeration elements list.
OC1FE : Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1 : B_0x1
An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
End of enumeration elements list.
OC1PE : Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1 : B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
End of enumeration elements list.
OC1M1 : Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x1 : B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2 : B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x3 : B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x4 : B_0x4
Force inactive level - OC1REF is forced low.
0x5 : B_0x5
Force active level - OC1REF is forced high.
0x6 : B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x7 : B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x8 : B_0x8
Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x9 : B_0x9
Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0xC : B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xD : B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
End of enumeration elements list.
CC2S : Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC2 channel is configured as output.
0x1 : B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2.
0x2 : B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1.
0x3 : B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
End of enumeration elements list.
OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)
access : read-write
OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)
access : read-write
OC2M1 : Output Compare 2 mode
bits : 12 - 14 (3 bit)
access : read-write
OC1M2 : Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
0x1 : B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2 : B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x3 : B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x4 : B_0x4
Force inactive level - OC1REF is forced low.
0x5 : B_0x5
Force active level - OC1REF is forced high.
0x6 : B_0x6
PWM mode 1 - Channel 1 is active as long as TIMx_CNT
0x7 : B_0x7
PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT
0x8 : B_0x8
Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
0x9 : B_0x9
Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
0xC : B_0xC
Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.
0xD : B_0xD
Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.
End of enumeration elements list.
OC2M2 : Output Compare 2 mode
bits : 24 - 24 (1 bit)
access : read-write
capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCMR1_Output
reset_Mask : 0x0
CC1S : Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 channel is configured as output
0x1 : B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x2 : B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x3 : B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
End of enumeration elements list.
IC1PSC : Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no prescaler, capture is done each time an edge is detected on the capture input
0x1 : B_0x1
capture is done once every 2 events
0x2 : B_0x2
capture is done once every 4 events
0x3 : B_0x3
capture is done once every 8 events
End of enumeration elements list.
IC1F : Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No filter, sampling is done at fDTS
0x1 : B_0x1
fSAMPLING=fCK_INT, N=2
0x2 : B_0x2
fSAMPLING=fCK_INT, N=4
0x3 : B_0x3
fSAMPLING=fCK_INT, N=8
0x4 : B_0x4
fSAMPLING=fDTS/2, N=6
0x5 : B_0x5
fSAMPLING=fDTS/2, N=8
0x6 : B_0x6
fSAMPLING=fDTS/4, N=6
0x7 : B_0x7
fSAMPLING=fDTS/4, N=8
0x8 : B_0x8
fSAMPLING=fDTS/8, N=6
0x9 : B_0x9
fSAMPLING=fDTS/8, N=8
0xA : B_0xA
fSAMPLING=fDTS/16, N=5
0xB : B_0xB
fSAMPLING=fDTS/16, N=6
0xC : B_0xC
fSAMPLING=fDTS/16, N=8
0xD : B_0xD
fSAMPLING=fDTS/32, N=5
0xE : B_0xE
fSAMPLING=fDTS/32, N=6
0xF : B_0xF
fSAMPLING=fDTS/32, N=8
End of enumeration elements list.
CC2S : Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC2 channel is configured as output
0x1 : B_0x1
CC2 channel is configured as input, IC2 is mapped on TI2
0x2 : B_0x2
CC2 channel is configured as input, IC2 is mapped on TI1
0x3 : B_0x3
CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
End of enumeration elements list.
IC2PSC : Input capture 2 prescaler
bits : 10 - 11 (2 bit)
access : read-write
IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)
access : read-write
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Capture mode disabled / OC1 is not active (see below)
0x1 : B_0x1
Capture mode enabled / OC1 signal is output on the corresponding output pin
End of enumeration elements list.
CC1P : Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1 : B_0x1
OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
End of enumeration elements list.
CC1NE : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1 : B_0x1
On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
End of enumeration elements list.
CC1NP : Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OC1N active high
0x1 : B_0x1
OC1N active low
End of enumeration elements list.
CC2E : Capture/Compare 2 output enable Refer to CC1E description
bits : 4 - 4 (1 bit)
access : read-write
CC2P : Capture/Compare 2 output polarity Refer to CC1P description
bits : 5 - 5 (1 bit)
access : read-write
CC2NP : Capture/Compare 2 complementary output polarity Refer to CC1NP description
bits : 7 - 7 (1 bit)
access : read-write
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : counter value
bits : 0 - 15 (16 bit)
access : read-write
UIFCPY : UIF Copy
bits : 31 - 31 (1 bit)
access : read-only
prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler value
bits : 0 - 15 (16 bit)
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : Auto-reload value
bits : 0 - 15 (16 bit)
repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP : Repetition counter value
bits : 0 - 7 (8 bit)
capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : Capture/Compare 1 value
bits : 0 - 15 (16 bit)
capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : Capture/Compare 2 value
bits : 0 - 15 (16 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPC : Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CCxE, CCxNE and OCxM bits are not preloaded
0x1 : B_0x1
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
End of enumeration elements list.
CCUS : Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1 : B_0x1
When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
End of enumeration elements list.
CCDS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CCx DMA request sent when CCx event occurs
0x1 : B_0x1
CCx DMA requests sent when update event occurs
End of enumeration elements list.
MMS : Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1 : B_0x1
Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2 : B_0x2
Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3 : B_0x3
Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x4 : B_0x4
Compare - OC1REFC signal is used as trigger output (TRGO).
0x5 : B_0x5
Compare - OC2REFC signal is used as trigger output (TRGO).
End of enumeration elements list.
TI1S : TI1 selection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The TIMx_CH1 pin is connected to TI1 input
0x1 : B_0x1
The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)
End of enumeration elements list.
OIS1 : Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1 : B_0x1
OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
End of enumeration elements list.
OIS1N : Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OC1N=0 after a dead-time when MOE=0
0x1 : B_0x1
OC1N=1 after a dead-time when MOE=0
End of enumeration elements list.
OIS2 : Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OC2=0 when MOE=0
0x1 : B_0x1
OC2=1 when MOE=0
End of enumeration elements list.
break and dead-time register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTG : Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 0 - 7 (8 bit)
access : read-write
LOCK : Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LOCK OFF - No bit is write protected
0x1 : B_0x1
LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
0x2 : B_0x2
LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3 : B_0x3
LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
End of enumeration elements list.
OSSI : Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1 : B_0x1
When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
End of enumeration elements list.
OSSR : Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1 : B_0x1
When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
End of enumeration elements list.
BKE : Break enable 1 Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Break inputs (BRK and CCS clock failure event) disabled
End of enumeration elements list.
BKP : Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Break input BRK is active low
0x1 : B_0x1
Break input BRK is active high
End of enumeration elements list.
AOE : Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MOE can be set only by software
0x1 : B_0x1
MOE can be set by software or automatically at the next update event (if the break input is not be active)
End of enumeration elements list.
MOE : Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1 : B_0x1
OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)
End of enumeration elements list.
BKF : Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No filter, BRK acts asynchronously
0x1 : B_0x1
fSAMPLING=fCK_INT, N=2
0x2 : B_0x2
fSAMPLING=fCK_INT, N=4
0x3 : B_0x3
fSAMPLING=fCK_INT, N=8
0x4 : B_0x4
fSAMPLING=fDTS/2, N=6
0x5 : B_0x5
fSAMPLING=fDTS/2, N=8
0x6 : B_0x6
fSAMPLING=fDTS/4, N=6
0x7 : B_0x7
fSAMPLING=fDTS/4, N=8
0x8 : B_0x8
fSAMPLING=fDTS/8, N=6
0x9 : B_0x9
fSAMPLING=fDTS/8, N=8
0xA : B_0xA
fSAMPLING=fDTS/16, N=5
0xB : B_0xB
fSAMPLING=fDTS/16, N=6
0xC : B_0xC
fSAMPLING=fDTS/16, N=8
0xD : B_0xD
fSAMPLING=fDTS/32, N=5
0xE : B_0xE
fSAMPLING=fDTS/32, N=6
0xF : B_0xF
fSAMPLING=fDTS/32, N=8
End of enumeration elements list.
BKDSRM : Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Break input BRK is armed
0x1 : B_0x1
Break input BRK is disarmed
End of enumeration elements list.
BKBID : Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Break input BRK in input mode
0x1 : B_0x1
Break input BRK in bidirectional mode
End of enumeration elements list.
DMA control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIMx_CR1,
0x1 : B_0x1
TIMx_CR2,
0x2 : B_0x2
TIMx_SMCR,
End of enumeration elements list.
DBL : DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x0 : B_0x0
1 transfer,
0x1 : B_0x1
2 transfers,
0x2 : B_0x2
3 transfers,
0x11 : B_0x11
18 transfers.
End of enumeration elements list.
DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS1 : Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock.
0x4 : B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x5 : B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x6 : B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x7 : B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x8 : B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.
End of enumeration elements list.
TS1 : Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Internal Trigger 0 (ITR0)
0x1 : B_0x1
Internal Trigger 1 (ITR1)
0x2 : B_0x2
Internal Trigger 2 (ITR2)
0x3 : B_0x3
Internal Trigger 3 (ITR3)
0x4 : B_0x4
TI1 Edge Detector (TI1F_ED)
0x5 : B_0x5
Filtered Timer Input 1 (TI1FP1)
0x6 : B_0x6
Filtered Timer Input 2 (TI2FP2)
End of enumeration elements list.
MSM : Master/slave mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
End of enumeration elements list.
SMS2 : Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock.
0x4 : B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x5 : B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x6 : B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x7 : B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x8 : B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.
End of enumeration elements list.
TS2 : Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Internal Trigger 0 (ITR0)
0x1 : B_0x1
Internal Trigger 1 (ITR1)
0x2 : B_0x2
Internal Trigger 2 (ITR2)
0x3 : B_0x3
Internal Trigger 3 (ITR3)
0x4 : B_0x4
TI1 Edge Detector (TI1F_ED)
0x5 : B_0x5
Filtered Timer Input 1 (TI1FP1)
0x6 : B_0x6
Filtered Timer Input 2 (TI2FP2)
End of enumeration elements list.
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Update interrupt disabled
0x1 : B_0x1
Update interrupt enabled
End of enumeration elements list.
CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 interrupt disabled
0x1 : B_0x1
CC1 interrupt enabled
End of enumeration elements list.
CC2IE : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC2 interrupt disabled
0x1 : B_0x1
CC2 interrupt enabled
End of enumeration elements list.
COMIE : COM interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
COM interrupt disabled
0x1 : B_0x1
COM interrupt enabled
End of enumeration elements list.
TIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger interrupt disabled
0x1 : B_0x1
Trigger interrupt enabled
End of enumeration elements list.
BIE : Break interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Break interrupt disabled
0x1 : B_0x1
Break interrupt enabled
End of enumeration elements list.
UDE : Update DMA request enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Update DMA request disabled
0x1 : B_0x1
Update DMA request enabled
End of enumeration elements list.
CC1DE : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 DMA request disabled
0x1 : B_0x1
CC1 DMA request enabled
End of enumeration elements list.
CC2DE : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC2 DMA request disabled
0x1 : B_0x1
CC2 DMA request enabled
End of enumeration elements list.
COMDE : COM DMA request enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
COM DMA request disabled
0x1 : B_0x1
COM DMA request enabled
End of enumeration elements list.
TDE : Trigger DMA request enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger DMA request disabled
0x1 : B_0x1
Trigger DMA request enabled
End of enumeration elements list.
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