I2C_CR1

I2C_TIMINGR

I2C_TIMEOUTR

I2C_ISR

I2C_ICR

I2C_PECR

I2C_RXDR

I2C_TXDR

I2C_CR2

I2C_OAR1

I2C_OAR2

PE : Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXIE : TX Interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXIE : RX Interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRIE : Address match Interrupt enable (slave only)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NACKIE : Not acknowledge received Interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOPIE : Stop detection Interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCIE : Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERRIE : Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DNF : Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANFOFF : Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXDMAEN : DMA transmission requests enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDMAEN : DMA reception requests enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SBC : Slave byte control This bit is used to enable hardware byte control in slave mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NOSTRETCH : Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WUPEN : Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GCEN : General call enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMBHEN : SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMBDEN : SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALERTEN : SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECEN : PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCLL : SCL low period (master mode)
bits : 0 - 7 (8 bit)

SCLH : SCL high period (master mode)
bits : 8 - 15 (8 bit)

SDADEL : Data hold time
bits : 16 - 19 (4 bit)

SCLDEL : Data setup time
bits : 20 - 23 (4 bit)

PRESC : Timing prescaler
bits : 28 - 31 (4 bit)

TIMEOUTA : Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
bits : 0 - 11 (12 bit)
access : read-write

TIDLE : Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIMOUTEN : Clock timeout enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIMEOUTB : Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
bits : 16 - 27 (12 bit)
access : read-write

TEXTEN : Extended clock timeout enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXE : Transmit data register empty (transmitters)
bits : 0 - 0 (1 bit)
access : read-write

TXIS : Transmit interrupt status (transmitters)
bits : 1 - 1 (1 bit)
access : read-write

RXNE : Receive data register not empty (receivers)
bits : 2 - 2 (1 bit)
access : read-only

ADDR : Address matched (slave mode)
bits : 3 - 3 (1 bit)
access : read-only

NACKF : Not acknowledge received flag
bits : 4 - 4 (1 bit)
access : read-only

STOPF : Stop detection flag
bits : 5 - 5 (1 bit)
access : read-only

TC : Transfer Complete (master mode)
bits : 6 - 6 (1 bit)
access : read-only

TCR : Transfer Complete Reload
bits : 7 - 7 (1 bit)
access : read-only

BERR : Bus error
bits : 8 - 8 (1 bit)
access : read-only

ARLO : Arbitration lost
bits : 9 - 9 (1 bit)
access : read-only

OVR : Overrun/Underrun (slave mode)
bits : 10 - 10 (1 bit)
access : read-only

PECERR : PEC Error in reception
bits : 11 - 11 (1 bit)
access : read-only

TIMEOUT : Timeout or t_low detection flag
bits : 12 - 12 (1 bit)
access : read-only

ALERT : SMBus alert
bits : 13 - 13 (1 bit)
access : read-only

BUSY : Bus busy
bits : 15 - 15 (1 bit)
access : read-only

DIR : Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADDCODE : Address match code (Slave mode)
bits : 17 - 23 (7 bit)
access : read-only

ADDRCF : Address Matched flag clear
bits : 3 - 3 (1 bit)

NACKCF : Not Acknowledge flag clear
bits : 4 - 4 (1 bit)

STOPCF : Stop detection flag clear
bits : 5 - 5 (1 bit)

BERRCF : Bus error flag clear
bits : 8 - 8 (1 bit)

ARLOCF : Arbitration lost flag clear
bits : 9 - 9 (1 bit)

OVRCF : Overrun/Underrun flag clear
bits : 10 - 10 (1 bit)

PECCF : PEC Error flag clear
bits : 11 - 11 (1 bit)

TIMOUTCF : Timeout detection flag clear
bits : 12 - 12 (1 bit)

ALERTCF : Alert flag clear
bits : 13 - 13 (1 bit)

PEC : Packet error checking register
bits : 0 - 7 (8 bit)

RXDATA : 8-bit receive data
bits : 0 - 7 (8 bit)

TXDATA : 8-bit transmit data
bits : 0 - 7 (8 bit)

SADD : Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
bits : 0 - 9 (10 bit)
access : read-write

RD_WRN : Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADD10 : 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HEAD10R : 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

START : Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NACK : NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NBYTES : Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
bits : 16 - 23 (8 bit)
access : read-write

RELOAD : NBYTES reload mode This bit is set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOEND : Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECBYTE : Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OA1 : Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
bits : 0 - 9 (10 bit)
access : read-write

OA1MODE : Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OA1EN : Own Address 1 enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OA2 : Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
bits : 1 - 7 (7 bit)
access : read-write

OA2MSK : Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OA2EN : Own Address 2 enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.