IWDG_KR (KR)

IWDG_WINR (WINR)

IWDG_PR (PR)

IWDG_RLR (RLR)

IWDG_SR (SR)

KEY : Key value (write only, read 0x0000)
bits : 0 - 15 (16 bit)

WIN : Watchdog counter window value
bits : 0 - 11 (12 bit)

PR : Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RL : Watchdog counter reload value
bits : 0 - 11 (12 bit)

PVU : Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
bits : 0 - 0 (1 bit)
access : read-only

RVU : Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
bits : 1 - 1 (1 bit)
access : read-only

WVU : Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
bits : 2 - 2 (1 bit)
access : read-only