Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Counter disabled
0x1 : B_0x1
Counter enabled
End of enumeration elements list.
UDIS : Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1 : B_0x1
UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
End of enumeration elements list.
URS : Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1 : B_0x1
Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
End of enumeration elements list.
OPM : One-pulse mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Counter is not stopped at update event
0x1 : B_0x1
Counter stops counting at the next update event (clearing the bit CEN)
End of enumeration elements list.
DIR : Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Counter used as upcounter
0x1 : B_0x1
Counter used as downcounter
End of enumeration elements list.
CMS : Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1 : B_0x1
Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2 : B_0x2
Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3 : B_0x3
Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
End of enumeration elements list.
ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIMx_ARR register is not buffered
0x1 : B_0x1
TIMx_ARR register is buffered
End of enumeration elements list.
CKD : Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
tDTS = tCK_INT
0x1 : B_0x1
tDTS = 2 Ã tCK_INT
0x2 : B_0x2
tDTS = 4 Ã tCK_INT
End of enumeration elements list.
UIFREMAP : UIF status bit remapping
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1 : B_0x1
Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
End of enumeration elements list.
status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No update occurred
0x1 : B_0x1
Update interrupt pending. This bit is set by hardware when the registers are updated:
End of enumeration elements list.
CC1IF : Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No compare match / No input capture occurred
0x1 : B_0x1
A compare match or an input capture occurred
End of enumeration elements list.
CC2IF : Capture/Compare 2 interrupt flag Refer to CC1IF description
bits : 2 - 2 (1 bit)
access : read-write
CC3IF : Capture/Compare 3 interrupt flag Refer to CC1IF description
bits : 3 - 3 (1 bit)
access : read-write
CC4IF : Capture/Compare 4 interrupt flag Refer to CC1IF description
bits : 4 - 4 (1 bit)
access : read-write
TIF : Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No trigger event occurred.
0x1 : B_0x1
Trigger interrupt pending.
End of enumeration elements list.
CC1OF : Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No overcapture has been detected.
0x1 : B_0x1
The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
End of enumeration elements list.
CC2OF : Capture/compare 2 overcapture flag refer to CC1OF description
bits : 10 - 10 (1 bit)
access : read-write
CC3OF : Capture/Compare 3 overcapture flag refer to CC1OF description
bits : 11 - 11 (1 bit)
access : read-write
CC4OF : Capture/Compare 4 overcapture flag refer to CC1OF description
bits : 12 - 12 (1 bit)
access : read-write
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation This bit can be set by software, it is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
End of enumeration elements list.
CC1G : Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
A capture/compare event is generated on channel 1:
End of enumeration elements list.
CC2G : Capture/compare 2 generation Refer to CC1G description
bits : 2 - 2 (1 bit)
access : write-only
CC3G : Capture/compare 3 generation Refer to CC1G description
bits : 3 - 3 (1 bit)
access : write-only
CC4G : Capture/compare 4 generation Refer to CC1G description
bits : 4 - 4 (1 bit)
access : write-only
TG : Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
End of enumeration elements list.
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 channel is configured as output
0x1 : B_0x1
CC1 channel is configured as input, IC1 is mapped on TI1
0x2 : B_0x2
CC1 channel is configured as input, IC1 is mapped on TI2
0x3 : B_0x3
CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
End of enumeration elements list.
OC1FE : Output compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1 : B_0x1
Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
End of enumeration elements list.
OC1M1 : Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
0x1 : B_0x1
Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x2 : B_0x2
Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0x3 : B_0x3
Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0x4 : B_0x4
Force inactive level - OC1REF is forced low.
0x5 : B_0x5
Force active level - OC1REF is forced high.
0x6 : B_0x6
PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT
0x1 : B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x2 : B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x3 : B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x4 : B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x5 : B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x6 : B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x7 : B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x8 : B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
End of enumeration elements list.
OCCS : OCREF clear selection This bit is used to select the OCREF clear source
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR
0x1 : B_0x1
OCREF_CLR_INT is connected to ETRF
End of enumeration elements list.
TS1 : Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Internal Trigger 0 (ITR0)
0x1 : B_0x1
Internal Trigger 1 (ITR1)
0x2 : B_0x2
Internal Trigger 2 (ITR2)
0x3 : B_0x3
Internal Trigger 3 (ITR3)
0x4 : B_0x4
TI1 Edge Detector (TI1F_ED)
0x5 : B_0x5
Filtered Timer Input 1 (TI1FP1)
0x6 : B_0x6
Filtered Timer Input 2 (TI2FP2)
0x7 : B_0x7
External Trigger input (ETRF)
0x8 : B_0x8
Internal Trigger 4 (ITR4)
0x9 : B_0x9
Internal Trigger 5 (ITR5)
0xA : B_0xA
Internal Trigger 6 (ITR6)
0xB : B_0xB
Internal Trigger 7 (ITR7)
0xC : B_0xC
Internal Trigger 8 (ITR8)
End of enumeration elements list.
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No action
0x1 : B_0x1
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
End of enumeration elements list.
ETF : External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No filter, sampling is done at fDTS
0x1 : B_0x1
fSAMPLING=fCK_INT, N=2
0x2 : B_0x2
fSAMPLING=fCK_INT, N=4
0x3 : B_0x3
fSAMPLING=fCK_INT, N=8
0x4 : B_0x4
fSAMPLING=fDTS/2, N=6
0x5 : B_0x5
fSAMPLING=fDTS/2, N=8
0x6 : B_0x6
fSAMPLING=fDTS/4, N=6
0x7 : B_0x7
fSAMPLING=fDTS/4, N=8
0x8 : B_0x8
fSAMPLING=fDTS/8, N=6
0x9 : B_0x9
fSAMPLING=fDTS/8, N=8
0xA : B_0xA
fSAMPLING=fDTS/16, N=5
0xB : B_0xB
fSAMPLING=fDTS/16, N=6
0xC : B_0xC
fSAMPLING=fDTS/16, N=8
0xD : B_0xD
fSAMPLING=fDTS/32, N=5
0xE : B_0xE
fSAMPLING=fDTS/32, N=6
0xF : B_0xF
fSAMPLING=fDTS/32, N=8
End of enumeration elements list.
ETPS : External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Prescaler OFF
0x1 : B_0x1
ETRP frequency divided by 2
0x2 : B_0x2
ETRP frequency divided by 4
0x3 : B_0x3
ETRP frequency divided by 8
End of enumeration elements list.
ECE : External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
External clock mode 2 disabled
0x1 : B_0x1
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
End of enumeration elements list.
ETP : External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ETR is non-inverted, active at high level or rising edge
0x1 : B_0x1
ETR is inverted, active at low level or falling edge
End of enumeration elements list.
SMS2 : Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock.
0x1 : B_0x1
Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0x2 : B_0x2
Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0x3 : B_0x3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0x4 : B_0x4
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0x5 : B_0x5
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0x6 : B_0x6
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0x7 : B_0x7
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0x8 : B_0x8
Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
End of enumeration elements list.
TS2 : Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Internal Trigger 0 (ITR0)
0x1 : B_0x1
Internal Trigger 1 (ITR1)
0x2 : B_0x2
Internal Trigger 2 (ITR2)
0x3 : B_0x3
Internal Trigger 3 (ITR3)
0x4 : B_0x4
TI1 Edge Detector (TI1F_ED)
0x5 : B_0x5
Filtered Timer Input 1 (TI1FP1)
0x6 : B_0x6
Filtered Timer Input 2 (TI2FP2)
0x7 : B_0x7
External Trigger input (ETRF)
0x8 : B_0x8
Internal Trigger 4 (ITR4)
0x9 : B_0x9
Internal Trigger 5 (ITR5)
0xA : B_0xA
Internal Trigger 6 (ITR6)
0xB : B_0xB
Internal Trigger 7 (ITR7)
0xC : B_0xC
Internal Trigger 8 (ITR8)
End of enumeration elements list.
DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Update interrupt disabled.
0x1 : B_0x1
Update interrupt enabled.
End of enumeration elements list.
CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 interrupt disabled.
0x1 : B_0x1
CC1 interrupt enabled.
End of enumeration elements list.
CC2IE : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC2 interrupt disabled.
0x1 : B_0x1
CC2 interrupt enabled.
End of enumeration elements list.
CC3IE : Capture/Compare 3 interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC3 interrupt disabled.
0x1 : B_0x1
CC3 interrupt enabled.
End of enumeration elements list.
CC4IE : Capture/Compare 4 interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC4 interrupt disabled.
0x1 : B_0x1
CC4 interrupt enabled.
End of enumeration elements list.
TIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger interrupt disabled.
0x1 : B_0x1
Trigger interrupt enabled.
End of enumeration elements list.
UDE : Update DMA request enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Update DMA request disabled.
0x1 : B_0x1
Update DMA request enabled.
End of enumeration elements list.
CC1DE : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC1 DMA request disabled.
0x1 : B_0x1
CC1 DMA request enabled.
End of enumeration elements list.
CC2DE : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC2 DMA request disabled.
0x1 : B_0x1
CC2 DMA request enabled.
End of enumeration elements list.
CC3DE : Capture/Compare 3 DMA request enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC3 DMA request disabled.
0x1 : B_0x1
CC3 DMA request enabled.
End of enumeration elements list.
CC4DE : Capture/Compare 4 DMA request enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CC4 DMA request disabled.
0x1 : B_0x1
CC4 DMA request enabled.
End of enumeration elements list.
TDE : Trigger DMA request enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Trigger DMA request disabled.
0x1 : B_0x1
Trigger DMA request enabled.
End of enumeration elements list.
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