IDCODE

DBG_CR (CR)

DBG_APB_FZ1 (APB_FZ1)

DBG_APB_FZ2 (APB_FZ2)

DEV_ID : Device Identifier
bits : 0 - 11 (12 bit)

REV_ID : Revision Identifier
bits : 16 - 31 (16 bit)

DBG_STOP : Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_STANDBY : Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM2_STOP : Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM3_STOP : Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM6_STOP : Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM7_STOP : Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_RTC_STOP : Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_WWDG_STOP : Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_IWDG_STOP : Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_I2C1_SMBUS_TIMEOUT : SMBUS timeout when core is halted
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_LPTIM2_STOP : Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_LPTIM1_STOP : Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM1_STOP : Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM14_STOP : Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM15_STOP : Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM16_STOP : Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBG_TIM17_STOP : Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.