Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNGEN : True random number generator enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated.
0x1 : B_0x1
True random number generator is enabled.
End of enumeration elements list.
IE : Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RNG Interrupt is disabled
0x1 : B_0x1
RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or CEIS=1 in the RNG_SR register.
End of enumeration elements list.
CED : Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Clock error detection is enable
0x1 : B_0x1
Clock error detection is disable
End of enumeration elements list.
status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRDY : Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The RNG_DR register is not yet valid, no random data is available.
0x1 : B_0x1
The RNG_DR register contains valid random data.
End of enumeration elements list.
CECS : Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
0x1 : B_0x1
The RNG clock is too slow (fRNGCLK< fHCLK/32).
End of enumeration elements list.
SECS : Seed error current status One of the noise source has provided more than 64 consecutive bits at a constant value (â0â or â1â), or more than 32 consecutive occurrence of two bit patterns (â01â or â10â) Both noise sources have delivered more than 32 consecutive bits at a constant value (â0â or â1â), or more than 16 consecutive occurrence of two bit patterns (â01â or â10â)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
0x1 : B_0x1
At least one of the following faulty sequence has been detected:
End of enumeration elements list.
CEIS : Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
The RNG clock is correct (fRNGCLK> fHCLK/32)
0x1 : B_0x1
The RNG has been detected too slow (fRNGCLK< fHCLK/32)
End of enumeration elements list.
SEIS : Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No faulty sequence detected
0x1 : B_0x1
At least one faulty sequence has been detected. See SECS bit description for details.
End of enumeration elements list.
data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RNDATA : Random data
bits : 0 - 31 (32 bit)
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